Scribd
Upload
146 views9 pages

VHDL Code For A D Flip Flop

The document contains VHDL code for several digital logic components including D flip-flops, JK flip-flops, multiplexers, counters, adders, and state machines. The code uses if/else statements and case statements to define the logic functions and state transitions of each component based on input signals and clock edges.

Uploaded by

Yogesh Khollam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
146 views9 pages

VHDL Code For A D Flip Flop

The document contains VHDL code for several digital logic components including D flip-flops, JK flip-flops, multiplexers, counters, adders, and state machines. The code uses if/else statements and case statements to define the logic functions and state transitions of each component based on input signals and clock edges.

Uploaded by

Yogesh Khollam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 9

VHDL code for a D Flip Flop

process (signal names)


begin
if (clockevent and clock = 1) then
output <= data;
end if;
end process

VHDL code for a D Flip Flop with Reset and Clear

if reset = 0 then
output <= 0;
elsif set = 0 then
output <= 1;
elsif (clockevent and clock = 1) then
output <= data;
end if;

VHDL code for a D Flip Flop

if (clockevent and clock = 0) then


if (reset = 0 and data = 0) then
output <= 0;
elsif (reset = 0 and data = 1) then
output <= 0;
elsif (reset = 1 and data = 0) then
output <= 0;
elsif (reset = 1 and data = 1) then

output <= 1;
end if;

VHDL code for a JK Flip Flop

if (clockevent and clock = 1) then


if (in1 = 0 and in2 = 0) then
output <= output;
elsif (in1 = 1 and in2 = 0) then
output <= 1;
elsif (in1 = 0 and in2 = 1) then
output <= 0;
elsif (in1 = 1 and in2 = 1) then
output <= not(output);
end if;
end if;

VHDL code for a 2-to-1 Mux

if sel = 0 then
output <= data1;
elsif sel = 1 then
output <= data2;
end if;

VHDL code for a Serial to Parallel Converter

if clear = 0 then
shift_reg <= 00000000;
elsif (clockevent and clock = 1) then
shift_reg(7 downto 1) <= (6 downto 0);
shift_reg(0) <= serial;
end if;

VHDL code for a Parallel to Serial Converter

if load = 0 then
shift_reg <= parallel;
elsif (clockevent and clock = 1) then
serial <= shift_reg(7);
shift_reg(7 downto 1) <= (6 downto 0);
end if;

VHDL code for a 4 bit Counter

if load = 0 then
output <= 1111;
elsif (clockevent and clock = 1) then
output <= data - 1;
end if;
carry <= 0 when output = 0000 else 1;
load <= carry;

VHDL code for a 1 bit Adder

if c = 0 then
if (a and b) = 1 then
sum <= 0;
carry <= 1;
elsif (a or b) = 1 then
sum <= 1;
carry <= 0
end if;
elsif c = 1 then
if (a and b) = 1 then
sum <= 1;
carry <= 1;
elsif (a or b) = 1 then
sum <= 0;
carry <= 1;
end if;
end if;

VHDL code for a State Machine

if reset = 0 then
state <= stateA;
output <= 0;
elsif (clockevent and clock) = 1 then
case state is
when stateA
output <= 0;
state <= stateB
when stateB
output <= 1;
if input = 1 then
state <= stateB;
else

state <=stateC;
end if;
when stateC
output <= 0
state <= stateA;
end case;
IEEE-1076: Standard VHDL Language Reference Manual IEEE Compute
VHDL code for a D Flip Flop

process (signal names)


begin
if (clockevent and clock = 1) then
output <= data;
end if;
end process

VHDL code for a D Flip Flop with Reset and Clear

if reset = 0 then
output <= 0;
elsif set = 0 then
output <= 1;
elsif (clockevent and clock = 1) then
output <= data;
end if;

VHDL code for a D Flip Flop

if (clockevent and clock = 0) then


if (reset = 0 and data = 0) then
output <= 0;
elsif (reset = 0 and data = 1) then
output <= 0;
elsif (reset = 1 and data = 0) then
output <= 0;
elsif (reset = 1 and data = 1) then
output <= 1;
end if;

VHDL code for a JK Flip Flop

if (clockevent and clock = 1) then


if (in1 = 0 and in2 = 0) then
output <= output;
elsif (in1 = 1 and in2 = 0) then
output <= 1;
elsif (in1 = 0 and in2 = 1) then
output <= 0;
elsif (in1 = 1 and in2 = 1) then
output <= not(output);
end if;
end if;

VHDL code for a 2-to-1 Mux

if sel = 0 then
output <= data1;
elsif sel = 1 then
output <= data2;
end if;

VHDL code for a Serial to Parallel Converter

if clear = 0 then
shift_reg <= 00000000;
elsif (clockevent and clock = 1) then
shift_reg(7 downto 1) <= (6 downto 0);
shift_reg(0) <= serial;
end if;

VHDL code for a Parallel to Serial Converter

if load = 0 then
shift_reg <= parallel;
elsif (clockevent and clock = 1) then
serial <= shift_reg(7);
shift_reg(7 downto 1) <= (6 downto 0);
end if;

VHDL code for a 4 bit Counter

if load = 0 then
output <= 1111;
elsif (clockevent and clock = 1) then
output <= data - 1;
end if;
carry <= 0 when output = 0000 else 1;
load <= carry;

VHDL code for a 1 bit Adder

if c = 0 then
if (a and b) = 1 then
sum <= 0;
carry <= 1;
elsif (a or b) = 1 then
sum <= 1;
carry <= 0
end if;
elsif c = 1 then
if (a and b) = 1 then
sum <= 1;
carry <= 1;
elsif (a or b) = 1 then
sum <= 0;
carry <= 1;
end if;
end if;

VHDL code for a State Machine

if reset = 0 then
state <= stateA;
output <= 0;
elsif (clockevent and clock) = 1 then
case state is
when stateA
output <= 0;
state <= stateB
when stateB
output <= 1;
if input = 1 then

state <= stateB;


else
state <=stateC;
end if;
when stateC
output <= 0
state <= stateA;
end case;
IEEE-1076: Standard VHDL Language Reference Manual IEEE Compute

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy