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Sumador 16 Bit

This document describes a 16-bit binary adder circuit. It contains two main components: 1. The ADD16 entity which defines the top-level adder port connections and contains a for generate loop to cascade 16 1-bit full adder cells. 2. The FULL_ADDER component which defines a 1-bit full adder logic that computes the sum and carry out signals from two 1-bit inputs and a carry in.

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Percy Julio Chambi Pacco
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163 views2 pages

Sumador 16 Bit

This document describes a 16-bit binary adder circuit. It contains two main components: 1. The ADD16 entity which defines the top-level adder port connections and contains a for generate loop to cascade 16 1-bit full adder cells. 2. The FULL_ADDER component which defines a 1-bit full adder logic that computes the sum and carry out signals from two 1-bit inputs and a carry in.

Uploaded by

Percy Julio Chambi Pacco
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SUMADOR COMPLETO DE 2 NÚMEROS 16 BIT

 Estilo estructural
 Sentencia For…Generate

LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY ADD16 IS
PORT(A,B:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CI:IN STD_LOGIC;
C0:OUT STD_LOGIC);
END ADD16;

ARCHITECTURE BEHAVIORAL OF ADD16 IS

SIGNAL SC:STD_LOGIC_VECTOR(14 DOWNTO 0);

COMPONENT FULL_ADDER
PORT(CI,A,B:IN STD_LOGIC;
S,C0:OUT STD_LOGIC);
END COMPONENT;

BEGIN
U0:FULL_ADDER PORT MAP(CI,A(0),B(0),S(0),SC(0));
U1_U14:FOR I IN 1 TO 14 GENERATE
U:FULL_ADDER PORT MAP(SC(I-1),A(I),B(I),S(I),SC(I));
END GENERATE;
U16:FULL_ADDER PORT MAP(SC(14),A(15),B(15),S(15),C0);

END BEHAVIORAL;
Component FULL ADDER

 Sumador completo de 2 números de 1 bit

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY FULL_ADDER IS
PORT(CI,A,B:IN STD_LOGIC;
S,C0:OUT STD_LOGIC);
END FULL_ADDER;

ARCHITECTURE BEHAVIORAL OF FULL_ADDER IS

BEGIN
S<=A XOR B XOR CI;
C0<=(A AND B) OR (A AND CI) OR (B AND CI);

END BEHAVIORAL;

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