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A4 Coa 2021itb050

The document contains VHDL code for various digital components including a half adder, a 1-bit magnitude comparator, a 1-bit full adder, and a full subtractor, along with their respective testbench codes. Each component is defined with its entity and architecture, and the testbenches provide stimulus for testing the functionality of these components. The design codes implement the logic for each component, demonstrating basic digital design principles.

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Lavneesh Sharma
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5 views9 pages

A4 Coa 2021itb050

The document contains VHDL code for various digital components including a half adder, a 1-bit magnitude comparator, a 1-bit full adder, and a full subtractor, along with their respective testbench codes. Each component is defined with its entity and architecture, and the testbenches provide stimulus for testing the functionality of these components. The design codes implement the logic for each component, demonstrating basic digital design principles.

Uploaded by

Lavneesh Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ANANYA DE/2021ITB050/ASSIGNMENT 4

HALF ADDER
TESTBENCH CODE

library IEEE;
use IEEE.std_logic_1164.all;

entity HalfAdder is
-- empty
end HalfAdder;

architecture tb of HalfAdder is

-- DUT component
component half_adder is
port(
a: in std_logic;
b: in std_logic;
sum: out std_logic;
carry: out std_logic);
end component;

signal a_in, b_in, sum_out, carry_out: std_logic;

begin

-- Connect DUT
DUT: half_adder port map(a_in, b_in, sum_out, carry_out);

process
begin
a_in <= '0';
b_in <= '0';
wait for 1 ns;

a_in <= '0';


b_in <= '1';
wait for 1 ns;
a_in <= '1';
b_in <= '0';
wait for 1 ns;

a_in <= '1';


b_in <= '1';
wait for 1 ns;

-- Clear inputs
a_in <= '0';
b_in <= '0';

wait;
end process;
end tb;

DESIGN CODE

library IEEE;
use IEEE.std_logic_1164.all;

entity half_adder is
port(
a: in std_logic;
b: in std_logic;
sum: out std_logic;
carry: out std_logic);
end half_adder;

architecture behavioural of half_adder is


begin
process(a, b) is
begin
sum <= a xor b;
carry <= a and b;
end process;
end behavioural;

1-bit Magnitude Comparator


TESTBENCH CODE

library IEEE;
use IEEE.std_logic_1164.all;

entity tb_Comp_1bit is
-- empty
end tb_Comp_1bit;

architecture behaviour of tb_Comp_1bit is

-- DUT component
component comparator_1bit is
port(
A: IN std_logic;
B : IN std_logic;
G : OUT std_logic;
L : OUT std_logic;
E : OUT std_logic);
end component;

signal A : std_logic:= '0';


signal B : std_logic:= '0';

signal G : std_logic;
signal L : std_logic;
signal E : std_logic;

begin

-- Connect DUT
DUT: comparator_1bit port map(
A =>A, B=> B,
G=> G,
L =>L,
E=> E);

process
begin
A <= '0', '1' after 400ns, '0' after 800ns;
B <= '0', '1' after 200ns, '0' after 400ns , '1' after 600ns, '0' after 800ns;
wait;

end process;
END;

DESIGN CODE

library IEEE;
use IEEE.std_logic_1164.all;

entity comparator_1bit is
port(
A, B: in std_logic;
G,L,E: out std_logic);
end comparator_1bit;

architecture behavioral of comparator_1bit is

begin
process (A, B)
begin

G <= '0';
L <= '0';
E <= '0';
if(A < B) then
L <='1';
elsif(A > B) then
G <='1';
else
E <='1';
end if;
end process;
end behavioral;

1-bit Full Adder


TESTBENCH CODE

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY onebitadd IS
END onebitadd;

ARCHITECTURE behavior OF onebitadd IS

-- Component Declaration for the Unit Under Test (UUT)


COMPONENT onebitfulladder
PORT(
a : IN std_logic;
b : IN std_logic;
cin : IN std_logic;
s : OUT std_logic;
cout : OUT std_logic
);
END COMPONENT;

--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
signal cin : std_logic := '0';

--Outputs
signal s : std_logic;
signal cout : std_logic;
BEGIN
uut: onebitfulladder PORT MAP (
a => a,
b => b,
cin => cin,
s => s,
cout => cout
);

-- Stimulus process
stim_proc: process
begin
-- insert stimulus here
a<='0','1' after 100 ns, '1' after 200 ns, '0' after 300 ns,'1' after 400 ns;
b<='0','1' after 100 ns, '1' after 150 ns, '0' after 400 ns,'1' after 500 ns;
wait;
end process;

END;

---------------------------------------------------------------------------------------------------------
DESIGN CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity onebitfulladder is
Port ( a,b,cin : in STD_LOGIC;
s,cout : out STD_LOGIC);
end onebitfulladder;

architecture Behavioral of onebitfulladder is

begin
s<= a xor b xor cin;
cout<= (a and b) or ((a xor b )and cin);

end Behavioral;

FULL SUBTRACTOR
TESTBENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_sub_tb is
end entity;

architecture tb of full_sub_tb is
component FULLSUBTRACTOR_BEHAVIORAL_SOURCE is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC_VECTOR (1 downto 0));
end component;
signal A: STD_LOGIC_VECTOR(2 downto 0);
signal Y: STD_LOGIC_VECTOR(1 downto 0);

begin

uut: FULLSUBTRACTOR_BEHAVIORAL_SOURCE port map(


A => A, Y => Y);

stim:process
begin

A <= "000";
wait for 20 ns;

A <= "001";
wait for 20 ns;

A <= "010";
wait for 20 ns;

A <= "011";
wait for 20 ns;

A <= "100";
wait for 20 ns;

A <= "101";
wait for 20 ns;

A <= "110";
wait for 20 ns;

A <= "111";
wait for 20 ns;
wait;

end process;

end tb;
DESIGN CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLSUBTRACTOR_BEHAVIORAL_SOURCE is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC_VECTOR (1 downto 0));
end FULLSUBTRACTOR_BEHAVIORAL_SOURCE;
architecture Behavioral of FULLSUBTRACTOR_BEHAVIORAL_SOURCE is
begin
process (A)
begin
if (A = "001" or A = "010" or A = "111") then
Y <= "11";
elsif (A = "011") then
Y <= "01";
elsif (A = "100") then
Y <= "10";
else
Y <= "00";
end if;
end process;
end Behavioral;

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