PIC18FXX2/XX8

Flash Microcontroller Programming Specification

1.0 DEVICE OVERVIEW 2.1 Hardware Requirements
This document includes the programming specifica- In high voltage ICSP mode, the PIC18FXX2/XX8
tions for the following devices: requires two programmable power supplies: one for
VDD and one for MCLR/VPP. Both supplies should have
• PIC18F242
a minimum resolution of 0.25V. Refer to Section 6.0 for
• PIC18F248 additional hardware parameters.
• PIC18F252
• PIC18F258 2.1.1 LOW VOLTAGE ICSP
• PIC18F442 PROGRAMMING
• PIC18F448 In low voltage ICSP mode, the PIC18FXX2/XX8 can be
• PIC18F452 programmed using a VDD source in the operating
• PIC18F458 range. This only means that MCLR/VPP does not have
to be brought to a different voltage, but can instead be
left at the normal operating voltage. Refer to
2.0 PROGRAMMING OVERVIEW Section 6.0 for additional hardware parameters.
OF THE PIC18FXX2/XX8
2.2 Pin Diagrams
The PIC18FXX2/XX8 can be programmed using the
high voltage In-Circuit Serial ProgrammingTM (ICSPTM) The pin diagrams for the PIC18FXX2/XX8 family are
method, or the low voltage ICSP method. Both of these shown in Figure 2-1. The pin descriptions of these dia-
can be done with the device in the users’ system. The grams do not represent the complete functionality of
low voltage ICSP method is slightly different than the the device types. Users should refer to the appropriate
high voltage method, and these differences are noted device data sheet for complete pin descriptions.
where applicable. This programming specification
applies to PIC18FXX2/XX8 devices in all package
types.

TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18FXX2/XX8

During Programming
Pin Name
Pin Name Pin Type Pin Description

MCLR/VPP VPP P Programming Enable

VDD VDD P Power Supply
Vss VSS P Ground
RB5 PGM I Low Voltage ICSP™ Input when LVP Configuration bit equals ‘1’(1)
RB6 SCLK I Serial Clock
RB7 SDATA I/O Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: See Section 5.3 for more detail.

 2010 Microchip Technology Inc. DS39576C-page 1

PIC18FXX2/XX8
FIGURE 2-1: PIC18FXX2/XX8 FAMILY PIN DIAGRAMS

MCLR/VPP 1 28 RB7 MCLR/VPP 1 40 RB7

RA0 2 27 RB6 RA0 2 39 RB6

PIC18F2X2/8 28L SOIC

PIC18F2X2/8 28L DIP
RA1 3 26 RB5 RA1 3 38 RB5
RA2 4 25 RB4 RA2 4 37 RB4
RA3 5 24 RB3 RA3 5 36 RB3

PIC18F4X2/8 40L DIP

RA4 6 23 RB2 RA4 6 35 RB2
RA5 7 22 RB1 RA5 7 34 RB1
VSS 8 21 RB0 RE0 8 33 RB0
OSC1 9 20 VDD RE1 9 32 VDD
OSC2 10 19 VSS RE2 10 31 VSS
RC0 11 18 RC7 VDD 11 30 RD7
RC1 12 17 RC6 VSS 12 29 RD6
RC2 13 16 RC5 OSC1 13 28 RD5
RC3 14 15 RC4 OSC2 14 27 RD4
RC0 15 26 RC7
RC1 16 25 RC6
MCLR/VPP

RC2 17 24 RC5
RC3 18 23 RC4
RA3
RA2
RA1
RA0

RB7
RB6
RB5
RB4

RD0 RD3
NC

NC

19 22
RD1 20 21 RD2
6
5
4
3
2
1
44
43
42
41
40

RA4 7 39 RB3
RA5 8 38 RB2
RE0 9 PIC18F4X2 37 RB1
RE1 10 36 RB0
RE2 11 PIC18F4X8 35 VDD

RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
12 34

NC
VDD VSS
VSS 13 33 RD7
OSC1 14 44L PLCC 32 RD6
OSC2 15 31 RD5
RC0 16 30 RD4
NC 171 29 RC7
19
20
21
22
23
24
25
26
27
28
8

44
43
42
41
40
39
38
37
36
35
34
RC7 1 33 NC
RD4 2 32 RC0
RD5 3 PIC18F4X2 31 OSC2
RC1
RC2
RC3
RD0
RD1
RD2
RD3
RC4
RC5
RC6
NC

RD6 4 30 OSC1
RD7 5 PIC18F4X8 29 VSS
VSS 6 28 VDD
VDD 7 27 RE2
44L QFP RE1
RB0 8 26
RB1 9 25 RE0
RB2 10 24 RA5
RB3 11 23 RA4
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0

12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34

33 OSC2
NC
NC
RB4
RB5
RB6
RB7
MCLR/VPP
RA0
RA1
RA2
RA3

RC7 1
RD4 2 32 OSC1
RD5 3 31 VSS
RD6 4 PIC18F4X2 30 AVSS
RD7 5 29 VDD
PIC18F4X8 28 VDD
VSS 6
VDD 7 27 RE2
AVDD 8 44L QFN 26 RE1
RB0 9 25 RE0
RB1 10 24 RA5
RB2 11 23 RA4
12
13
14
15
16
17
18
19
20
21
22
RB3
NC
RB4
RB5
RB6
RB7
MCLR/VPP
RA0
RA1
RA2
RA3

Note: Not all multiplexed pin definitions are shown. Refer to the appropriate data sheet for complete pin descriptions.

DS39576C-page 2  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
2.3 Memory Map TABLE 2-2: IMPLEMENTATION OF CODE
MEMORY
The code memory space extends from 0000h to 7FFFh
(32 Kbytes) in four, 8-Kbyte panels. Addresses 0000h Code Memory Size
Device
through 01FFh, however, define a “Boot Block” region (Bytes)
that is treated separately from Panel 1. All code PIC18F242
memory is on-chip. 0000h - 3FFFh (16K)
PIC18F248
In addition to the code memory space, there are three
PIC18F252
blocks in the configuration and ID space that are acces- 0000h - 7FFFh (32K)
sible to the user through Table Reads and Table Writes. PIC18F258
Their locations in the memory map are shown in PIC18F442
Figure 2-3. 0000h - 3FFFh (16K)
PIC18F448
PIC18F452
0000h - 7FFFh (32K)
PIC18F458

FIGURE 2-2: CODE MEMORY SPACE FOR PIC18FXX2/XX8 DEVICES

MEMORY SIZE / DEVICE

Block Code Protection
16 Kbytes 32 Kbytes Address Controlled By:
(PIC18FX42) (PIC18FX52) Range

000000h
Boot Block Boot Block CPB, WRTB, EBTRB
0001FFh
000200h
Block 0 Block 0 CP0, WRT0, EBTR0
001FFFh
002000h
Block 1 Block 1 CP1, WRT1, EBTR1
003FFFh
004000h
Unimplemented
Block 2 CP2, WRT2, EBTR2
Read ‘0’s
005FFFh
006000h
Unimplemented
Block 3 CP3, WRT3, EBTR3
Read ‘0’s
007FFFh
008000h

Unimplemented Unimplemented
Read ‘0’s Read ‘0’s (Unimplemented Memory Space)

1FFFFFh

 2010 Microchip Technology Inc. DS39576C-page 3

PIC18FXX2/XX8
Users may store identification information (ID) in eight 2.3.1 MEMORY ADDRESS POINTER
ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations Memory in the address space 000000h to 3FFFFFh is
read out normally, even after code protection is applied. addressed via the Table Pointer, which is comprised of
three pointer registers:
Locations 300001h through 30000Dh are reserved for
the configuration bits. These bits may be set to select • TBLPTRU, at address 0FF8h
various device options, and are described in • TBLPTRH, at address 0FF7h
Section 5.0. These configuration bits read out normally • TBLPTRL, at address 0FF6h
even after code protected.
Locations 3FFFFEh and 3FFFFFh are reserved for the TBLPTRU TBLPTRH TBLPTRL
device ID bits. These bits may be used by the program-
Addr[21:16] Addr[15:8] Addr[7:0]
mer to identify what device type is being programmed,
and are described in Section 5.0. These configuration The 4-bit command, ‘0000’ (Core Instruction), is used
bits read out normally even after code protection. to load the Table Pointer prior to using many Read or
Write operations.

FIGURE 2-3: CONFIGURATION AND ID LOCATIONS FOR PIC18FXX2/XX8 DEVICES

000000h
Code Memory
01FFFFh ID Location 1 200000h
ID Location 2 200001h
ID Location 3 200002h
ID Location 4 200003h
ID Location 5 200004h
ID Location 6 200005h
Unimplemented
Read as ‘0’ ID Location 7 200006h
ID Location 8 200007h

CONFIG1L 300000h
CONFIG1H 300001h
CONFIG2L 300002h
CONFIG2H 300003h
1FFFFFh CONFIG3L 300004h
CONFIG3H 300005h
Configuration CONFIG4L 300006h
and ID CONFIG4H 300007h
Space CONFIG5L 300008h
CONFIG5H 300009h
CONFIG6L 30000Ah
2FFFFFh CONFIG6H 30000Bh
CONFIG7L 30000Ch
CONFIG7H 30000Dh

Device ID1 3FFFFEh

Device ID2 3FFFFFh

3FFFFFh

Note: Sizes of memory areas are not to scale.

DS39576C-page 4  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
2.4 High Level Overview of the FIGURE 2-5: HIGH LEVEL
Programming Process PROGRAMMING FLOW
Figure 2-5 shows the high level overview of the pro- Start
gramming process. First, a bulk erase is performed.
Next, the code memory, ID locations, and data
EEPROM are programmed. These memories are then Perform Bulk
Erase
verified to ensure that programming was successful. If
no errors are detected, the configuration bits are then
programmed and verified.
Program Memory
2.5 Entering High Voltage ICSP
Program/Verify Mode
Program IDs
The High Voltage ICSP Program/Verify mode is
entered by holding SCLK and SDATA low, and then
raising MCLR/VPP to VIHH (high voltage). Once in this
mode, the code memory, data EEPROM, ID locations, Program Data
and configuration bits can be accessed and
programmed in serial fashion.
The sequence that enters the device into the Program- Verify Program
ming/Verify mode places all unused I/Os in the high
impedance state.

2.5.1 ENTERING LOW VOLTAGE ICSP Verify IDs

PROGRAM/VERIFY MODE
When the LVP configuration bit is ‘1’ (see Section 5.3), Verify Data
the Low Voltage ICSP mode is enabled. Low Voltage
ICSP Program/Verify mode is entered by holding SCLK
and SDATA low, placing a logic high on PGM, and then Program
raising MCLR/VPP to VIH. In this mode, the RB5/PGM Configuration Bits
pin is dedicated to the programming function and
ceases to be a general purpose I/O pin.
The sequence that enters the device into the Program- Verify
ming/Verify mode places all unused I/Os in the high Configuration Bits
impedance state.
Done
FIGURE 2-4: ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE FIGURE 2-6: ENTERING LOW VOLTAGE
P13 P12 PROGRAM/ VERIFY MODE
P15 P12
D110
VIH
MCLR/VPP MCLR/VPP

VDD
VDD
SDATA VIH
PGM
SCLK
SDATA
SDATA = Input

SCLK
SDATA = Input

 2010 Microchip Technology Inc. DS39576C-page 5

PIC18FXX2/XX8
2.6 Serial Program/Verify Operation TABLE 2-3: COMMANDS FOR
PROGRAMMING
The SCLK pin is used as a clock input pin and the
SDATA pin is used for entering command bits and data 4-Bit
Description
input/output during serial operation. Commands and Command
data are transmitted on the rising edge of SCLK,
Core Instruction
latched on the falling edge of SCLK, and are Least 0000
(Shift in16-bit instruction)
Significant bit (LSb) first.
Shift out TABLAT register 0010
2.6.1 4-BIT COMMANDS Table Read 1000

All instructions are 20 bits, consisting of a leading 4-bit Table Read, post-increment 1001
command followed by a 16-bit operand, which depends Table Read, post-decrement 1010
on the type of command being executed. To input a Table Read, pre-increment 1011
command, SCLK is cycled four times. The commands
needed for programming and verification are shown in Table Write 1100
Table 2-3. Table Write, post-increment by 2 1101

Depending on the 4-bit command, the 16-bit operand Table Write, post-decrement by 2 1110
represents 16 bits of input data or 8 bits of input data Table Write, start programming 1111
and 8 bits of output data.
Throughout this specification, commands and data are
TABLE 2-4: SAMPLE COMMAND
presented as illustrated in Figure 2-4. The 4-bit com-
mand is shown MSb first. The command operand, or SEQUENCE
“Data Payload”, is shown <MSB><LSB>. Figure 2-7 4-Bit Data
Core Instruction
demonstrates how to serially present a 20-bit Command Payload
command/operand to the device.
1101 3C 40 Table Write,
post-increment by 2
2.6.2 CORE INSTRUCTION
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to setup
registers as appropriate for use with other commands.

FIGURE 2-7: TABLE WRITE, POST INCREMENT TIMING (1101)

P2 P2A
P2B
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
SCLK
P5 P5A

P4

P3

SDATA 1 0 1 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 n n n n

0 4 C 3
4-bit Command 16-bit Data Payload Fetch Next 4-bit Command

SDATA = Input

DS39576C-page 6  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
3.0 DEVICE PROGRAMMING TABLE 3-2: BULK ERASE COMMAND
SEQUENCE
3.1 High Voltage ICSP Bulk Erase 4-Bit Data
Core Instruction
Erasing code or data EEPROM is accomplished by Command Payload
writing an “erase option” to address 3C0004h. Code 0000 0E 3C MOVLW 3Ch
memory may be erased portions at a time, or the user 0000 6E F8 MOVWF TBLPTRU
may erase the entire device in one action. “Bulk Erase” 0000 0E 00 MOVLW 00h
operations will also clear any code protect settings 0000 6E F7 MOVWF TBLPTRH
associated with the memory block erased. Erase 0000 0E 04 MOVLW 04h
options are detailed in Table 3-1. 0000 6E F6 MOVWF TBLPTRL
1100 00 80 Write 80h TO 3C0004h to
TABLE 3-1: BULK ERASE OPTIONS erase entire device.
Description Data 0000 00 00 NOP
0000 00 00 Hold SDATA low until
Chip Erase 80h erase completes.
Erase Data EEPROM 81h
Erase Boot Block 83h FIGURE 3-1: BULK ERASE FLOW
Erase Panel 1 88h
Start
Erase Panel 2 89h
Erase Panel 3 8Ah
Load Address
Erase Panel 4 8Bh Pointer to
3C0004h
The actual Bulk Erase function is a self-timed opera-
tion. Once the erase has started (falling edge of the 4th
SCLK after the WRITE command), serial execution will Write 80h
to Erase
cease until the erase completes (parameter P11). Dur-
Entire Device
ing this time, SCLK may continue to toggle, but SDATA
must be held low.
The code sequence to erase the entire device is shown Delay P11+P10
in Figure 3-2 and the flowchart is show in Figure 3-1. Time

Note: A bulk erase is the only way to reprogram

code protect bits from an on state to an off Done
state.

FIGURE 3-2: BULK ERASE TIMING

P10
1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 1 2 3 4 1 2
SCLK
P5 P5A P5 P5A P11

SDATA 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n n

4-bit Command 16-bit 4-bit Command NOP 4-bit Command Erase Time 16-bit
Data Payload Data Payload

SDATA = Input

 2010 Microchip Technology Inc. DS39576C-page 7

PIC18FXX2/XX8
3.1.1 LOW VOLTAGE ICSP BULK ERASE 3.1.2 ICSP MULTI-PANEL SINGLE ROW
ERASE
When using low voltage ICSP, the part must be sup-
plied by the voltage specified in parameter D111, if a Irrespective of whether high or low voltage ICSP is
bulk erase is to be executed. All other bulk erase details used, it is possible to erase single row (64 bytes of
as described above apply. data) in all panels at once. For example, in the case of
If it is determined that a program memory erase must a 64-Kbyte device (8 panels), 512 bytes through 64
be performed at a supply voltage below the bulk erase bytes in each panel, can be erased simultaneously dur-
limit, refer to the erase methodology described in ing each erase sequence. In this case, the offset of the
Sections 3.1.2 and 3.2.2. erase within each panel is the same (see Figure 3-5).
Multi-Panel Single Row Erase is enabled by appropri-
If it is determined that a data EEPROM erase must be ately configuring the Programming Control register
performed at a supply voltage below the bulk erase located at 3C0006h.
limit, follow the methodology described in Section 3.4
and write ones to the array. The multi-panel single row erase duration is externally
timed and is controlled by SCLK. After a “Start Pro-
gramming” command is issued (4-bit command,
‘1111’), a NOP is issued, where the 4th SCLK is held
high for the duration of the programming time, P9.
After SCLK is brought low, the programming sequence
is terminated. SCLK must be held low for the time spec-
ified by parameter P10 to allow high voltage discharge
of the memory array.
The code sequence to program a PIC18FXX2/XX8
device is shown in Table 3-3. The flowchart shown in
Figure 3-3 depicts the logic necessary to completely
erase a PIC18FXX2/XX8 device. The timing diagram
that details the “Start Programming” command, and
parameters P9 and P10 is shown in Figure 3-6.
Note: The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.

DS39576C-page 8  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
TABLE 3-3: ERASE CODE MEMORY CODE SEQUENCE
4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to config memory.

0000 8E A6 BSF EECON1, EEPGD
0000 8C A6 BSF EECON1, CFGS
0000 86 A6 BSF EECON1, WREN
Step 2: Configure device for multi-panel writes.
0000 0E 3C MOVLW 3Ch
0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 06 MOVLW 06h
0000 6E F6 MOVWF TBLPTRL
1100 00 40 Write 40h to 3C0006h to enable multi-panel erase.
Step 3: Direct access to code memory and enable erase.
0000 8E A6 BSF EECON1, EEPGD
0000 9C A6 BCF EECON1, CFGS
0000 88 A6 BSF EECON1, FREE
0000 6A F8 CLRF TBLPTRU
0000 6A F7 CLRF TBLPTRH
0000 6A F6 CLRF TBLPTRL
Step 4: Erase single row of all panels at an offset.
1111 <DummyLSB> Write 2 dummy bytes and start programming.
<DummyMSB>
0000 00 00 NOP - hold SCLK high for time P9.
Step 5: Repeat step 4, with Address Pointer incremented by 64 until all panels are erased.

FIGURE 3-3: MULTI-PANEL SINGLE ROW ERASE CODE MEMORY FLOW

Start
Addr = 0
Configure
Device for
Multi-Panel Erase

Start Erase Sequence

and Hold SCLK High
Until Done

Addr = Addr + 64

Delay P9 + P10
Time for Erase
to Occur

All
No panels
done?

Yes

Done

 2010 Microchip Technology Inc. DS39576C-page 9

PIC18FXX2/XX8
3.2 Code Memory Programming The programming duration is externally timed and is
controlled by SCLK. After a “Start Programming” com-
Programming code memory is accomplished by first mand is issued (4-bit command, ‘1111’), a NOP is
loading data into the appropriate write buffers and then issued, where the 4th SCLK is held high for the
initiating a programming sequence. Each panel in the duration of the programming time, P9.
code memory space (see Figure 2-2) has an 8-byte
deep write buffer that must be loaded prior to initiating After SCLK is brought low, the programming sequence
a write sequence. The actual memory write sequence is terminated. SCLK must be held low for the time spec-
takes the contents of these buffers and programs the ified by parameter P10 to allow high voltage discharge
associated EEPROM code memory. of the memory array.

Typically, all of the program buffers are written in paral- The code sequence to program a PIC18FXX2/XX8
lel (Multi-Panel Write mode). In other words, in the case device is shown in Figure 3-4. The flowchart shown in
of a 32-Kbyte device (4 panels with an 8-byte buffer per Figure 3-5 depicts the logic necessary to completely
panel), 32 bytes will be simultaneously programmed write a PIC18FXX2/XX8 device.
during each programming sequence. In this case, the Note: The TBLPTR register must contain the
offset of the write within each panel is the same (see same offset value when initiating the pro-
Figure 3-4). Multi-Panel Write mode is enabled by gramming sequence as it did when the
appropriately configuring the programming control write buffers were loaded.
register located at 3C0006h.

DS39576C-page 10  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
FIGURE 3-4: ERASE AND WRITE BOUNDARIES

Panel n
TBLPTR<21:13> = (n – 1)

TBLPTR<2:0> = 7 Erase Region

8-byte Write Buffer

TBLPTR<2:0> = 6 (64 bytes)

TBLPTR<2:0> = 5
TBLPTR<2:0> = 4
TBLPTR<2:0> = 3
TBLPTR<2:0> = 2
TBLPTR<2:0> = 1
TBLPTR<2:0> = 0
Offset = TBLPTR<12:3> Offset = TBLPTR<12:6>

Panel 3
TBLPTR<21:13> = 2

TBLPTR<2:0> = 7 Erase Region

8-byte Write Buffer

TBLPTR<2:0> = 6 (64 bytes)

TBLPTR<2:0> = 5
TBLPTR<2:0> = 4
TBLPTR<2:0> = 3
TBLPTR<2:0> = 2
TBLPTR<2:0> = 1
TBLPTR<2:0> = 0
Offset = TBLPTR<12:3> Offset = TBLPTR<12:6>

Panel 2
TBLPTR<21:13> = 1

TBLPTR<2:0> = 7 Erase Region

8-byte Write Buffer

TBLPTR<2:0> = 6 (64 bytes)

TBLPTR<2:0> = 5
TBLPTR<2:0> = 4
TBLPTR<2:0> = 3
TBLPTR<2:0> = 2
TBLPTR<2:0> = 1
TBLPTR<2:0> = 0
Offset = TBLPTR<12:3> Offset = TBLPTR<12:6>

Panel 1
TBLPTR<21:13> = 0

TBLPTR<2:0> = 7 Erase Region

8-byte Write Buffer

TBLPTR<2:0> = 6 (64 bytes)

TBLPTR<2:0> = 5
TBLPTR<2:0> = 4
TBLPTR<2:0> = 3
TBLPTR<2:0> = 2
TBLPTR<2:0> = 1
TBLPTR<2:0> = 0
Offset = TBLPTR<12:3> Offset = TBLPTR<12:6>

Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL.

 2010 Microchip Technology Inc. DS39576C-page 11

PIC18FXX2/XX8
TABLE 3-4: WRITE CODE MEMORY CODE SEQUENCE
4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to config memory.

0000 8E A6 BSF EECON1, EEPGD

0000 8C A6 BSF EECON1, CFGS
0000 86 A6 BSF EECON1, WREN

Step 2: Configure device for multi-panel writes.

0000 0E 3C MOVLW 3Ch

0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 06 MOVLW 06h
0000 6E F6 MOVWF TBLPTRL
1100 00 40 Write 40h to 3C0006h to enable multi-panel writes.

Step 3: Direct access to code memory.

0000 8E A6 BSF EECON1, EEPGD

0000 9C A6 BCF EECON1, CFGS

Step 4: Load write buffer for Panel 1.

0000 0E <Addr[21:16]> MOVLW <Addr[21:16]>

0000 6E F8 MOVWF TBLPTRU
0000 0E <Addr[15:8]> MOVLW <Addr[15:8]>
0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1100 <LSB><MSB> Write 2 bytes

Step 5: Repeat for Panel 2.

Step 6: Repeat for all but the last panel (N – 1).

Step 7: Load write buffer for last panel.

0000 0E <Addr[21:16]> MOVLW <Addr[21:16]>

0000 6E F8 MOVWF TBLPTRU
0000 0E <Addr[15:8]> MOVLW <Addr[15:8]>
0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1111 <LSB><MSB> Write 2 bytes and start programming
0000 00 00 NOP - hold SCLK high for time P9

To continue writing data, repeat steps 2 through 5, where the Address Pointer is incremented by 8 in each panel at each iteration of
the loop.

DS39576C-page 12  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
FIGURE 3-5: PROGRAM CODE MEMORY FLOW

Start
N=1
LoopCount = 0
Configure
Device for
Multi-Panel Writes

Panel Base Address =

(N – 1) x 2000h
Addr = Panel Base Address
+ (8 x LoopCount)

Load 8 Bytes
N=N+1 to Panel N Write
Buffer at <Addr>

All
No panel buffers
written?

N=1 Yes
LoopCount =
LoopCount + 1 Start Write Sequence
and Hold SCLK
High Until Done

Delay P9+P10 Time

for Write to Occur

No All
locations
done?

Yes

Done

FIGURE 3-6: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111)

P10
1 2 3 4 1 2 3 4 5 6 15 16 1 2 3 4 1 2 3
SCLK P9
P5 P5A

SDATA 1 1 1 1 n n n n n n n n 0 0 0 0 0 0 0

4-bit Command 16-bit Data Payload 4-bit Command Programming Time 16-bit
Data Payload

SDATA = Input

 2010 Microchip Technology Inc. DS39576C-page 13

PIC18FXX2/XX8
3.2.1 SINGLE PANEL PROGRAMMING The minimum amount of code memory that may be
erased at a given time is 64 bytes. Again, the device
The programming example presented in Section 3.2 must be placed in Single Panel Write mode. The
utilizes multi-panel programming. This technique EECON1 register must then be used to erase the
greatly decreases the total amount of time necessary to 64-byte target space prior to writing the data.
completely program a device and is the recommended
method of completely programming a device. When using the EECON1 register to act on code mem-
ory, the EEPGD bit must be set (EECON1<7> = 1) and
There may be situations, however, where it is advanta- the CFGS bit must be cleared (EECON1<6> = 0). The
geous to limit writes to a single panel. In such cases, WREN bit must be set (EECON1<2> = 1) to enable
the user only needs to disable the multi-panel write writes of any sort (e.g., erases), and this must be done
feature of the device by appropriately configuring the prior to initiating a write sequence. The FREE bit must
programming control register located at 3C0006h. be set (EECON1<4> = 1) in order to erase the program
The single panel that will be written will automatically space being pointed to by the Table Pointer. The erase
be enabled, based on the value of the Table Pointer. sequence is initiated by the setting the WR bit
(EECON1<1> = 1). It is strongly recommended that the
Note: For single panel programming, the user
WREN bit be set only when absolutely necessary.
must still fill the 8-byte write buffer for the
given panel. To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
3.2.2 MODIFYING CODE MEMORY bit. This register must be sequentially loaded with 55h
and then, AAh, immediately prior to asserting the WR
All of the programming examples up to this point have bit in order for the write to occur.
assumed that the device is blank prior to programming.
In fact, if the device is not blank, the direction has been The erase will begin on the falling edge of the 4th SCLK
to completely erase the device via a Bulk Erase after the WR bit is set.
operation (see Section 3.1) operation. After the erase sequence terminates, SCLK must still
It may be the case, however, that the user wishes to be held low for the time specified by parameter P10 to
modify only a section of an already programmed allow high voltage discharge of the memory array.
device. In such a situation, erasing the entire device is
not a realistic option.
The minimum amount of data that can be written to the
device is 8 bytes. This is accomplished by placing the
device in Single Panel Write mode (see Section 3.2.1),
loading the 8-byte write buffer for the panel, and then
initiating a write sequence. In this case, however, it is
assumed that the address space to be written already
has data in it (i.e., it is not blank).

DS39576C-page 14  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
TABLE 3-5: MODIFYING CODE MEMORY
4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to config memory.

0000 8E A6 BSF EECON1, EEPGD

0000 8C A6 BSF EECON1, CFGS

Step 2: Configure device for single panel writes.

0000 0E 3C MOVLW 3Ch

0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 06 MOVLW 06h
0000 6E F6 MOVWF TBLPTRL
1100 00 00 Write 00h to 3C0006h to enable single-panel writes.

Step 3: Direct access to code memory.

0000 8E A6 BSF EECON1, EEPGD

0000 9C A6 BCF EECON1, CFGS

Step 4: Set the Table Pointer for the block to be erased.

0000 0E <Addr[21:16]> MOVLW <Addr[21:16]>

0000 6E F8 MOVWF TBLPTRU
0000 0E <Addr[8:15]> MOVLW <Addr[8:15]>
0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL

Step 5: Enable memory writes and setup an erase.

0000 84 A6 BSF EECON1, WREN

0000 88 A6 BSF EECON1, FREE

Step 6: Perform required sequence.

0000 0E 55 MOVLW 55h

0000 6E A7 MOVWF EECON2
0000 0E AA MOVLW 0AAh
0000 6E A7 MOVWF EECON2

Step 7: Initiate erase.

0000 82 A6 BSF EECON1, WR

0000 00 00 NOP

Step 8: Wait for P11+P10 and then disable writes.

0000 94 A6 BCF EECON1, WREN

Step 9: Load write buffer for panel. The correct panel will be selected based on the Table Pointer.

0000 0E <Addr[8:15]> MOVLW <Addr[8:15]>

0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1111 <LSB><MSB> Write 2 bytes and start programming
0000 00 00 NOP - hold SCLK high for time P9

To continue writing data, repeat step 8, where the Address Pointer is incremented by 8 at each iteration of the loop.

 2010 Microchip Technology Inc. DS39576C-page 15

PIC18FXX2/XX8
3.3 Data EEPROM Programming FIGURE 3-7: PROGRAM DATA FLOW
Data EEPROM is accessed one byte at a time via an
Start
Address Pointer, EEADR, and a data latch, EEDATA.
Data EEPROM is written by loading EEADR with the
desired memory location, EEDATA with the data to be Set Address
written, and initiating a memory write by appropriately
configuring the EECON1 and EECON2 registers. A
byte write automatically erases the location and writes Set Data
the new data (erase-before-write).
When using the EECON1 register to perform a data
Enable Write
EEPROM write, the EEPGD bit must be cleared
(EECON1<7> = 0) and the CFGS bit must be cleared
(EECON1<6> = 0). The WREN bit must be set
Unlock Sequence
(EECON1<2> = 1) to enable writes of any sort, and this 55h - EECON2
must be done prior to initiating a write sequence. The AAh - EECON2
write sequence is initiated by the setting the WR bit
(EECON1<1> = 1). It is strongly recommended that the
Start Write
WREN bit be set only when absolutely necessary. Sequence
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR WR bit No
bit. This register must be sequentially loaded with 55h clear?
and then, AAh, immediately prior to asserting the WR
Yes
bit in order for the write to occur.
The write will begin on the falling edge of the 4th SCLK No
Done?
after the WR bit is set.
After the programming sequence terminates, SCLK Yes
must still be held low for the time specified by
Done
parameter P10 to allow high voltage discharge of the
memory array.

FIGURE 3-8: DATA EEPROM WRITE TIMING

P10
1 2 3 4 1 2 15 16 1 2

SCLK
P5 P5A

0 0 0 0 n n
SDATA
4-bit Command BSF EECON1, WR Poll WR bit, Repeat Until Clear 16-bit Data
(see below) Payload

SDATA = Input

1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16
SCLK
P5 P5A P5 P5A

Poll WR bit
0 0 0 0 0 0 0 0
SDATA

4-bit Command MOVF EECON1, W, 0 4-bit Command MOVWF TABLAT Shift Out Data
(see Figure 4-6)

SDATA = Input SDATA = Output

DS39576C-page 16  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
TABLE 3-6: PROGRAMMING DATA MEMORY
4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to data EEPROM.

0000 9E A6 BCF EECON1, EEPGD

0000 9C A6 BCF EECON1, CFGS

Step 2: Set the data EEPROM Address Pointer.

0000 0E <Addr> MOVLW <Addr>

0000 6E A9 MOVWF EEADR
0000 OE <AddrH> MOVLW <AddrH>
0000 6E AA MOVWF EEADRH

Step 3: Load the data to be written.

0000 0E <Data> MOVLW <Data>

0000 6E A8 MOVWF EEDATA

Step 4: Enable memory writes.

0000 84 A6 BSF EECON1, WREN

Step 5: Perform required sequence.

0000 0E 55 MOVLW 0X55

0000 6E A7 MOVWF EECON2
0000 0E AA MOVLW 0XAA
0000 6E A7 MOVWF EECON2

Step 6: Initiate write.

0000 82 A6 BSF EECON1, WR

Step 7: Poll WR bit, repeat until the bit is clear.

0000 50 A6 MOVF EECON1, W, 0

0000 6E F5 MOVWF TABLAT
0010 <LSB><MSB> Shift out data(1)

Step 8: Disable writes.

0000 94 A6 BCF EECON1, WREN

Repeat steps 2 through 8 to write more data.

Note 1: See Figure 4-4 for details on Shift Out Data timing.

 2010 Microchip Technology Inc. DS39576C-page 17

PIC18FXX2/XX8
3.4 ID Location Programming Note: For single panel programming, the user
The ID locations are programmed much like the code must still fill the 8-byte data buffer for the
memory, except that multi-panel writes must be panel.
disabled. The single panel that will be written will auto- Figure 3-7 demonstrates the code sequence required
matically be enabled, based on the value of the Table to write the ID locations.
Pointer. The ID registers are mapped in addresses
200000h through 200007h. These locations read out
normally, even after code protection.

TABLE 3-7: WRITE ID SEQUENCE

4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to config memory.

0000 8E A6 BSF EECON1, EEPGD

0000 8C A6 BSF EECON1, CFGS

Step 2: Configure device for single panel writes.

0000 0E 3C MOVLW 3Ch

0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 06 MOVLW 06h
0000 6E F6 MOVWF TBLPTRL
1100 00 00 Write 00h to 3C0006h to enable single panel writes.

Step 3: Direct access to code memory.

0000 8E A6 BSF EECON1, EEPGD

0000 9C A6 BCF EECON1, CFGS

Step 4: Load write buffer. Panel will be automatically determined by address.

0000 0E 20 MOVLW 20h

0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 00 MOVLW 00h
0000 6E F6 MOVWF TBLPTRL
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1111 <LSB><MSB> Write 2 bytes and start programming
0000 00 00 NOP - hold SCLK high for time P9

In order to modify the ID locations, refer to the

methodology described in Section 3.2.2, “Modifying
Code Memory”. As with code memory, the ID locations
must be erased before modified.

DS39576C-page 18  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
3.5 Boot Block Programming 3.6 Configuration Bits Programming
The Boot Block segment is programmed in exactly the Unlike code memory, the configuration bits are pro-
same manner as the ID locations (see Section 3.4). grammed a byte at a time. The “Table Write, Begin Pro-
Multi-panel writes must be disabled so that only gramming” (4-bit command, ‘1111’) is used, but only
addresses in the range 0000h to 01FFh will be written. 8 bits of the following 16-bit payload will be written. The
The code sequence detailed in Figure 3-7 should be LSB of the payload will be written to even addresses,
used, except that the address data used in “Step 3” will and the MSB will be written to odd addresses. The
be in the range 000000h to 0001FFh. code sequence to program two consecutive
configuration locations is shown in Figure 3-8.

TABLE 3-8: SET ADDRESS POINTER TO CONFIGURATION LOCATION

4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to config memory.

0000 8E A6 BSF EECON1, EEPGD

0000 8C A6 BSF EECON1, CFGS

Step 2: Position the program counter(1).

0000 EF 00 GOTO 100000h

0000 F8 00

Step 3(2): Set Table Pointer for config byte to be written. Write even/odd addresses.

0000 0E 30 MOVLW 30h

0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPRTH
0000 0E 00 MOVLW 00h
0000 6E F6 MOVWF TBLPTRL
1111 <LSB><MSB ignored> Load 2 bytes and start programming
0000 00 00 NOP - hold SCLK high for time P9
0000 2A F6 INCF TBLPTRL
1111 <LSB ignored><MSB> Load 2 bytes and start programming
0000 00 00 NOP - hold SCLK high for time P9

Note 1: If the code protection bits are programmed while the program counter resides in the same block, then the interaction of
code protection logic may prevent further table writes. To avoid this situation, move the program counter outside the
code protection area (e.g., GOTO 100000h).
2: Enabling the write protection of configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of configuration
bits. Always write all the configuration bits before enabling the write protection for configuration bits.

FIGURE 3-9: CONFIGURATION PROGRAMMING FLOW

Start Start

Load Even Load Odd

Configuration Configuration
Address Address

Program Program
LSB MSB

Delay P9 Time Delay P9 Time

for Write for Write

Done Done

 2010 Microchip Technology Inc. DS39576C-page 19

PIC18FXX2/XX8
4.0 READING THE DEVICE The 4-bit command is shifted in LSb first. The Read is
executed during the next 8 clocks, then shifted out on
4.1 Read Code Memory, ID Locations, SDATA during the last 8 clocks, LSb to MSb. A delay of
and Configuration Bits P6 must be introduced after the falling edge of the 8th
SCLK of the operand to allow SDATA to transition from
Code memory is accessed one byte at a time, via the an input to an output. During this time, SCLK must be
4-bit command, ‘1001’ (Table Read, post-increment). held low (see Table 4-1). This operation also
The contents of memory pointed to by the Table Pointer increments the Table Pointer pointer by one, pointing to
(TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the the next byte in code memory for the next read.
Table Latch and then serially output on SDATA. This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to the reading of the ID and configuration registers.

TABLE 4-1: READ CODE MEMORY SEQUENCE

4-Bit
Data Payload Core Instruction
Command

Step 1: Set Table Pointer.

0000 0E <Addr[21:16]> MOVLW Addr[21:16]

0000 6E F8 MOVWF TBLPTRU
0000 0E <Addr[15:8]> MOVLW <Addr[15:8]>
0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL

Step 2: Read memory into Table Latch and then shift out on SDATA, LSb to MSb.

1001 00 00 TBLRD *+

FIGURE 4-1: TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)

1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
SCLK
P5 P6 P5A

P14

SDATA 1 0 0 1 LSb 1 2 3 4 5 6 MSb n n n n

Shift Data Out Fetch Next 4-bit Command

SDATA = Input SDATA = Output SDATA = Input

DS39576C-page 20  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
4.2 Verify Code Memory and ID The Table Pointer must be manually set to 200000h
locations (base address of the ID locations) once the code mem-
ory has been verified. The post-increment feature of
The verify step involves reading back the code memory the Table Read 4-bit command may not be used to
space and comparing against the copy held in the pro- increment the Table Pointer beyond 1FFFFFh.
grammer’s buffer. Memory reads occur a single byte at
a time, so two bytes must be read to compare against
the word in the programmer’s buffer. Refer to
Section 4.1 for implementation details of reading code
memory.

FIGURE 4-2: VERIFY CODE MEMORY FLOW

Start

Set Pointer = 0 Set Pointer = 200000h

Read Low Byte Read Low Byte

Read High Byte Read High Byte

Does Does
No No
word = expect Failure, word = expect Failure,
data? Report data? Report
Error Error
Yes Yes

All All
No No ID locations
code memory
verified? verified?

Yes Yes

Done

 2010 Microchip Technology Inc. DS39576C-page 21

PIC18FXX2/XX8
4.3 Verify Configuration Bits FIGURE 4-3: READ DATA EEPROM
FLOW
A configuration address may be read and output on
SDATA via the 4-bit command, ‘1001’. Configuration
Start
data is read and written in a bytewise fashion, so it is
not necessary to merge two bytes into a word prior to a
compare. The result may then be immediately Set
compared to the appropriate configuration data in the Address
programmer’s memory for verification. Refer to
Section 4.1 for implementation details of reading
configuration data. Read
Byte
4.4 Read Data EEPROM Memory
Data EEPROM is accessed one byte at a time via an Move to TABLAT
Address Pointer, EEADR, and a data latch, EEDATA.
Data EEPROM is read by loading EEADR with the
desired memory location and initiating a memory read
Shift Out Data
by appropriately configuring the EECON1 register. The
data will be loaded into EEDATA, where it may be seri-
ally output on SDATA via the 4-bit command, ‘0010’
(shift out data holding register). A delay of P6 must be No
introduced after the falling edge of the 8th SCLK of the Done?
operand to allow SDATA to transition from an input to
Yes
an output. During this time, SCLK must be held low
(see Figure 4-4). Done
The command sequence to read a single byte of data
is shown in Figure 4-2.

TABLE 4-2: READ DATA EEPROM MEMORY

4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to data EEPROM.

0000 9E A6 BCF EECON1, EEPGD

0000 9C A6 BCF EECON1, CFGS

Step 2: Set the data EEPROM Address Pointer.

0000 0E <Addr> MOVLW <Addr>

0000 6E A9 MOVWF EEADR
0000 OE <AddrH> MOVLW <AddrH>
0000 6E AA MOVWF EEADRH

Step 3: Initiate a memory read.

0000 80 A6 BSF EECON1, RD

Step 4: Load data into the serial data holding register.

0000 50 A8 MOVF EEDATA, W, 0

0000 6E F5 MOVWF TABLAT
0010 <LSB><MSB> Shift Out Data(1)

Note 1: The <LSB> is undefined. The <MSB> is the data.

DS39576C-page 22  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
FIGURE 4-4: SHIFT OUT DATA HOLDING REGISTER TIMING (0010)

1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
SCLK
P5 P6 P5A

P14

SDATA 0 1 0 0 LSb 1 2 3 4 5 6 MSb n n n n

Shift Data Out Fetch Next 4-bit Command

SDATA = Input SDATA = Output SDATA = Input

4.5 Verify Data EEPROM If it is determined that the device is not blank, then the
device should be Bulk Erased (see Section 3.1) before
A data EEPROM address may be read via a sequence any attempt to program is made.
of core instructions (4-bit command, ‘0000’) and then
output on SDATA via the 4-bit command, ‘0010’ (shift Given that “Blank Checking” is merely code and data
out data holding register). The result may then be EEPROM verification with FFh expect data, refer to
immediately compared to the appropriate data in the Section 4.4 and Section 4.2 for implementation details.
programmer’s memory for verification. Refer to
Section 4.4 for implementation details of reading data FIGURE 4-5: BLANK CHECK FLOW
EEPROM.
Start
4.6 Blank Check
The term “Blank Check” means to verify that the device Blank Check Device
has no programmed memory cells. All memories must
be verified: code memory, data EEPROM, ID locations,
and configuration bits. The Device ID registers
(3FFFFEh:3FFFFFh) should be ignored. Is
device Yes
Continue
A “blank” or “erased” memory cell will read as a ‘1’. So, blank?
“Blank Checking” a device merely means to verify that
all bytes read as FFh, except the configuration bits. No
Unused (reserved) configuration bits will read ‘0’ (pro-
Abort
grammed). Refer to Table 5-2 for blank configuration
expect data for the various PIC18FXX2/XX8 devices.

 2010 Microchip Technology Inc. DS39576C-page 23

PIC18FXX2/XX8
5.0 CONFIGURATION WORD 5.3 Low Voltage Programming
(LVP) Bit
The PIC18FXX2/XX8 has several configuration words.
These bits can be set or cleared to select various The LVP bit in configuration register CONFIG4L
device configurations. All other memory areas should enables low voltage ICSP programming. The LVP bit
be programmed and verified prior to setting configura- defaults to a ‘1’ from the factory.
tion words. These bits may be read out normally, even
If Low Voltage Programming mode is not used, the LVP
after read or code protected.
bit can be programmed to a ‘0’ and RB5/PGM becomes
a digital I/O pin. However, the LVP bit may only be pro-
5.1 ID Locations
grammed by entering the High Voltage ICSP mode,
A user may store identification information (ID) in eight where MCLR/VPP is raised to VIHH. Once the LVP bit is
ID locations mapped in 200000h:200007h. It is programmed to a ‘0’, only the High Voltage ICSP mode
recommended that the most significant nibble of each is available and only the High Voltage ICSP mode can
ID be 0Fh. In doing so, if the user code inadvertently be used to program the device.
tries to execute from the ID space, the ID data will
Note 1: The normal ICSP mode is always avail-
execute as NOP.
able, regardless of the state of the LVP bit,
by applying VIHH to the MCLR/VPP pin.
5.2 Device ID Word
2: While in Low Voltage ICSP mode, the RB5
The device ID word for the PIC18FXX2/XX8 is located pin can no longer be used as a general
at 3FFFFEh:3FFFFFh. These bits may be used by the purpose I/O. The RB5 pin should be held
programmer to identify what device type is being pro- low during normal operation to protect
grammed and read out normally, even after code or against inadvertent ICSP mode entry.
read protected.
.

TABLE 5-1: DEVICE ID VALUE

Device ID Value
Device
DEVID2 DEVID1
PIC18F242 04h 100x xxxx
PIC18F248 08h 000x xxxx
PIC18F252 04h 000x xxxx
PIC18F258 08h 010x xxxx
PIC18F442 04h 101x xxxx
PIC18F448 08h 001x xxxx
PIC18F452 04h 001x xxxx
PIC18F458 08h 011x xxxx

DS39576C-page 24  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
TABLE 5-2: PIC18FXX2/XX8 CONFIGURATION BITS AND DEVICE IDS
Erased or
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
“Blank” Value

300000h CONFIG1L — — — — — — — — 0000 0000

300001h CONFIG1H — — OSCEN — — FOSC2 FOSC1 FOSC0 0010 0111
300002h CONFIG2L — — — — BORV1 BORV2 BOREN PWRTE 0000 1111
300003h CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN 0000 1111
300004h CONFIG3L — — — — — — — — 0000 0000
300005h CONFIG3H — — — — — — — CCP2MX* 0000 0001
300006h CONFIG4L BKBUG — — — — LVP — STVREN 1000 0101
300007h CONFIG4H — — — — — — — — 0000 0000
300008h CONFIG5L — — — — CP3 CP2 CP1 CP0 0000 1111
300009h CONFIG5H CPD CPB — — — — — — 1100 0000
30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 0000 1111
30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 1110 0000
30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 0000 1111
30000Dh CONFIG7H — EBTRB — — — — — — 0100 0000
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1
* This bit only applies to the PIC18FXX2 devices.

 2010 Microchip Technology Inc. DS39576C-page 25

PIC18FXX2/XX8
TABLE 5-3: PIC18FXX2/XX8 BIT DESCRIPTION
Configuration
Bit Name Description
Words
OSCEN CONFIG1H Low Power System Clock Option (Timer1) Enable bit
1 = Disabled
0 = Timer1 oscillator system clock option enabled
FOSC2:FOSC0 CONFIG1H Oscillator Selection bits
111 = RC oscillator w/ OSC2 configured as RA6
110 = HS oscillator w/ PLL enabled
101 = EC oscillator w/ OSC2 configured as RA6
100 = RC oscillator w/ OSC2 configured as “divide by 4 clock output”
011 = RC oscillator
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
BORV1:BORV0 CONFIG2L Brown-out Reset Voltage bits
11 = VBOR set to 2.0V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
BOREN CONFIG2L Brown-out Reset Enable bit
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
PWRTEN CONFIG2L Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTPS2:WDTPS0 CONFIG2H Watchdog Timer Postscaler Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
WDTEN CONFIG2H Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
CCP2MX(1) CONFIG3H CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
BKBUG CONFIG4L Background Debugger Enable bit
1 = Background debugger disabled
0 = Background debugger enabled
LVP CONFIG4L Low Voltage Programming Enable bit
1 = Low voltage programming enabled
0 = Low voltage programming disabled
STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit
1 = Stack overflow/underflow will cause RESET
0 = Stack overflow/underflow will not cause RESET
Note 1: This bit only applies to the PIC18FXX2 devices.
2: These bits only apply to the PIC18FX52/X58 devices.

DS39576C-page 26  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
TABLE 5-3: PIC18FXX2/XX8 BIT DESCRIPTION (CONTINUED)
Configuration
Bit Name Description
Words
CP0 CONFIG5L Code Protection bits (code memory area 0200h - 1FFFh)
1 = Code memory not code protected
0 = Code memory code protected
CP1 CONFIG5L Code Protection bits (code memory area 2000h - 3FFFh)
1 = Code memory not code protected
0 = Code memory code protected
CP2(2) CONFIG5L Code Protection bits (code memory area 4000h - 5FFFh)
1 = Code memory not code protected
0 = Code memory code protected
CP3(2) CONFIG5L Code Protection bits (code memory area 6000h - 7FFFh)
1 = Code memory not code protected
0 = Code memory code protected
CPD CONFIG5H Code Protection bits (data EEPROM)
1 = Data EEPROM not code protected
0 = Data EEPROM code protected
CPB CONFIG5H Code Protection bits (boot block, memory area 0000h - 01FFh)
1 = Boot block not code protected
0 = Boot block code protected
WRT0 CONFIG6L Table Write Protection bit (code memory area 0200h - 1FFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRT1 CONFIG6L Table Write Protection bit (code memory area 2000h - 3FFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRT2(2) CONFIG6L Table Write Protection bit (code memory area 4000h - 5FFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRT3(2) CONFIG6L Table Write Protection bit (code memory area 6000h - 7FFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRTD CONFIG6H Table Write Protection bit (data EEPROM)
1 = Data EEPROM not write protected
0 = Data EEPROM write protected
WRTB CONFIG6H Table Write Protection bit (boot block, memory area 0000h - 01FFh)
1 = Boot block not write protected
0 = Boot block write protected
WRTC CONFIG6H Table Write Protection bit (Configuration registers)
1 = Configuration registers not write protected
0 = Configuration registers write protected
Note 1: This bit only applies to the PIC18FXX2 devices.
2: These bits only apply to the PIC18FX52/X58 devices.

 2010 Microchip Technology Inc. DS39576C-page 27

PIC18FXX2/XX8
TABLE 5-3: PIC18FXX2/XX8 BIT DESCRIPTION (CONTINUED)
Configuration
Bit Name Description
Words
EBTR0 CONFIG7L Table Read Protection bit (code memory area 0200h - 01FFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
EBTR1 CONFIG7L Table Read Protection bit (code memory area 2000h - 3FFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
EBTR2(2) CONFIG7L Table Read Protection bit (code memory area 4000h - 5FFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
EBTR3(2) CONFIG7L Table Read Protection bit (code memory area 6000h - 7FFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
EBTRB CONFIG7H Table Read Protection bit (boot block, memory area 0000h - 01FFh)
1 = Boot block not protected from table reads executed in other blocks
0 = Boot block protected from table reads executed in other blocks
DEV10:DEV3 DEVID2 Device ID bits
These bits are used with the DEV2:DEV0 bits in the DEVID1 register to
identify part number.
DEV2:DEV0 DEVID1 Device ID bits
These bits are used with the DEV10:DEV3 bits in the DEVID2 register to
identify part number.
REV4:REV0 DEVID1 These bits are used to indicate the revision of the device.
Note 1: This bit only applies to the PIC18FXX2 devices.
2: These bits only apply to the PIC18FX52/X58 devices.

5.4 Embedding Configuration Word 5.5 Checksum Computation

Information in the HEX File The checksum is calculated by summing the following:
To allow portability of code, a PIC18FXX2/XX8 pro- • The contents of all code memory locations
grammer is required to read the configuration word • The configuration word, appropriately masked
locations from the HEX file. If configuration word infor-
• ID locations
mation is not present in the HEX file, then a simple
warning message should be issued. Similarly, while The Least Significant 16-bits of this sum are the
saving a HEX file, all configuration word information checksum.
must be included. An option to not include the configu- Table 5-4 describes how to calculate the checksum for
ration word information may be provided. When each device.
embedding configuration word information in the HEX
file, it should start at address 300000h. Note 1: The checksum calculation differs depend-
ing on the code protect setting. Since the
Microchip Technology Inc. feels strongly that this
code memory locations read out differently
feature is important for the benefit of the end customer.
depending on the code protect setting, the
table describes how to manipulate the
actual code memory values to simulate the
values that would be read from a protected
device. When calculating a checksum by
reading a device, the entire code memory
can simply be read and summed. The con-
figuration word and ID locations can
always be read.

DS39576C-page 28  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
TABLE 5-4: CHECKSUM COMPUTATION
0xAA at 0
Code Blank
Device Checksum and Max
Protect Value
Address

PIC18F242 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L & C2B4 C20A

0000)+(CFGW1H & 0027)+(CFGW2L + 000F)&(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L & 0000)+(CFGW1H & C491 C437
0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 0003)+(CFGW5H & 00C0)+(CFGW6L &
0003)+(CFGW6H & 00E0)+(CFGW7L & 0003)+(CFGW7H &
0040)+SUM(IDs)
Boot/Panel1/Panel2 (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 028E 289
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 028E 289
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
PIC18F248 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L & C2B3 C209
0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L & 0000)+(CFGW1H & C48F C435
0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0000)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 0003)+(CFGW5H & 00C0)+(CFGW6L &
0003)+(CFGW6H & 00E0)+(CFGW7L & 0003)+(CFGW7H &
0040)+SUM(IDs)
Boot/Panel1/Panel2 (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 028C 287
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 028C 287
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
Legend: Item Description
CFGW = Configuration Word
SUM[a:b] = Sum of locations a to b inclusive
SUM_ID = Bytewise sum of lower four bits of all customer ID locations
+= Addition
&= Bitwise AND

 2010 Microchip Technology Inc. DS39576C-page 29

PIC18FXX2/XX8
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
0xAA at 0
Code Blank
Device Checksum and Max
Protect Value
Address

PIC18F252 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+SUM 82D8 822E

(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+SUM 84B7 845D
(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L +
000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H &
0001)+(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L &
000F)+(CFGW5H & 00C0)+(CFGW6L & 000F)+(CFGW6H &
00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)+SUM(IDs)
Boot/Panel1/Panel2 SUM(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & C2B4 C25A
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H &
0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H & 02A8 02A3
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H &
00C0)+(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L &
000F)+(CFGW7H & 0040)+SUM(IDs)
PIC18F258 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+SUM 82D7 822D
(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0000)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+SUM 84B5 845B
(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L +
000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H &
0000)+(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L &
000F)+(CFGW5H & 00C0)+(CFGW6L & 000F)+(CFGW6H &
00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)+SUM(IDs)
Boot/Panel1/Panel2 SUM(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & C2B2 C258
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0000)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H &
0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H & 02A6 02A1
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H &
00C0)+(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L &
000F)+(CFGW7H & 0040)+SUM(IDs)
Legend: Item Description
CFGW = Configuration Word
SUM[a:b] = Sum of locations a to b inclusive
SUM_ID = Bytewise sum of lower four bits of all customer ID locations
+= Addition
&= Bitwise AND

DS39576C-page 30  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
0xAA at 0
Code Blank
Device Checksum and Max
Protect Value
Address

PIC18F442 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L & C3B4 C20A

0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L & 0000)+(CFGW1H & C491 C437
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 0003)+(CFGW5H & 00C0)+(CFGW6L &
0003)+(CFGW6H & 00E0)+(CFGW7L & 0003)+(CFGW7H &
0040)+SUM(IDs)
Boot/Panel1/Panel2 (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H & 028E 289
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H & 028E 289
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
PIC18F448 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L & C2B3 C209
0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L & 0000)+(CFGW1H & C48F C435
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0000)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 0003)+(CFGW5H & 00C0)+(CFGW6L &
0003)+(CFGW6H & 00E0)+(CFGW7L & 0003)+(CFGW7H &
0040)+SUM(IDs)
Boot/Panel1/Panel2 (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H & 028C 287
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H & 028C 287
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
Legend: Item Description
CFGW = Configuration Word
SUM[a:b] = Sum of locations a to b inclusive
SUM_ID = Bytewise sum of lower four bits of all customer ID locations
+= Addition
&= Bitwise AND

 2010 Microchip Technology Inc. DS39576C-page 31

PIC18FXX2/XX8
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
0xAA at 0
Code Blank
Device Checksum and Max
Protect Value
Address

PIC18F452 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+SUM 82D8 822E

(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+SUM 84B7 845D
(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L +
000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H &
0001)+(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L &
000F)+(CFGW5H & 00C0)+(CFGW6L & 000F)+(CFGW6H &
00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)+SUM(IDs)
Boot/Panel1/Panel2 SUM(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & C2B4 C25A
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H &
0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H & 02A8 02A3
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H &
00C0)+(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L &
000F)+(CFGW7H & 0040)+SUM(IDs)
PIC18F458 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+SUM 82D7 822D
(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0000)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+SUM 84B5 845B
(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L +
000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H &
0000)+(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L &
000F)+(CFGW5H & 00C0)+(CFGW6L & 000F)+(CFGW6H &
00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)+SUM(IDs)
Boot/Panel1/Panel2 SUM(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & C2B2 C258
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0000)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H &
0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H & 02A6 02A1
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H &
00C0)+(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L &
000F)+(CFGW7H & 0040)+SUM(IDs)
Legend: Item Description
CFGW = Configuration Word
SUM[a:b] = Sum of locations a to b inclusive
SUM_ID = Bytewise sum of lower four bits of all customer ID locations
+= Addition
&= Bitwise AND

DS39576C-page 32  2010 Microchip Technology Inc.

 PIC18FXX2/XX8
5.6 Embedding Data EEPROM
Information In the HEX File
To allow portability of code, a PIC18FXX2/XX8
programmer is required to read the data EEPROM
information from the HEX file. If data EEPROM infor-
mation is not present, a simple warning message
should be issued. Similarly, when saving a HEX file, all
data EEPROM information must be included. An option
to not include the data EEPROM information may be
provided. When embedding data EEPROM information
in the HEX file, it should start at address F00000h.
Microchip Technology Inc. believes that this feature is
important for the benefit of the end customer.

 2010 Microchip Technology Inc. DS39576C-page 33

PIC18FXX2/XX8
6.0 AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: 10C to 50C unless otherwise indicated

Param
Sym Characteristic Min Max Units Conditions
No.
D110 VIHH High Voltage Programming Voltage on 9.00 13.25 V
MCLR/VPP
D110A VIHL Low Voltage Programming Voltage on 2.00 5.50 V
MCLR/VPP
D111 VDD Supply Voltage during programming 2.00 5.50 V Normal
programming
4.50 5.50 V Bulk erase
operations
D112 IPP Programming Current on MCLR/VPP — 300 A
D113 IDDP Supply Current during programming — 5 mA
D031 VIL Input Low Voltage VSS 0.2 VSS V
D041 VIH Input High Voltage 0.8 VDD VDD V
D080 VOL Output Low Voltage — 0.6 V IOL = 8.5 mA
D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA
D012 CIO Capacitive loading on I/O pin (SDATA) — 50 pF To meet AC
specifications
P2 Tsclk Serial Clock (SCLK) period 100 — ns VDD = 5.0V
1 — s VDD = 2.0V
P2A TsclkL Serial Clock (SCLK) Low time 40 — ns VDD = 5.0V
400 — ns VDD = 2.0V
P2B TsclkH Serial Clock (SCLK) High time 40 — ns VDD = 5.0V
400 — ns VDD = 2.0V
P3 Tset1 Input Data Setup Time to serial clock  15 — ns
P4 Thld1 Input Data Hold Time from SCLK 15 — ns
P5 Tdly1 Delay between 4-bit command and 20 — ns
command operand
P5A Tdly1a Delay between 4-bit command 20 — ns
operand and next 4-bit command
P6 Tdly2 Delay between last SCLK  of 20 — ns
command byte to first SCLK  of read
of data word
P9 Tdly5 SCLK High time 1 — ms
(minimum programming time)
P10 Tdly6 SCLK Low time after programming 5 — s
(high voltage discharge time)
P11 Tdly7 Delay to allow self-timed data write or 10 — ms
bulk erase to occur
P12 Thld2 Input Data Hold time from 2 — s
MCLR/VPP 
P13 Tset2 VDD Setup time to MCLR/VPP  100 — ns
P14 Tvalid Data Out Valid from SCLK  10 — ns
P15 Tset3 PGM Setup time to MCLR/VPP  2 — s

DS39576C-page 34  2010 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
rfPIC and UNI/O are registered trademarks of Microchip
MICROCHIP MAKES NO REPRESENTATIONS OR
Technology Incorporated in the U.S.A. and other countries.
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip
QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard,
arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
hold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
intellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2010 Microchip Technology Inc. DS39576C-page 35

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01/05/10

DS39576C-page 36  2010 Microchip Technology Inc.