§9 - Metastability and Clock Recovery Asynchronous inputs

‹ We will consider a number of issues related to ‹ Not all inputs are synchronized with the clock
asynchronous inputs, multiple clock domains, clock ‹ Examples:
synchronisation and clock distribution. ™ Keystrokes
‹ Useful references: ™ Sensor inputs
™ Chapter 8, pp757-773, Digital Design Principles & Practices, ™ Data received from a network (transmitter has its own clock)
John Wakerly. ‹ Inputs must be synchronized with the
™ “Metastability in Altera Devices”, Altera App Note 42. system clock before being applied to a synchronous
™ “PLLs in Cyclone II Devices”, Chapter 7 of Cyclone II Manual, system.
Altera
™ “Using the Virtex Delay-Locked Loop”, XAPP-132.

Imperial College, 2007 Digital System Design 9.1 Imperial College, 2007 Digital System Design 9.2

A simple synchronizer Only one synchronizer per input

Imperial College, 2007 Digital System Design 9.3 Imperial College, 2007 Digital System Design 9.4
Even worse The way to do it

‹ One synchronizer per input

‹ Carefully locate the synchronization points in a
system.
‹ Combinational delays to the two synchronizers are
‹ But still a problem -- the synchronizer output may
likely to be different.
become metastable when setup and hold time are
not met.
Imperial College, 2007 Digital System Design 9.5 Imperial College, 2007 Digital System Design 9.6

Recommended synchronizer design Metastability decision window

‹ Hope that FF1 settles down before “META” is sampled.

™ In this case, “SYNCIN” is valid for almost a full
clock period.
™ Can calculate the probability of “synchronizer failure” (FF1 still
metastable when META sampled)

Imperial College, 2007 Digital System Design 9.7 Imperial College, 2007 Digital System Design 9.8
Metastability resolution time Flip-flop metastable behavior
‹ Probability of flip-flop output being in the metastable
state is an exponentially decreasing function of tr (time
since clock edge, i.e. “resolution time”).
‹ Stated another way,

exp (tr / τ )
MTBF (tr ) =
To f a
where
τ and T0 are parameters for a particular flip-flop,
f is the clock frequency, and
a is the number of asynchronous transitions / sec

Imperial College, 2007 Digital System Design 9.9 Imperial College, 2007 Digital System Design 9.10

MTBF versus Resolution Time (tr) Typical flip-flop metastability parameters

MTBF (tr ) =
Changing T0 exp (tr / τ )
To f a

MTBF = 1000 yrs.

Grad = 1/τ
F = 25 MHz
a = 100 KHz
tr = ?

Imperial College, 2007 Digital System Design 9.11 Imperial College, 2007 Digital System Design 9.12
Is 1000 years enough? Multiple-cycle synchronizer

‹ If MTBF = 1000 years and you ship 52,000 copies of

the product, then some system experiences a
mysterious failure every week.
‹ Real-world MTBFs must be much higher.
‹ How to get better MTBFs?
™ Use faster flip-flops
Ê But clock speeds keep getting faster, thwarting this approach.
™ Wait for multiple clock ticks to get a longer metastabilty
resolution time
Ê Waiting longer usually doesn’t hurt performance
Ê …unless there is a critical “round-trip” handshake.
‹ Clock-skew problem

Imperial College, 2007 Digital System Design 9.13 Imperial College, 2007 Digital System Design 9.14

Deskewed multiple-cycle synchronizer Clock Skew

™ Clock signal may not reach all flip-flops simultaneously.
™ Output changes of flip-flops receiving “early” clock may reach D
inputs of flip-flops with “late” clock too soon.

‹ Necessary in really high-speed systems

Reasons for slowness:
‹ DSYNCIN is valid for almost an entire clock period. (a) wiring delays
(b) capacitance
(c) incorrect design

Imperial College, 2007 Digital System Design 9.15 Imperial College, 2007 Digital System Design 9.16
 Clock-skew calculation Example of bad clock distribution

‹ tffpd(min) + tcomb(min) − thold − tskew(max) > 0

‹ First two terms are minimum time after clock edge
that a D input changes
‹ Hold time is earliest time that the input may change
‹ Clock skew subtracts from the available
hold-time margin
‹ Compensating for clock skew:
™ Longer flip-flop propagation delay
™ Explicit combinational delays
™ Shorter (even negative) flip-flop hold times

Imperial College, 2007 Digital System Design 9.17 Imperial College, 2007 Digital System Design 9.18

Multiple Clock Domains Example: Classical clock recovery

‹ Many digital systems have more than one clock ‹ Clocking information embedded in data stream
domains:- ‹ Use PLL to recover the clock
‹ State of system is stored in analog loop filter

‹ Needs to synchronise the two clock domains using two

basic building blocks:
™ Phase-locked loop (PLL)
™ Delay-locked loop (DLL)

Imperial College, 2007 Digital System Design 9.19 Imperial College, 2007 Digital System Design 9.20
 Phase Alignment in Source Synchronous
Oversampled Clock/Data Recovery Systems

‹ Oversample the data and perform phase alignment ‹ Timing information carried by reference clock
digitally ‹ Use DLL to ensure proper clock phase for sampling
‹ De-couples clock generation from tracking of data
‹ Data must guarantee transitions to ensure tracking

Imperial College, 2007 Digital System Design 9.21 Imperial College, 2007 Digital System Design 9.22

What is a Delay locked loop? What is Phase locked loop?

‹ First order loop: ‹ 2nd/3rd order loop:

™ easily stabilized ™ stability could be an issue
™ frequency synthesis is difficult ™ frequency multiplication is easy
™ reference clock jitter passes to output ™ reference clock jitter reduced by filtering
™ no phase error accumulation ™ phase error accumulation
Imperial College, 2007 Digital System Design 9.23 Imperial College, 2007 Digital System Design 9.24
Timing Loop Performance Parameters Clock Management with DLL
‹ Phase Jitter:
‹ Can eliminate on-chip clock delay
™ can also eliminate on-board clock delay
‹ 4 fixed-phase outputs (0°, 90 °, 180 °, 270 °)
‹ Selectable phase shift ( n / 256 of the period)
™ through configuration
™ or through increment/decrement
‹ Phase Offset ™ 1/256 of clock period or 50 picosecond granularity
™ Error between output phase and reference phase ‹ Frequency synthesis (division and multiplication)
‹ Bandwidth ‹ Outputs are always phase-coherent
™ rate at which output phase tracks reference
‹ Acquisition time (to lock)
Solves the speed problem of large chips
‹ Frequency range (lock range)
Imperial College, 2007 Digital System Design 9.25 Imperial College, 2007 Digital System Design 9.26

DLL in Xilinx Virtex data/clock alignment Xilinx DLL with various phase outputs

Imperial College, 2007 Digital System Design 9.27 Imperial College, 2007 Digital System Design 9.28
Using DLL in a standard way Using DLL to de-skew onboard clock signals

Imperial College, 2007 Digital System Design 9.29 Imperial College, 2007 Digital System Design 9.30

Altera Cyclone II PLL (1) Altera Cyclone II PLL (2)

‹ Phase-locked loop (PLL) is a closed-loop frequency-control system ‹ PLL aligns the rising edge of reference input clock to feedback clock using the PFD.
‹ PFD detects difference in phase and frequency between reference clock and
based on the phase difference between the input clock signal and feedback clock and generates an “up” or “down” control signal based on whether
the feedback clock signal of a controlled oscillator. the feedback frequency is lagging or leading the reference frequency.
‹ Main components: ‹ If the charge pump receives an up signal, current is driven into the loop filter,
otherwise, current is drawn from the loop filter.
™ Phase frequency detector (PFD) ‹ Loop filter converts these “up” “down” signals to a control voltage to control the
™ Charge pump & loop filter oscillation frequency of the voltage controlled oscillator (VCO).
™ Voltage controlled oscillator (VCO) ‹ Feedback loop counter (M) is used to increase VCO frequency above input
reference frequency.
™ Counters (N – pre-scale, M – feedback, C – post-scale) ‹ Pre-scale counter (N) is used to produce the reference frequency from FIN.
‹ The post-scale counters (C) allows a number of harmonically related frequencies be
generated from one common clock.

Imperial College, 2007 Digital System Design 9.31 Imperial College, 2007 Digital System Design 9.32
Altera Cyclone II PLL (3)
‹ The output frequency is given by:

Imperial College, 2007 Digital System Design 9.33