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ASIC Design Lab Reports

This document contains lab reports from the ASIC Design Lab at HITEC University Taxila. It includes module descriptions and test benches for various digital logic circuits designed using Verilog, including half adders, full adders, multiplexers, decoders, counters, and multipliers. Lab assignments involve designing basic components like 1-bit and 4-bit adders, and building up to more complex systems like an ALU and binary multiplier. Test benches are provided to verify the functionality of each design.

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0% found this document useful (0 votes)
353 views16 pages

ASIC Design Lab Reports

This document contains lab reports from the ASIC Design Lab at HITEC University Taxila. It includes module descriptions and test benches for various digital logic circuits designed using Verilog, including half adders, full adders, multiplexers, decoders, counters, and multipliers. Lab assignments involve designing basic components like 1-bit and 4-bit adders, and building up to more complex systems like an ALU and binary multiplier. Test benches are provided to verify the functionality of each design.

Uploaded by

Nisar Ahmed Rana
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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HITEC University Taxila

Department of Electrical Engineering


Subject: ASIC Design

ASIC Design Lab Reports

Lab Instructors:
Engr. Fahad Islam Cheema
Engr. Asim Rasheed

Submitted By:
Nisar Ahmed Rana
07-HITEC-EE-94
Sheikh Muhammad Arshad
07-HITEC-EE-113
Muhammad Qaisar Shahzad
07-HITEC-EE-74
Zeeshan Akram Bhatti
07-HITEC-EE-129
LAB # 2
Design a 2-to-1 multiplexer using gate level modeling:
module mux21(Q,A,B,S);
output Q;
input A,B,S;
wire S0,Y0,Y1;
not (S0,S);
and (Y0,A,S0);
and (Y1,B,S);
or (Q,Y0,Y1);
endmodule

a. Design a Half Adder using Gate level modeling

module halfadder(S,C,X,Y);
output S,C;
input X,Y;
xor(S,X,Y);
and (C,X,Y);
endmodule
LAB 3:
Task-1
i) Design a 1-bit Half Adder using data flow
ii) Design 1-bit Full adder using Half Adder in data flow Modeling

Task-2
i) Design a 4-bit Full Adder using 1-bit Full Adder
ii) Design a 4-bit Adder directly (without using 1-bit adder) in data flow modeling
Design simulator for your 4-bit Full Adder and prove it right by using some test cases

Task-1

a. Design a 1-bit Half Adder using data flow


module halfadder(S,C,A,B);
output S,C;
input A,B;
assign S=A^B;
assign C=A&&B;
endmodule

b. Design 1-bit Full adder using Half Adder in data flow Modeling

module FA1bit(Sout,Cout,A,B,Cin);
output Sout,Cout;
input A,B,Cin;
wire S1,C1,C2;
halfadder a1(S1,C1,A,B);
halfadder a3(Sout,C2,S1,Cin);
assign Cout=C1||C2;
endmodule
Task-2

a. Design a 4-bit Full Adder using 1-bit Full Adder


module A4bitUFA1bit(c4,s3,s2,s1,s0,b3,a3,b2,a2,b1,a1,b0,a0,c0);
output c4,s3,s2,s1,s0;
input b3,a3,b2,a2,b1,a1,b0,a0,c0;
wire c3,c2,c1;
FA1bit fa1(s3,c4,b3,a3,c3);
FA1bit fa2(s2,c3,b2,a2,c2);
FA1bit fa3(s1,c2,b1,a1,c1);
FA1bit fa4(s0,c1,b0,a0,c0);
endmodule

b. Design a 4-bit Adder directly (without using 1-bit adder) in data flow modeling
module A4bitdirect(Sout,Cout,A,B,Cin);
output [3:0]Sout;
output Cout;
input [3:0]A,B;
input Cin;
assign {Cout,Sout}=A+B+Cin;
endmodule
LAB 4
ALU:- Test Bench:-
module ALU(num,a,b,c,d); module ALU_ALUtb_v_tf();
output reg [5:0] num;
//reg [5:0] num; // Inputs
input [2:0]a,b; reg [2:0]a; reg [2:0]b; reg c; reg d;
input c,d; // Outputs
always @(a,b) wire [5:0]num;
begin // Instantiate the UUT
case ({c,d}) ALU uut (
00: num=a+b; .num(num),
01: num=a-b; .a(a),
10: num=a*b; .b(b),
11: num=a/b; .c(c),
endcase .d(d)
end );
endmodule // Initialize Inputs

initial begin
a = 3'b111; b = 3'b101; c = 0; d = 1;
end
endmodule

Decoder:- Test Bench:-


module Decoder(q,i1,i2); module Decoder_38_Decoder_tb_38_v_tf();
output reg [3:0] q; // Inputs
input i1,i2; reg i1; reg i2; reg i3;
always // Outputs
case ({i1,i2}) wire [7:0] q;
00: q=0001; Decoder_38 D38(q,i1,i2,i3);
01: q=0010; initial
10: q=0100; begin
11: q=1000; i1=0;
endcase i2=0;
endmodule i3=1;
#100 $display("I1=%b, I2=%b,
I3=%b",i1,i2,i3);
end
endmodule
DFF:- Test Bench:-
module DFF(q,clk,rst); module DFF_DFF_tb_v_tf();
output reg q; wire q;
input clk,rst; reg clk;
always @ (posedge rst or negedge clk) reg rst;
if(rst) initial
q<=1'b0; begin
else clk=1'b0;
q<=~q; rst=1;
endmodule #5 rst=0;
end
always
#5 clk=~clk;
Endmodule
Endmodule
Test Bench:-
Full Adder:- module FA4b_FA4b_tb_v_tf();
module FA4B(S,Cout,A,B,Cin); reg [3:0] i1;reg [3:0] i2;
output [3:0] S; wire [3:0] s;wire c;
output Cout; FA4b Fo(s,c,i1,i2);
input [3:0] A,B; initial begin
input Cin; i1 = 4'b0011;
wire C1,C2,C3; i2 = 4'b0110;
FA F1(S[0],C1,A[0],B[0],Cin); end
FA F2(S[1],C2,A[1],B[1],C1); endmodule
FA F3(S[2],C3,A[2],B[2],C2);
FA F4(S[3],Cout,A[3],B[3],C3);

module Counter_Counttb_v_tf();
Counter:- wire [7:0]q;
module Counter(q,rst,clk); reg clk,rst;
output reg [7:0]q; Counter C1(q,rst,clk);
input rst, clk; initial
always @(negedge clk or posedge rst) begin
begin clk=1'b0;
if(rst) rst=1;
q<=8'b00000000; #5 rst=0;
else end
q<=q+1; always
end #1 clk=~clk;
endmodule Endmodule
Test Bench:-
LAB 6
Half Adder:- assign w8=s[2]&r[1];
module HA(s,cout,a,b); FADF F2(S5,C5,w8,w9,C3);
input a,b; assign p[3]=S5;
output s,cout; assign w10=s[2]&r[2];
assign {cout,s}=a+b; FADF F3(S6,C6,C4,w10,C5);
endmodule assign p[4]=S6;
Full Adder:- assign p[5]=C6;
module FADF(s,cout,a,b,cin); endmodule
output s,cout; Test Bench:-
input a,b,cin;
assign {cout,s}=a+b+cin; module Amul_Amul_tb_v_tf();
endmodule
4 bit Full Adder: // Inputs
module 4bitFADF(Sum,Carry,A,B,Cin); reg [2:0] s;
output [3:0] Sum; reg [2:0] r;
output Carry; // Outputs
input [3:0] A,B; wire [5:0] p;
input Cin;
// Instantiate the UUT
FADF f0(Sum[0],c1,A[0],B[0],Cin); Amul uut (
FADF f1(Sum[1],c2,A[1],B[1],c1); .p(p),
FADF f2(Sum[2],c3,A[2],B[2],c2); .s(s),
FADF f3(Sum[3],cout,A[3],B[3],c3); .r(r)
endmodule );
//Instatiation of a full adder initial begin
module FADF(s,cout,a,b,cin); s = 3'b111;
output s,cout; r = 3'b101;
input a,b,cin; end
assign {cout,s}=a+b+cin; endmodule
endmodule
Q Multiplier:-
Q2:-
module CSAM(p,a,b);
module Amul(p,s,r);
output [6:0] p;
input [2:0] s,r;
input [3:0] a;
output [5:0] p;
input [2:0] b;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11;
wire C1,S1,C2,S2,C3,S3,C4,S4,C5,S5,C6,S6;
wire
assign p[0]=s[0]&r[0];
C1,S1,C2,S2,C3,S3,C4,S4,C5,S5,C6,S6,C7,S7,C8,S
assign w1=s[0]&r[1];
8,C9,S9;
assign w2=s[1]&r[0];
assign p[0]=a[0]&b[0];
HA H1(S1,C1,w1,w2);
assign w1=a[0]&b[1];
assign p[1]=S1;
assign w2=a[1]&b[0];
assign w3=s[0]&r[2];
HA H1(S1,C1,w1,w2);
assign w4=s[1]&r[1];
assign p[1]=S1;
FADF F1(S2,C2,w3,w4,C1);
assign w3=a[1]&b[1];
assign w4=a[2]&b[0];
HA H2(S2,C2,w3,w4);
assign w6=S2;
assign w5=a[0]&b[2];
assign w7=s[2]&r[0];
FADF F1(S3,C3,S2,w5,C1);
HA H2(S3,C3,w6,w7);
assign p[2]=S3;
assign p[2]=S3;
assign w6=a[2]&b[1];
assign w5=s[1]&r[2];
assign w7=a[3]&b[0];
HA H3(S4,C4,w5,C2);
HA H3(S4,C4,w6,w7);
assign w9=S4;
assign w8=a[1]&b[2]; Test Bench:-
FADF F2(S5,C5,w8,S4,C2); module CSAM_CSAM_tb_v_tf();
HA H4(S6,C6,S5,C3);
// Inputs
assign p[3]=S6;
assign w9=a[3]&b[1]; reg [3:0] a;
assign w10=a[2]&b[2]; reg [2:0] b;
FADF F3(S7,C7,w9,w10,C4); // Outputs
FADF F4(S8,C8,S7,C5,C6); wire [6:0] p;
assign p[4]=S8;
assign w11=a[3]&b[2];
// Instantiate the UUT
FADF F5(S9,C9,w11,C7,C8);
assign p[5]=S9;
assign p[6]=C9; CSAM uut (.p(p), .a(a), .b(b) );
endmodule // Initialize Inputs
initial begin
a = 4'b1001;
b = 3'b110;
end
endmodule
LAB 7
Asynchronous Counter:
JK-Flipflop: reg clk;
module jkflipflop(q,j,k,clk); reg j;
output reg q=0; reg k;
input j,k,clk; wire a;
always @(negedge clk) wire b;
case({j,k}) wire c;
2'b00:q<=q; wire d;
2'b01:q<=0; Asyn_counter uut (.a(a), .b(b), .c(c), .d(d), .clk(clk),
2'b10:q<=1; .j(j), .k(k));
2'b11:q<=~q; initial begin
endcase clk = 0;
endmodule forever
Counter Module: #5 clk=~clk;
module Asyn_counter(a,b,c,d,clk,j,k); end
output wire a,b,c,d; initial begin
input clk,j,k; j = 0;
jkflipflop a1(a,j,k,clk); k = 1;
jkflipflop a2(b,j,k,a); #5
jkflipflop a3(c,j,k,b); j = 1;
jkflipflop a4(d,j,k,c); k = 1;
endmodule end
endmodule
TestBench:
module Asyn_counter_testbench1_v_tf();

Synchronous Counter:
Code: TestBench:
module synch_counter(a,b,c,d,clk,j,k); module synch_counter_testbench2_v_tf();
output wire a,b,c,d; reg clk, j, k;
input clk,j,k; wire a, b, c, d;
wire d1,d2; initial begin
jkflipflop x1(a,j,k,clk); clk = 0;
jkflipflop x2(b,a,a,clk); forever
and (d1,a,b); #5 clk=~clk;
jkflipflop x3(c,d1,d1,clk); end
and (d2,a,b,c); initial begin
jkflipflop x4(d,d2,d2,clk); j = 0;
endmodule k = 1;
#5
j = 1;
k = 1;
end
endmodul
LAB 8
IMPLEMENTATION OF HALF ADDER ON FPGA BOARD
HALFADDER:
Code:
module Halfadder(sum,cout,a,b);
output sum;
output cout;
input a;
input b;
assign {cout,sum}=a+b;
endmodule
Assign Package Pins:
Internal Architecture of CLBs Slice:
Lab 9

OBJECTIVE
 Practicing and playing with hardware.
 Design and Implementation of BCD to 7-Segment decoder on Spartan-2 FPGA Kit.
 Design of a 4-bit counter on 7-Segment Display using FPGA Kit.

Verilog Code:
modulecnt(x,q,clk);
inputclk;
output [7:0]q;
output x;
reg [3:0]cnt;
reg [7:0]q=8'b00000000;
reg [23:0]clkcnt=0;
regclkn;

always @ (posedgeclk)
begin
clkcnt=clkcnt+1;
if (clkcnt==20000000)
begin
clkn=~clkn;
clkcnt=0;
end
end

always@(posedgeclkn)
begin
cnt<=cnt+1;
end

assign x=1'b1;
always @ (cnt)

case({cnt})
4'b0000: q=8'b10111111; //0
4'b0001: q=8'b10110000; //1
4'b0010: q=8'b11011011; //2
4'b0011: q=8'b11001111; //3
4'b0100: q=8'b11100110; //4
4'b0101: q=8'b11101101; //5
4'b0110: q=8'b11111101; //6
4'b0111: q=8'b10000111; //7
4'b1000: q=8'b11111111; //8
4'b1001: q=8'b11101111; //9
4'b1010: q=8'b11110111; //A
4'b1011: q=8'b11111111; //B
4'b1100: q=8'b10111001; //C
4'b1101: q=8'b10111111; //D
4'b1110: q=8'b11111001; //E
4'b1111: q=8'b11110001; //F
endcase

endmodule
Lab 10
OBJECTIVE
 Familiarize you with the design of finite state machine (FSM).
 Distinguishing between Moore and Mealy models.
Mealy models

Code TestBench
module FSM1(x,y,clk,rst); module FSM1_testmealay_v_tf();
input x,clk,rst; // Inputs
output reg y; reg x, clk, rst;
reg [1:0]perstate,nxtstate; // Outputs
parameter g0=2'b00,g1=2'b01,g2=2'b10; wire y;
always @(posedge clk or posedge rst) // Instantiate the UUT
//sequebtial block FSM1 uut (.x(x), .y(y), .clk(clk), .rst(rst) );
if(rst) perstate=g0; initial begin
else perstate=nxtstate; clk = 0;
always @(perstate or x) //next state block forever #10 clk = ~clk;
case (perstate) end
g0: if(x) nxtstate=g1; initial begin
else nxtstate=g2; rst = 0;
g1: if(x) nxtstate=g0; forever #50 rst = ~rst;
else nxtstate=g2; end
g2: if(x) nxtstate=g1; initial begin
else nxtstate=g0; x = 0;
endcase #10
always @ (perstate or x) //output block x = 1;
case (perstate) #10
g0:y=0; x = 0;
g1:if(x) y=1'b1; else y=1'b0; #10
g2: if(x) y=1'b0; else y=1'b1; x = 1;
endcase end
endmodule endmodule
Moore model

Code
module FSM2(clk,x,y,rst,perstate);
input x,clk,rst;
output reg y; TestBench
output reg [1:0]perstate=2'b00; module FSM2_test2_v_tf();
reg [1:0]nxtstate; // Inputs
parameter g0=2'b00,g1=2'b01,g2=2'b10,g3=2'b11; reg clk, x, rst;
always @(posedge clk or posedge rst) // Outputs
//sequebtial block wire y;
if(rst) perstate=g0; wire [1:0] perstate;
else perstate=nxtstate;
always @(perstate or x) //next state block
case (perstate) FSM2 uut (.clk(clk), .x(x), .y(y), .rst(rst),
g0: if(x) nxtstate=g1; .perstate(perstate) );
else nxtstate=g2; initial begin
g1: if(x) nxtstate=g3; clk = 0;
else nxtstate=g2; forever #10 clk = ~clk;
g2: if(x) nxtstate=g1; end
else nxtstate=g3; initial begin
g3: if(x) nxtstate=g1; x = 0;
else nxtstate=g2; #10 x = 1;
endcase #10 x = 0;
always @ (perstate) //output block #10 x = 1;
case (perstate) end
g0:y=0; endmodue
g1:y=1'b0;
g2: y=1'b0;
g3: y=1'b1;
endcase
endmodule
LAB 11
Traffic Light Controller
Objectives
 Practice on the design of clocked sequential circuits.
 Introducing practical aspects of logic implementation (switch debouncing, timing constraints etc.).

Code TestBench
module Traffic_controller(clk,x,y,perstate); module Traffic_controller_test1_v_tf();
input [2:0]x; // Inputs
input clk; reg clk;
output reg [2:0]y; reg [2:0] x;
output reg [1:0]perstate=2'b00; // Outputs
reg [1:0]nxtstate; wire [2:0] y;
parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11; wire [1:0] perstate;
// Bidirs
always @(posedge clk) //sequebtial block // Instantiate the UUT
perstate=nxtstate; Traffic_controller uut (
.clk(clk),
always @(perstate or x) //next state block .x(x),
case (perstate) .y(y),
s0: if(x==3'b000) nxtstate=s0; .perstate(perstate)
else if(x==3'b001) nxtstate=s1; );
else if(x==3'b010) nxtstate=s2; initial begin
else if(x==3'b100) nxtstate=s3; clk=0;
s1: if(x==3'b001) nxtstate=s1; forever #10 clk = ~clk;
else nxtstate=s0; end
s2: if(x==3'b010) nxtstate=s2; initial begin
else nxtstate=s0; x=3'b000;
s3: if(x==3'b100) nxtstate=s3; #20
else nxtstate=s0; x=3'b001;
endcase #20
always @ (perstate or x) //output block x=3'b010;
case (perstate) #20
s0: if(x==3'b000) y=3'b111; x=3'b100;
else y=3'b000; #20
s1: if(x==3'b001) y=3'b001; x=3'b000;
else y=3'b000; end
s2: if(x==3'b010) y=3'b010; endmodule
else y=3'b000;
s3: if(x==3'b100) y=3'b100;
else y=3'b000;
endcase
endmodule

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