VLSI-LAB MANUAL:DIGITAL

SOFTWARE: CADENCE NCLAUNCH

YASHWANTH SINGH .M

1PE16EC178

PESIT-BSC

7C
EXPERIMENTS:
VERILOG:
1. ALL GATES
2. SYNCHRONOUS COUNTER
3. ASYNCHRONOUS COUNTER
4. FLIP-FLOPS
a)SR FLIPFLOP

b)D FLIPFLOP

c) JK FLIPFLOP

d)T FLIPFLOP

5. PARALLEL ADDER

6. SERIAL ADDER

SWITCH LEVEL:
7. INVERTER

8. BUFFER

9. TRANSMISSION GATE

10. NAND GATE

EXPERIMENT NO :1

ALL GATES

CODE:

module all_gates(input a,b,output [6:0]y);

not x1(y[0],a);
and x2(y[1],a,b);
or x3 (y[2],a,b);
nand x4 (y[3],a,b);
nor x5 (y[4],a,b);
xor x6 (y[5],a,b);
xnor x7 (y[6],a,b);
endmodule

TEST BENCH:

module gates1_tb();
reg a,b;
wire [6:0]y;
all_gates a1(a,b,y);
initial begin
#0 a=1'b1;b=1'b0;
#10 a=1'b0;b=1'b0;
#10 a=1'b1;b=1'b0;
#10 a=1'b1;b=1'b1;
#10 $finish;
end
endmodule

OUTPUTS: 1
2.

EXPERIMENT NO .2

SYNCHRONOUS COUNTER

CODE:

module syn_ctr(input up,clk,clr,output [3:0]count);

reg [3:0]count;
always@(negedge clk,posedge clr)
begin
if(clr)
count=4'b0000;
else
begin
if(up)
count=count+1;
else
count=count-1;
end
end
endmodule

TEST BENCH:

module syn_tb();
reg up,clk,clr;
wire [3:0]count;
syn_ctr n1(up,clk,clr,count);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
#0 clr=1'b1;up=1'b1;
#10 clr=1'b0;up=1'b1;
#50 clr=1'b0;up=1'b0;
#30 $finish;
end
endmodule

OUTPUT:
EXPERIMENT NO 3

ASYNCHRONOUS COUNTER

CODE:

module asyn_ctr(input clk,clear,output [3:0]count);

reg [3:0]count;
always@(negedge clk)
begin
if(clear)
count=4'b0000;
else
count[0]=~count[0];
end
always@(negedge count[0])
begin
count[1]=~count[1];
end
always@(negedge count[1])
begin
count[2]=~count[2];
end
always@(negedge count[2])
begin
count[3]=~count[3];
end
endmodule

TEST BENCH:

module asyn_tb();
reg clk,clear;
wire [3:0]count;
asyn_ctr n1(clk,clear,count);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
#0 clear=1'b1;
#10 clear=1'b0;
#150 $finish;
end
endmodule
OUTPUT:

EXPERIMENT NO.4

FLIPFLOPS:

SR FLIPFLOP:

CODE:

module srff(q,sr,clk,p,r);
input clk,p,r;
input [1:0]sr;
output reg [1:0]q;
initial
begin
q=2'b10;
end
always@(posedge clk,negedge p,negedge r)
begin
if(!r)
q=2'b01;
else if(!p)
q=2'b10;
else
case(sr)
2'b00:q=q;
2'b01:q=2'b01;
2'b10:q=2'b10;
2'b11:q=2'b11;
endcase
end
endmodule
TEST BENCH:

module sr_tb();
reg clk,p,r;
reg [1:0]sr;
wire [1:0]q;
srff s1(q,sr,clk,p,r);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
#0 p=1'b0;r=1'b1;sr[0]=1'bx;sr[1]=1'bx;
#10 p=1'b01;r=1'b0;sr[0]=1'bx;sr[1]=1'bx;
#10 p=1'b1;r=1'b1;sr[0]=1'b0;sr[1]=1'b1;
#10 p=1'b1;r=1'b1;sr[0]=1'b1;sr[1]=1'b0;
#10 p=1'b1;r=1'b1;sr[0]=1'b1;sr[1]=1'b1;
#10 p=1'b1;r=1'b1;sr[0]=1'b0;sr[1]=1'b0;
#10 $finish;
end
endmodule

output:
D FLIPFLOP

CODE:

module d_ff(q,d,clk,p,r);
input clk,p,r;
input d;
output reg [1:0]q;
initial
begin
q=2'b10;
end
always@(posedge clk,negedge p,negedge r)
begin
if(!r)
q=2'b01;
else if(!p)
q=2'b10;
else
case(d)
1'b0:q=2'b01;
1'b1:q=2'b10;
default:q=2'b01;
endcase
end
endmodule

TEST BENCH:

module d_tb();
reg clk,p,r;
reg d;
wire [1:0]q;
d_ff s1(q,d,clk,p,r);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
#0 p=1'b0;r=1'b1;d=1'bx;
#10 p=1'b01;r=1'b0;d=1'bx;
#10 p=1'b1;r=1'b1;d=1'b1;
#10 p=1'b1;r=1'b1;d=1'b0;
#10 p=1'b1;r=1'b1;d=1'b0;
#10 p=1'b1;r=1'b1;d=1'b1;
#10 $finish;
end
endmodule
JK FLIPFLOP

CODE:

module jk_ff(q,j,k,clk,p,r);
input clk,p,r;
input j,k;
output reg [1:0]q;
initial
begin
q=2'b10;
end
always@(posedge clk,negedge p,negedge r)
begin
if(!r)
q=2'b01;
else if(!p)
q=2'b10;
else
case({j,k})
2'b00:begin q[0]=q[0];q[1]=q[1];end
2'b01:begin q[0]=1'b0;q[1]=1'b1;end
2'b10:begin q[0]=1'b1;q[1]=1'b0;end
2'b11:begin q[0]=(~q[0]);q[1]=(~q[1]);end
default:begin q[0]=q[0];q[1]=q[1];end
endcase
end
endmodule
TEST BENCH:

module jk_tb();
reg clk,p,r;
reg j,k;
wire [1:0]q;
jk_ff s1(q,j,k,clk,p,r);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
#0 p=1'b0;r=1'b1;j=1'bx;k=1'bx;
#10 p=1'b01;r=1'b0;j=1'bx;k=1'bx;
#10 p=1'b1;r=1'b1;j=1'b0;k=1'b0;
#10 p=1'b1;r=1'b1;j=1'b0;k=1'b1;
#10 p=1'b1;r=1'b1;j=1'b1;k=1'b0;
#10 p=1'b1;r=1'b1;j=1'b1;k=1'b1;
#10 p=1'b1;r=1'b1;j=1'b0;k=1'b0;
#10 p=1'b1;r=1'b1;j=1'b1;k=1'b1;
#10 p=1'b1;r=1'b1;j=1'b1;k=1'b1;
#10 p=1'b1;r=1'b1;j=1'b0;k=1'b0;
#10 $finish;
end
endmodule

OUTPUT:
T FLIPFLOP

CODE:

module t_ff(q,t,clk,p,r);
input clk,p,r;
input t;
output reg [1:0]q;
initial
begin
q=2'b10;
end
always@(posedge clk,negedge p,negedge r)
begin
if(!r)
q=2'b01;
else if(!p)
q=2'b10;
else
case(t)
1'b0:begin q[0]=q[0];q[1]=q[1];end
1'b1:begin q[0]=(~q[0]);q[1]=(~q[1]);end
default:begin q[0]=q[0];q[1]=q[1];end
endcase
end
endmodule

TEST BENCH:

module t_tb();
reg clk,p,r;
reg t;
wire [1:0]q;
t_ff s1(q,t,clk,p,r);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
#0 p=1'b0;r=1'b1;t=1'bx;
#10 p=1'b01;r=1'b0;t=1'bx;
#10 p=1'b1;r=1'b1;t=1'b1;
#10 p=1'b1;r=1'b1;t=1'b0;
#10 p=1'b1;r=1'b1;t=1'b1;
#10 p=1'b1;r=1'b1;t=1'b0;
#10 $finish;
end
endmodule

OUTPUT:
EXPERIMENT NO.5

4BIT PARALLEL ADDER

CODE:

module bit_4adder(a,b,cin,sum,carry);
input [3:0]a,b;
input cin;
output [3:0]sum;
output carry;
wire c1,c2,c3;
full_adder f1(a[0],b[0],cin,sum[0],c1);
full_adder f2(a[1],b[1],c1,sum[1],c2);
full_adder f3(a[2],b[2],c2,sum[2],c3);
full_adder f4(a[3],b[3],c3,sum[3],carry);
endmodule

FULL ADDER

module full_adder(input a,b,cin,output sum,carry);

wire w1,w2,w3;
xor x1(w1,a,b);
and x3(w2,a,b);
and x4(w3,w1,cin);
xor x2(sum,w1,cin);
or x5(carry,w3,w2);
endmodule

TEST BENCH :FULL ADDER

module full_tb();
reg a,b,cin;
wire carry,sum;
full_adder f1(a,b,cin,sum,carry);
initial begin
#0 a=1'b0;b=1'b0;cin=1'b0;
#10 a=1'b0;b=1'b0;cin=1'b1;
#10 a=1'b0;b=1'b1;cin=1'b0;
#10 a=1'b0;b=1'b1;cin=1'b1;
#10 $finish;
end
endmodule

TEST BENCH: 4BIT ADDER

module bit_4tb();
reg [3:0]a,b;
reg cin;
wire [3:0]sum;
wire carry;
bit_4adder b1(a,b,cin,sum,carry);
initial begin
#0 a=4'b1010;b=4'b1110;cin=0;
#10 a=4'b1010;b=4'b1101;cin=1;
#10 a=4'b1010;b=4'b1011;cin=0;
#10 a=4'b1010;b=4'b0111;cin=1;
#10 $finish;
end
endmodule
EXPERIMENT NO 6

SERIAL ADDER

CODE:

module
serial_yash(clk,reset,load_en1,load_en2,serial_out,serial_cout,data1,d
ata2,en);
input clk,reset,load_en1,load_en2,en;
input [7:0]data1,data2;
output [7:0]serial_out;
output serial_cout;
wire sum,carry;
reg hcarry;
reg [7:0]shift_1,shift_2,shift_3=8'b0;
reg shift_1_lsb,shift_2_lsb;

always @(posedge clk)

begin

if(load_en1)
shift_1=data1;
else if(en)
begin
shift_1_lsb=shift_1[0];
shift_1=shift_1>>1;
shift_1[7]=shift_1_lsb;
end
 if(load_en2)
shift_2=data2;
else if(en)
begin
shift_2_lsb=shift_2[0];
shift_2=shift_2>>1;
shift_2[7]=shift_2_lsb;
end

if(en)
begin
shift_3=shift_3>>1;
if(sum)
shift_3[7]=sum;
else
shift_3[7]=1'b0;
end

end

assign serial_out=shift_3;
full_adder f1(shift_1[0],shift_2[0],hcarry,sum,cout);
assign serial_cout=hcarry;

always @(posedge clk)

begin
if(reset)
hcarry=1'b0;
else if(en)
hcarry=cout;
else
hcarry=hcarry;
end

endmodule

FULL ADDER:

module full_adder(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
assign s=(a^b)^cin;
assign cout=((a&b)|(cin&a)|(b&cin));
endmodule

TEST BENCH:

module serial_yash_tb();
reg clk,reset,load_en1,load_en2,en;
reg [7:0]data1,data2;
wire [7:0]serial_out;
 wire serial_cout;
serial_yash
ad1(clk,reset,load_en1,load_en2,serial_out,serial_cout,data1,data2,en)
;
initial begin
clk=1'b0;
end
always #5 clk=~clk;
initial begin
reset=1'b1;
#5 reset=1'b0;load_en1=1'b1;load_en2=1'b1;
#5 data1=8'b10001001;data2=8'b11111001;
#10 load_en1=1'b0;load_en2=1'b0;en=1'b1;
#80 en=1'b0;
#10 reset=1'b1;
#10 reset=1'b0;load_en1=1'b1;load_en2=1'b1;
#10 data1=8'b00011001;data2=8'b10001001;
#10 load_en1=1'b0;load_en2=1'b0;en=1'b1;
#80 en=1'b0;
#20 $finish;
end
endmodule

OUTPUT:

1.
2.

3.
 SWITCH LEVEL :

EXPERIMENT NO.7

INVERTER

module inverter(in,out);
input in;
output out;
supply1 VDD;
supply0 GND;
nmos(out,GND,in);
pmos(out,VDD,in);
endmodule

TEST BENCH:

module inv_tb();
reg in;
wire out;
inverter n1(in,out);
initial begin
#0 in=1'b0;
#10 in=1'b1;
#10 in=1'b0;
#10 in=1'b1;
#10 $finish;
end
endmodule

OUTPUT:
EXPERIMENT NO. 8

BUFFER

CODE:

module buffer(in,out);
input in;
output out;
wire in1;
inverter i1(in,in1);
inverter i2(in1,out);
endmodule

TEST BENCH:

module buff_tb();
reg in;
wire out;
buffer n1(in,out);
initial begin
#0 in=1'b0;
#10 in=1'b1;
#10 $finish;
end
endmodule

OUTPUT:
EXPERIMENT NO.9

TRANSMISSION GATE

CODE:

module trans(in,out,en);
input in,en;
output out;
wire en1;
inverter i1(en,en1);
nmos(out,in,en);
pmos(out,in,en1);
endmodule

TEST BENCH:

module inv_tb();
reg in,en;
wire out;
trans n1(in,out,en);
initial begin
#0 in=1'b0;en=1'b0;
#10 in=1'b1;en=1'b0;
#10 in=1'b0;en=1'b1;
#10 in=1'b1;en=1'b1;
#10 $finish;
end
endmodule
EXPERIMENT NO. 10

NAND GATE

CODE:

module nand1(a,b,out);
input a,b;
output out;
wire c;
supply1 VDD;
supply0 GND;
pmos(out,VDD,a);
pmos(out,VDD,b);
nmos(out,c,a);
nmos(c,GND,b);
endmodule

TEST BENCH:

module nand1_tb();
reg a,b;
wire out;
nand1 n1(a,b,out);
initial begin
#0 a=1'b0;b=1'b0;
#10 a=1'b1;b=1'b0;
#10 a=1'b0;b=1'b1;
#10 a=1'b1;b=1'b1;
#10 $finish;
end
endmodule