MSP430G2553 Uart Header
MSP430G2553 Uart Header
// MSP430G2xx2 Demo - Timer_A, Ultra-Low Pwr UART 9600 Echo, 32kHz ACLK
//
//
lpsei:
//
__enable_interrupt();
//UART-hoz megszakits bekapcsolsa
//
UART_init();
//
//
Adat fogadsa:
//
__bis_SR_register(LPM0_bits); //itt addig vr amig nem jn karakter
//
//
adat=rxBuffer; //adat unsigned char tipus vltozba lementjk a karak
tert
//
//
UART_tx(rxBuffer); // ez az echo
//
//
Szveg kiiratsa:
//
UART_print("\r\nUzenetet megkaptam!\r\n");
//
//
Adat kiiratsa:
//
UART_print2(adat); +-9999 max rtkkel
//
UART_print_float(adat); +-999 max rtkkel, 2 tizedes jegyig kiirja
//
// Description: Use Timer_A CCR0 hardware output modes and SCCI data latch
// to implement UART function @ 9600 baud. Software does not directly read and
// write to RX and TX pins, instead proper use of output modes and SCCI data
// latch are demonstrated. Use of these hardware features eliminates ISR
// latency effects as hardware insures that output and input bit latching and
// timing are perfectly synchronised with Timer_A regardless of other
// software activity. In the Mainloop the UART function readies the UART to
// receive one character and waits in LPM3 with all activity interrupt driven.
// After a character has been received, the UART receive function forces exit
// from LPM3 in the Mainloop which configures the port pins (P1 & P2) based
// on the value of the received byte (i.e., if BIT0 is set, turn on P1.0).
// ACLK = TACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO
// //* An external watch crystal is required on XIN XOUT for ACLK *//
//
//
MSP430G2xx2
//
----------------//
/|\|
XIN|//
| |
| 32kHz
//
--|RST
XOUT|//
|
|
//
| CCI0B/TXD/P1.1|-------->
//
|
| 9600 8N1
//
| CCI0A/RXD/P1.2|<-------//
// D. Dang
// Texas Instruments Inc.
// December 2010
// Built with CCS Version 4.2.0 and IAR Embedded Workbench Version: 5.10
//******************************************************************************
void UART_init(void)
{
DCOCTL = 0x00;
BCSCTL1 = CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ;
P1OUT
P1SEL
P1DIR
P1DIR
|=
|=
|=
&=
BIT1 |BIT2;
UART_TXD |UART_RXD;
UART_TXD;
~UART_RXD;
TACCTL0 = OUT;
TACCTL1 = SCS + CM1 + CAP + CCIE;
TACTL = TASSEL_2 + MC_2;
}
//-----------------------------------------------------------------------------// Outputs one byte using the Timer_A UART
//-----------------------------------------------------------------------------void UART_tx(int byte)
{
while (TACCTL0 & CCIE);
TACCR0 = TAR;
TACCR0 += UART_TBIT;
TACCTL0 = OUTMOD0 + CCIE;
txData = byte;
txData |= 0x100;
txData <<= 1;
}
//
//
//
//
//
//
//
}
void UART_print2(int data)
{
int a,b,c,d;
if(data<0.0){
UART_tx(0x2D);
data=-data;
}
a=data/1000;
b=(data-a*1000)/100;
c=(data-a*1000-b*100)/10;
d=data-a*1000-b*100-c*10;
a+=48;
b+=48;
c+=48;
d+=48;
UART_tx(a);
UART_tx(b);
UART_tx(c);
UART_tx(d);
}
void UART_print_float(float data) //vals szm kiiratsa kt tizedes jegyel
{
int a,b,c,d,e;
int data_i;
//egsz rsznek a trolsra
float remain;
//tizedes pont utnni rsz trolsra
if(data<0.0){
UART_tx(0x2D);
data=-data;
}
data_i=(unsigned int)data;
remain=(data-(double)data_i)*100;
a=(unsigned int)data/100;
b=((unsigned int)data-a*100)/10;
c=(unsigned int)data-a*100-b*10;
d=(unsigned int)remain/10;
e=(unsigned int)remain-d*10;
//szzasok szma
//tizesek szma
//egyesek szma
//tizedesek szma
//szzadosok szma
a+=48;
b+=48;
c+=48;
d+=48;
e+=48;
UART_tx(a);
UART_tx(b);
UART_tx(c);
UART_tx(0x2E);
UART_tx(d);
UART_tx(e);
}
//pont kdja
//
//
//
//
// TX Mark '1'
// TX Space '0'
}
//-----------------------------------------------------------------------------// Timer_A UART - Receive Interrupt Handler
//-----------------------------------------------------------------------------#pragma vector = TIMER0_A1_VECTOR
__interrupt void Timer_A1_ISR(void)
{
static unsigned char rxBitCnt = 8;
static unsigned char rxData = 0;
switch (__even_in_range(TA0IV, TA0IV_TAIFG)) { // Use calculated branching
case TA0IV_TACCR1:
// TACCR1 CCIFG - UART RX
TACCR1 += UART_TBIT;
// Add Offset to CCRx
if (TACCTL1 & CAP) {
// Capture mode = start bit edg
e
TACCTL1 &= ~CAP;
de
TACCR1 += UART_TBIT_DIV_2;
}
else {
rxData >>= 1;
if (TACCTL1 & SCCI) {
atch
rxData |= 0x80;
}
rxBitCnt--;
if (rxBitCnt == 0) {
rxBuffer = rxData;
rxBitCnt = 8;
TACCTL1 |= CAP;
//
//
//
//
de
__bic_SR_register_on_exit(LPM0_bits); // Clear LPM0 bits fr
om 0(SR)
}
}
break;
}
}
//------------------------------------------------------------------------------