Chapitre Franais

Section France

3D-IC Integration

Developments Cooperation for servicing and MPW runs offering

CMP annual users meeting, 25 January 2012, PARIS

Agenda
Chapitre Franais Section France

Introduction

Process overview

Partnership for MPW runs service

3D-IC Design Platform

First MPW run Conclusion

CMP annual users meeting, 25 January 2012, PARIS

3D-IC Integration : Not a New Story

Chapitre Franais Section France

Akasaka, Y., and Nishimura, T., "Concept and Basic Technologies for 3-D IC Structure IEEE Proceedings of International Electron Devices Meetings, Vo. 32, 1986, pp. 488-491.

CMP annual users meeting, 25 January 2012, PARIS

3D-IC Integration : The Other Path for Scaling

Chapitre Franais Section France

Source IBM

http://www.research.ibm.com/journal/rd/526/knickerbocker.html

Moores law by scaling conventional CMOS involves huge investments. 3D IC processes : An opportunity for another path towards continuing the scaling, involving less investments. Like for conventional CMOS, infrastructures are needed to promote 3D-IC integration, making it available for prototyping at reasonable costs.
CMP annual users meeting, 25 January 2012, PARIS

Two Worlds with Different Integration Approaches

Chapitre Franais Section France

Monolithic
Distributing a whole system across several tiers
Heterogeneous Multi layer 3D-IC TSV integrated 3D-IC TSV integrated 3D-IC face to face

3D-IC TSV Stacked Memory

n o i t a r g e Int
Die to Die Integrated package Multi-Chip Module

Silicon Interposer to high Integrated MCM

Discrete
Assembly of Known Good Dies
CMP annual users meeting, 25 January 2012, PARIS

Substrate based Module (PCB)

Which Design Methodology ?

Chapitre Franais Section France

Discrete : 3D packaging, stacked dies, 1- Design a whole system. 2- Split it in subsystems. 3- Place the subsystems as predefined Known Good Dies (IPs). 4- Determine and place the interfaces in between. 5- The system is done Monolithic : 3D-IC Integration 1- Design a whole system. 2- Split it in subsystems. 3- Determine and place the interfaces in between. 4- Generate and Place the subsystems in between the interfaces. 5- The system is done
Here comes the difference : The key for a true 3D-IC Integration
CMP annual users meeting, 25 January 2012, PARIS

SiP versus 3D-IC

Chapitre Franais Section France

CMP annual users meeting, 25 January 2012, PARIS

Chapitre Franais

Section France

3D-IC Applications

CMP annual users meeting, 25 January 2012, PARIS

Chapitre Franais

Section France

CMP annual users meeting, 25 January 2012, PARIS

3D Microelectronics for Physics (FermiLab, IN2P3, INFN, CERN)

Chapitre Franais Section France

CMP annual users meeting, 25 January 2012, PARIS

Large Systems Benefits from 3D-IC Integration

Chapitre Franais Section France

"Implementing a 2-Gbs 1024-bit -rate Low-Density Parity-Check Code Decoder in ThreeDimensional Integrated Circuits" Lili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, and C.-J. Richard Shi University of Washington International Conference on Computer Design, ICCD, Oct. 2007

Comparison between 3D and 2D designs

Performance Factor (Area * Timing * Power) = 14

CMP annual users meeting, 25 January 2012, PARIS

An Illustration: CPU/Memory Stack

Chapitre Franais Section France

R8051 CPU
80MHz operation; 140MHz Lab test (VDD High) 220MHz Memory interface

IEEE 754 Floating point coprocessor 32 bit Integer coprocessor 2 UARTs, Int. Cont., 3 Timers, Crypto functions 128KBytes/layer main memory

5X performance 1/10th Power

Source Tezzaron (2004)
CMP annual users meeting, 25 January 2012, PARIS

Some 3D-IC Applications

Chapitre Franais Section France

Pixel array for Particle detection (HEP community)

(Pixel sensor + Analog + Digital + Memory + high speed I/Os)

CMOS Image Sensor (Sensor + Processor + Memory) 3D stacked Memories (Flash, DRAM, etc) Multi-cores Processor + Cache Memory NoC (Network on Chip) Processor + DRAM + RF + MEMS + Optical communication +
CMP annual users meeting, 25 January 2012, PARIS

Design Methodology
Chapitre Franais Section France

3D 2.9 D 2.8 D 2.7 D 2.6 D 2.5 D 2.4 D 2.3 D 2.2 D 2.1 D 2D

The more Design Automation is performed on the 3rd dimension, the more is the 3D-IC Integration.
Processor + DRAM + RF + MEMS + Optical communication

NoC Multi-Processors + Memory Pixel Sensor (HEP) Simple Imaging Sensor Memory Stack

System Complexity
CMP annual users meeting, 25 January 2012, PARIS

Chapitre Franais

Section France

CMC-CMP-MOSIS Collaboration

CMP annual users meeting, 25 January 2012, PARIS

Benefits for a global Infrastructure

Chapitre Franais Section France

CMC / CMP / MOSIS partnering for 3D-IC process access

Stimulate the activity by sharing the expenses for manufacturing.

Join forces for the technical support, and dedicate the roles for each partner.

Make easier the tech support for local users respectively by each local center.

Because there is no standard for the 3D-IC integration, it is urgent to setup an infrastructure making possible a broad adoption of 3D-ICs. That will have a beneficial effect on prices, more frequent MPW runs, and more skilled engineers.
CMP annual users meeting, 25 January 2012, PARIS

CMC - CMP - MOSIS Cooperation

Chapitre Franais Section France

CMC supporting Canadian Customers CMP supporting European Customers MOSIS supporting US Customers Each may support other locations

CMP annual users meeting, 25 January 2012, PARIS

Chapitre Franais

Section France

Tezzaron 2-Tier Process (130nm CMOS) Process Overview

CMP annual users meeting, 25 January 2012, PARIS

Tezzaron Process Flow for TSV and DBI (using Via Middle process)
Chapitre Franais Section France

Starting wafer in 130nm (5 Cu metal layers + 6th Cu metal as DBI)

Source Tezzaron
CMP annual users meeting, 25 January 2012, PARIS

Tezzaron Process Flow for TSV and DBI (using Via Middle process)
Chapitre Franais Section France

Cu

Cu

Cu

Cu

Cu

Cu

Cu Cu

Cu

Cu

Cu

CMP annual users meeting, 25 January 2012, PARIS

Resulting 2-tier 3D-IC integration TSV and DBI (Via Middle Process)
DBIs continuing the stacking
Chapitre Franais Section France

Top Tier (10um thickness)

Bottom Tier (Handle wafer)

Source Tezzaron

CMP annual users meeting, 25 January 2012, PARIS

Resulting 2-tier 3D-IC integration TSV and DBI (Via Middle Process)
Chapitre Franais Section France

Bond pad for wire bonding or bump, flip-chip

Top Tier (10um thickness)

Bottom Tier (Handle wafer)

Source Tezzaron
CMP annual users meeting, 25 January 2012, PARIS

3D-IC MPW Infrastructure

Chapitre Franais Section France

CMC-CMP-MOSIS partnering to offer 3D-IC MPW runs Clustering Manufacturing

ce a l np

3D-IC Users

In discussion
In p rep ara tio n

Critical mass will allow frequent MPW runs and low pricing
CMP annual users meeting, 25 January 2012, PARIS

Chapitre Franais

Section France

3D-IC Design Platform

CMP annual users meeting, 25 January 2012, PARIS

Tezzaron / GlobalFoundries Design Platform

Chapitre Franais Section France

The Design Platform is modular. It has all features for full-custom design or semi-custom automatic generation design. PDK : Original PDK from GF + (TSV / DBI) definition from Tezzaron Libraries : CORE and IO standard libraries from ARM Memory compilers : SPRAM, DPRAM and ROM from ARM 3D-IC Utilities : Contributions developments embedded in the platform Tutorials, Users setup.

All modules inside the platform refer to a unique variable, making it portable to any site. The installation procedure is straightforward. Support of CDBA and OpenAccess databases.
CMP annual users meeting, 25 January 2012, PARIS

PDK Tezzaron / GlobalFoundries

Chapitre Franais Section France

chrt13lprf_DK009_Rev_1D (Version issued in Q2 2011) assura calibre cds_cdb cds_oa doc eldo hercules hspice prep3DLVS skill spectre strmMaptables_ARM strmMaptables_Encounter
assura: FILLDRC LVS QRC calibre: 3DDRC 3DLVS DRC FILLDRC calibreSwitchDef

Cadence CDBA 5.1.41 Cadence OA 6.1.4 Design-rules manuals Simulation Models 3D-LVS Preprocessor Design-kit Customization

hercules: DRC LVS STAR_RCXT

CMP annual users meeting, 25 January 2012, PARIS

Collaborative Work to the Design Platform

Chapitre Franais Section France

HEP labs contributing with Programs, Libraries, and Utilities. All included in the Design Platform

DBI (direct bonding interface) cells library. (FermiLab) 3D Pad template compatible with the ARM IO lib. (IPHC) Preprocessor for 3D LVS / Calibre (NCSU) Skill program to generate an array of labels (IPHC) Calibre 3D DRC (Univ. of Bonn) Dummies filling generator under Assura (CMP) Basic logic cells and IO pads (FermiLab) Floor-planning / automatic Place & Route using DBIs, and TSVs (CMP) Skill program generating automatically sealrings and scribes (FermiLab) MicroMagic PDK (Tezzaron/NCSU)
CMP annual users meeting, 25 January 2012, PARIS

Virtuoso Layout Editor with 3D layers and verification

Chapitre Franais Section France

Virtuoso / Cadence IC 5.1.41

TSV Back Metal Calibre Back Pad Assura

DBI
CMP annual users meeting, 25 January 2012, PARIS

Customized Menu with some utilities

Chapitre Franais Section France

Virtuoso / Cadence IC 6.1.4

CMP annual users meeting, 25 January 2012, PARIS

Libraries from Providers and Users

Chapitre Franais Section France

Univ. Bonn NCSU ARM IPHC FermiLab GF/TSC

CMP annual users meeting, 25 January 2012, PARIS

Virtuoso / Calibre DRC Interactive Menu

Chapitre Franais Section France

Setting switches graphically

CMP annual users meeting, 25 January 2012, PARIS

Virtuoso / Calibre LVS Interactive Menu

Chapitre Franais Section France

Choosing 2D or 3D LVS

CMP annual users meeting, 25 January 2012, PARIS

New features in release 2011q2v3

Chapitre Franais Section France

3D-LVS fully functional both for the CDB and OA. Graphical interface for the NCSUs preprocessor utility for merging 2 tiers GDSII. Corrected LEF file for the M6 / two thick metal option. Assura 2D LVS is functional. Walk-Through Encounter tutorial with both DBI and TSV scripting for automatic P&R. Master file browsing the documentation.

3 package options : Complete design-platform TDP = (TDK + libraries + compilers) TDK only TDK + libraries with reduced layout views (memory blocks generated on request with reduced layout views)
CMP annual users meeting, 25 January 2012, PARIS

True 3D Mask Layout Editor

Chapitre Franais Section France

Technology Files fully supported by Tezzaron MicroMagic MAX-3D

CMP annual users meeting, 25 January 2012, PARIS

MicroMagic 3D viewer
Chapitre Franais Section France

CMP annual users meeting, 25 January 2012, PARIS

MicroMagic 3D crossection
Chapitre Franais Section France

CMP annual users meeting, 25 January 2012, PARIS

3D-IC Automatic P&R using DBI and TSV

Chapitre Franais Section France

System Level Partitioning 3D Floor-Planning DBI, TSV, IO placement Automatic Place & Route

Design exploration at system level Design exploration at the physical level DBI, TSV, and IO placement & optimization Cells and blocks place & route can be done tier by tier To be done for each tier, then combined for back-annotation to the 3D top level system

Extraction, Timing Analysis Physical verification 3D DRC, 3D LVS Dummies Filling Final 3D DRC

Similar to the full-custom design flow

CMP annual users meeting, 25 January 2012, PARIS

Automatic P & R Design Flow (From Floor-Plan to Routed Design)

Chapitre Franais Section France

- Std cells Placement - Clock Tree Synthesis

Filler Cells Placement

- DBIs Placement - TSVs Placement - Obstructions on TSVs - Clock routing - Final routing

CMP annual users meeting, 25 January 2012, PARIS

Automatic P&R with Direct Bond Interface

Chapitre Franais Section France

- Encounter natively refuses to make the routing for pins on DBIs. - Custom scripts solved the problem. Its a workaround. - The resulting layout is compliant to the Tezzaron DRC, LVS etc

DBI array generation + P&R

DBI completely routed down to the lower metal layers

CMP annual users meeting, 25 January 2012, PARIS

Automatic P&R with Direct Bond Interface

Chapitre Franais Section France

Saving the floor plan for the bottom tier, and apply it for top tier so the automatic Place & Route run the placement and routing taking into account the DBI locations. The place & route for both tiers is optimal for timing, buffer sizing and power performance.

Resulting in a correct by construction design.

CMP annual users meeting, 25 January 2012, PARIS

3D viewer for 3D-IC design

- Graphically Interfaced into Virtuoso. - Works for both CDB and OA. - Use a free and open-source VRML viewer.

Chapitre Franais

Section France

CMP annual users meeting, 25 January 2012, PARIS

MPW run in 2011

Chapitre Franais Section France

First MPW run Tezzaron 3D-IC 130nm. October 2011.

Institution DEUTSCHES ELEKTRONENSYNCHROTRON (DESY) Town Country Area

HAMBURG

GERMANY

19.7 mm2

LAL / IN2P3 / CNRS

ORSAY

FRANCE

25 mm2

ISEA

Toulouse

FRANCE

6.25 mm2

CMP annual users meeting, 25 January 2012, PARIS

Conclusion
A very collaborative work has been achieved and still ongoing between the parties CMC, CMP, MOSIS, FermiLab, Tezzaron, HEP Labs, NCSU.

Chapitre Franais

Section France

Design Platform 2011q2v3 in use since June 2011. (Release 2012q1v1 will be available in February, 2012)

First MPW run launched in October 2011.

Second MPW run scheduled for March 26th, 2012.

CMP annual users meeting, 25 January 2012, PARIS