EE-4440

FPGA-BASED SYSTEM DESIGN

PAF-KARACHI INSTITUTE OF ECONOMICS & TECHNOLOGY College of Engineering

Course Information Sheet

Course Title: FPGA-BASED SYSTEMS DESIGN Course Code: EE-4440 Credit Hours: 3+1 Pre-requisite(s): Digital System Design and Applications (EE-1421) Teaching Faculty: Dr. Husain Parvez Email Address: husain.parvez@pafkiet.edu.pk Faculty Contact: Advanced Engineering Lab College of Engineering Main Campus Class lectures & http://groups.yahoo.com/group/fpga_kiet_fall_2013 Announcements: ___________________________________________________________________________________ Course Objectives: The aim of this course is to prepare the students to:
Design HDL-based digital systems Use Finite State Machines for the design of control units of sequential systems Test designs using verification techniques like test benches Implement these designs on an FPGA or CPLD prototyping board Understand and assess timing parameters of finished designs

Learning Outcomes: By the end of this course, students should have attained the knowledge as per the course
contents and be able to: Design and code simple and hierarchical Systems using HDL behavioral and structural constructs. Design FSM from specifications and partition designs into control logic and data path Write test benches for combinational and sequential systems. Compile, simulate, synthesize and implement HDL code Give placement and timing constraints for simulations/synthesis tools and determine basic timing parameters of the simulated/synthesized designs

Text Book: Reference Book:

1. RTL Hardware Design Using VHDL Coding for Efficiency, Portability and Scalability. Pong P Chu, 2006 2. EVITA Enhanced VHDL Tutorial with Applications.

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Course Outline
SNo Contents
Introduction to Digital System Design (chapter-1, Evita Chapter-1) i. Introduction about the course. Marks distribution, grading, text book, and miscellaneous announcements. ii. Why we need VHDL? (Evita Chapter-1) iii. Device technologies for hardware implementation and their comparison w.r.t. area, speed, power, cost. Full-Custom ASIC, Standard-cell ASIC, Gate-array ASIC, CPLD, FPGA. (Text book 1.2) iv. System representation - behavioral, Structural, Physical. Level of abstraction - transistor level, gate level, RT level, process level. (Text book 1.3, 1.4) Quick Revision of Digital Logic Design (Notes) i. Combinational v Sequential Circuits ii. Boolean expressions, truth tables, SOP, POS iii. Example: Half adder, Full adder, 4-bit full adder iv. Subtraction using adder v. K-map optimization vi. Difference between latch and flip-flop vii. Example: 4-bit up counter, serial shifter Overview of Hardware Description Languages (ch-2, Evita Chapter-2) i. Basic VHDL through even-parity example. Entity, Architecture, signals. Three different implementations to be discussed. (Text book 2.2) a. General description through truth-table b. Structural description c. Abstract behavioral description ii. Evita Chapter-2 a. Intro to Entity, Architecture, Package Basic Language constructs of VHDL (ch-3, Evita Chapter-3,4,5) i. Skeleton of basic VHDL program. (Text book 3.2) a. Entity, Architecture body b. In, Out, InOut ports c. Design unit and library ii. Lexical elements and program format. (Text book 3.3) a. Comments, reserved words, Identifiers, Numbers and characters iii. VHDL objects. (Text book 3.4) a. Signals, variables, constants, Alias iv. Data types and operators. (Text book 3.5) a. Std_logic_vector b. Bit_vector c. Integer d. Operators (concatenation, logical, shift, equality, arithmetic, etc) v. Evita Chapter 3, 4, 5 a. Signals, types of signals, Signal declaration b. Entity, port declaration c. Data types, operators, constants. Overview of Hardware Description Languages (ch-2, Evita Chapter-9) i. Test bench for even-parity example (Text book 2.2) ii. File-based test bench for even-parity example. (Notes) iii. Evita Chapter 9 a. Structure of Test bench
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Concurrent Signal Assignment Statements in VHDL (ch-4) i. Simple signal assignment concurrent statements (Text book 4.2) a. Examples (Text book 4.2.1) b. Conceptual diagram (Text book 4.2.2) c. Closed feed-back loop (Text book 4.2.3) ii. Conditional signal assignment statements, (Text book 4.3) a. Examples Multiplexer, Binary decoder, Simple ALU. (Text book 4.3.1) b. Conceptual diagrams (Text book 4.3.2, 4.3.3) Concurrent Signal Assignment Statements in VHDL (ch-4) i. Select signal assignment statements (Text book 4.4) a. Examples b. Conceptual implementation ii. Conditional vs select assignment statements. (Text book 4.5) Sequential Statement of VHDL (ch-5, Evita Chapter-6) i. VHDL Process. 5.1 a. Introduction, sensitivity list, wait ii. Sequential Signal Assignment. (Text book 5.2) iii. Variable assignment statement. (Text book 5.3) iv. IF statement. (Text book 5.4) v. Evita Chapter 6 a. Introduction to Processes b. Wait statements c. Sensitivity list d. Signal vs variables e. Loops Sequential Statement of VHDL (ch-5, Evita Chapter-6,7) i. Conceptual implementation of IF statement. (Text book 5.4) ii. Case statement (Text book 5.5) iii. Conceptual implementation of CASE statement. (Text book 5.5) iv. Simple for loop (Text book 5.6) v. Evita Chapter 6, 7 a. Passing information between processes Combinational circuit design: practice (ch-7) i. Gray code incrementor. (Text book 7.5) ii. Adder-based multiplier. (Text book 7.5) First Hourly Sequential circuit design: Principle (ch-8) i. Basic memory elements. (Text book 8.1) ii. Basic synchronous circuit model. (Text book 8.2) iii. Basic memory elements in VHDL. (Text book 8.4) iv. Simple design examples (Text book 8.5) a. DFF with enable b. TFF (Toggle Flip-Flop) c. Shift register v. RAM/ROM instantiation vi. Arbitrary sequence counter. (Text book 8.5) Sequential circuit design: Principle (ch-8) i. Binary counter. (Text book 8.5) ii. Decade counter. (Text book 8.5) iii. Programmable module-m counter. (Text book 8.5) iv. One segment coding style. (Text book 8.7) v. Use of variables in sequential circuit design. (Text book 8.8)
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Finite State Machine: Principle and Practice (ch-10) i. FSM overview. (Text book 10.1) ii. FSM representation. (Text book 10.2) iii. Moore vs Mealy FSM. (Text book 10.1) iv. Example:- Memory controller example. v. Example:- Bit Sequence detector Finite State Machine: Principle and Practice (ch-10) i. Example: Edged detection circuit. ii. Example:- Bit sequence detector iii. Manual translation of FSM to Boolean equations. Finite State Machine: Principle and Practice (ch-10) i. Example:- Nickel Dime Vending machine example. ii. State minimization. iii. VHDL description of an FSM. (Text book 10.5) iv. State Assignment. (Text book 10.6) FSM-D (Chapter-11) i. Introduction (Text book 11.1) ii. Overview of FSM-D, Basic FSMD block diagram (Text book 11.2) iii. FSMD design of a repetitive-addition multiplier FSM-D (Chapter-11, 12) i. Multi-segment VHDL description of an FSMD ii. Example - FSMD of a GCD Circuit (Text book 12.4) FSM-D (Chapter-12) i. Square-root approximation circuit (Text book 12.6) Second Hourly Synthesis of VHDL Code (ch-6) i. Timing analysis. (Text book 6.5) a. Propagation delay, System delay, false path, delay estimation ii. Timing Hazards. (Text book 6.5) a. Static hazards, Dynamic hazards Sequential circuit design: Principle (ch-8) i. Timing analysis of sequential synchronous circuits. (Text book 8.6) Finite State Machine: Principle and Practice (ch-10) i. Timing and performance of an FSM. (Text book 10.3) ii. Moore Machine vs Mealy Machine. Combinational circuit design: practice (ch-7) i. Operator sharing. Examples. (Text book 7.2) ii. Functionality sharing. Examples. (Text book 7.3) Sequential circuit design: Practice (ch-9) i. Misuse of asynchronous signals. (Text book 9.1) ii. Misuse of gated clock. (Text book 9.1) iii. Misuse of derived clock. (Text book 9.1) iv. Gray counter. (Text book 9.2) v. Ring counter. (Text book 9.2) vi. Register file. (Text book 9.3) Sequential circuit design: Practice (ch-9) i. Register-based synchronous FIFO. (Text book 9.3) ii. Register-based content addressable memory. (Text book 9.3) Sequential circuit design: Practice (ch-9) i. Pipelined Design. (Text book 9.4) a. Delay vs Throughput b. Overview on pipelined design c. Non-pipelined multiplier in cascaded stages
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Sequential circuit design: Practice (ch-9) i. Revision - Non-pipelined multiplier in cascaded stages (Text book 9.4) ii. Four-stage pipelined multiplier. Hierarchical Design in VHDL (ch-13, Evita Chapter-8) i. Introduction. (Text book 13.1) ii. Components. (Text book 13.2) iii. Generics. (Text book 13.3) iv. Configuration. (Text book 13.4) v. Other supporting constructs. (Text book 13.5) vi. Evita Chapter 8 a. Structural description b. Configurations Revision

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Student Assessment Information Sheet

A. Breakdown of Assessment of Theory
No. Description 1. Final Exam 2. Hourly Test (average of all hourly exams) 3. Quiz 4. Assignment 5. GSS TOTAL Mark Distribution (%) 50 25 10 15 00 100%

B. Breakdown of Assessment of Lab

No. Description 1. Final Exam 2. Project 3. Lab reports TOTAL

Mark Distribution (%) 20 50 30 100%

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Attendance and Class Participation: 1. Attendance shall be taken by the teacher within first five minutes of the class start time 2. Students whos absentees from the class exceed six (6) shall be dropped from the course without any warning. [Name of the student shall disappear from the attendance roll.] 3. There shall be no make-up test of any kind for any assessed component of the course. 4. All assessed components shall be returned to the students immediately after checking. 5. No claim for any correction, review or scrutiny shall be entertained one week after the return of answer scripts. 6. Please save all your returned quizzes and assignments for verification of tabulated results towards the end of the semester.

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