ELECTRONICS & COMMUNICATION ENGINEERING

CATEGORY L T P CREDIT
ECT393 FPGA BASED SYSTEM DESIGN VAC 3 1 0 4

Preamble: This course aims to develop the skill of FPGA based system design.

Prerequisite: ECT203 Logic Circuit Design

Course Outcomes: After the completion of the course the student will be able to

CO 1 Design simple digital systems with programmable logic devices

CO 2 Analyze the architecture of FPGA
CO 3 Analyze the design considerations of FPGA

CO4 Design simple combinational and sequential circuits using FPGA

Mapping of course outcomes with program outcomes

PO 1 PO 2 PO 3 PO 4 PO 5 PO 6 PO 7 PO 8 PO 9 PO PO PO
10 11 12
CO 1 3 3 2 2
CO 2 3 3 2 2
CO 3 3 3 2 2
CO 4 3 3 2 2

Assessment Pattern

Bloom’s Category Continuous Assessment End Semester Examination

Tests
1 2
Remember K1 10 10 10
Understand K2 30 30 60
Apply K3 10 10 30
Analyze K4
Evaluate
Create

Mark distribution

Total CIE ESE ESE Duration

Marks
150 50 100 3 hours

Continuous Internal Evaluation Pattern:

Attendance : 10marks
Continuous Assessment Test(2numbers) : 25marks
Assignment/Quiz/Course project : 15marks

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End Semester Examination Pattern: There will be two parts; Part A and Part B. Part A
contain 10 questions with 2 questions from each module, having 3 marks for each question.
Students should answer all questions. Part B contains 2 questions from each module of
which student should answer any one. Each question can have maximum 2 sub-divisions and
carry 14 marks.

Course Level Assessment Questions

Course Outcome 1 (CO1): Design simple digital systems with programmable logic devices.

1. Design a decade counter using Verilog.

2. Implement a full adder using ROM

Course Outcome 2 (CO2): Analyze the architecture of FPGA

1. Compare coarse and fine grained FPGA.

2. Explain the architecture of logic block of FPGA

Course Outcome 3 (CO3): Analyze the design considerations of FPGA

1. What are the vendor specific issues in FPGA design.

2. Analyze Timing and Power dissipation in a typical FPGA.

Course Outcome 4 (CO4): Design simple combinational and sequential circuits using FPGA.

1. Implement a counter in Xilinx Virtex.

2. Explain how sequential circuit can be mapped into Xilinx Virtex LUT.

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SYLLABUS
Module 1:
Introduction: Digital system design options and tradeoffs, Design methodology and technology
overview, High Level System Architecture and Specification: Behavioral modelling and
simulation, Hardware description languages (emphasis on Verilog), combinational and sequential
design, state machine design, synthesis issues, test benches.

Module 2:
Programmable logic Devices: ROM, PLA, PAL, CPLD, FPGA Features, Limitations,
Architectures and Programming. Implementation of MSI circuits using Programmable logic
Devices.

Module 3:
FPGA architecture: FPGA Architectural options, granularity of function and wiring resources,
coarse V/s fine grained, vendor specific issues (emphasis on Xilinx and Altera), Logic block
architecture: FPGA logic cells, timing models, power dissipation I/O block architecture: Input and
Output cell characteristics, clock input, Timing, Power dissipation.

Module 4:
Placement and Routing: Programmable interconnect - Partitioning and Placement, Routing
resources, delays; Applications -Embedded system design using FPGAs, DSP using FPGAs.

Module 5:
Commercial FPGAs: Xilinx, Altera, Actel (Different series description only), Case study Xilinx
Virtex: implementation of simple combinational and sequential circuits.

Text Books
1. FPGA-Based System Design Wayne Wolf, Verlag: Prentice Hall
2. Modern VLSI Design: System-on-Chip Design (3rd Edition) Wayne Wolf, Verlag
Reference Books
1. Field Programmable Gate Array Technology - S. Trimberger, Edr, 1994, Kluwer Academic
2. Digital Design Using Field Programmable Gate Array, P.K. Chan & S. Mourad, 1994,
Prentice Hall
3. Field programmable gate array, S. Brown, R.J. Francis, J. Rose, Z.G. Vranesic, 2007, BS

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Course Contents and Lecture Schedule

No Topic No. of
Lectures
1 Introduction
1.1 Digital system design options and tradeoffs 1
1.2 Design methodology and technology overview 2
1.3 High Level System Architecture and Specification: Behavioral 2
modelling and simulation
1.4 Hardware description languages, combinational and sequential design 2
1.5 State machine design, synthesis issues, test benches. 2

2 Programmable logic Devices

2.1 ROM, PLA, PAL, CPLD 3
2.2 FPGA Features, Limitations, Architectures and Programming. 2
2.3 Implementation of MSI circuits using Programmable logic Devices. 3

3 FPGA architecture
3.1 FPGA Architectural options 1
3.2 Granularity of function and wiring resources, coarse V/s fine grained, 3
vendor specific issues (emphasis on Xilinx and Altera)
3.3 Logic block architecture: FPGA logic cells, timing models, power 3
dissipation
3.4 I/O block architecture: Input and Output cell characteristics, clock 3
input, Timing, Power dissipation.

4 Placement and Routing

4.1 Programmable interconnect - Partitioning and Placement 3
4.2 Routing resources, delays 3
4.3 Applications -Embedded system design using FPGAs, DSP using 3
FPGAs
5 Commercial FPGAs
5.1 Xilinx, Altera, Actel (Different series description only) 2
5.2 Case study Xilinx Virtex 4
5.3 Implementation of simple combinational and sequential circuits 3

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Model Question paper

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY

FIFTH SEMESTER B.TECH DEGREE EXAMINATION, (Model Question Paper)
Course Code: ECT393
Program: Electronics and Communication Engineering
Course Name: FPGA Based System Design
Max.Marks: 100 Duration: 3Hours
PART A

Answer ALL Questions. Each Carries 3 mark.

1. What are the synthesis issues in FPGA design.

K2
2 Describe FPGA design methodology. K2
3 Differentiate PLA with PAL K2
4 What are the limitations of FPGA. K2
5 Compare coarse and fine grained FPGA architecture. K2
6 What are the timing models in logic block architecture. K2
7 List the applications of FPGA. K2
8 Describe routing resources in FPGA routing. K2
9 Describe how a combnational circuit can be mapped into K2
Xilinx Virtex LUT.
10 List different commercially available FPGAs. K2

PART – B
Answer one question from each module; each question carries 14 marks.
Module – I

11. Design a full adder using Verilog. 7 CO1 K3

a)
11. Explain behavioral modeling and simulation with an example. 7 CO1 K2
b)
OR
12.a) What is FSM? How it is used for FPGA. 7 CO1 K2
12.b) Explain the purpose of test bench and how it is written in a HDL. 7 CO1 K2

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Module – II

13 a) Design the function F=XYZ’+Y’ Z+X Y’ using PLA 8 CO2 K3

13 b) Compare CPLD with FPGA 6 CO2 K2
OR
14 a) Implement the following Boolean function using PAL: 8 CO2 K3
F(w, x, y, z) = Σm (0, 2, 4, 10, 11, 12, 14, 15)m (0, 2,
4, 10, 11, 12, 14, 15)
14 b) Draw the structure of PAL and explain it. 6 CO2 K2

Module – III

15 a) Draw and explain I/O block architecture of FPGA. 7 CO2 K2

15 b) Draw and explain coarse grained FPGA architecture. 7 CO2 K2
OR
16 a) Explain timing and power dissipation in Logic block and I/O block. 7 CO2 K2
16 b) Draw and explain fine grained FPGA architecture. 7 CO2 K2

Module – IV

17 a) Explain partitioning and placement processes in FPGA 8 CO4 K2

17 b) Explain embedded system design using FPGAs 6 CO4 K2
OR
18 a) Explain the delays associated with placement and routing 7 CO4 K2
18 b) Explain DSP design using FPGAs 7 CO4 K2

Module – V

19 a) With neat diagram explain the architecture of Xilinx Virtex IOB. 7 CO3 K2

19 b) Design a four bit up counter with parallel load feature using Xilinx 7 CO3 K3
Virtex.
OR
20 a) Explain the mapping of combinational and sequential circuits using 5 CO3 K3
LUTs.
20 b) Explain the architecture of Xilinx Virtex CLB 9 CO3 K2

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