Chapter 3

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ARM MPU Subsystem

This chapter describes the MPU Subsystem for the device.
Topic

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3.1

ARM Cortex-A8 MPU Subsystem

The Microprocessor Unit (MPU) subsystem of the device handles transactions between the ARM core (ARM Cortex-A8 Processor), the L3 interconnect, and the interrupt controller (INTC). The MPU subsystem is a hard macro that integrates the ARM Cortex-A8 Processor with additional logic for protocol conversion, emulation, interrupt handling, and debug enhancements. Cortex-A8 is an ARMv7 compatible, dual-issue, in-order execution engine with integrated L1 and L2 caches with NEON SIMD Media Processing Unit. An Interrupt Controller is included in the MPU subsystem to handle host interrupt requests in the system. The MPU subsystem includes CoreSight compliant logic to allow the Debug Sub-system access to the CortexA8 debug and emulation resources, including the Embedded Trace Macrocell. The MPU subsystem has three functional clock domains, including a high-frequency clock domain used by the Cortex-A8. The high-frequency domain is isolated from the rest of the system by asynchronous bridges. Figure 3-1 shows the high-level block diagram of the MPU subsystem. Figure 3-1. Microprocessor Unit (MPU) Subsystem
MPU Subsystem ETMSOC

Integer Core L1 I
32KB w/SED

Neon Core L1 D
32KB w/SED

Cortex A8 L2
256KB w/ECC

OCP2 ATB Internal SRAM

64K ICE Crusher 128

32

Debug Bus (OCP)

ROM 176 KB OCM RAM

64 KB

AXI2OCP
275 MHz 64 128 64 32

AINTC
275 MHz

System Interrupts

I2ASYNC
550 MHz 128

I2ASYNC
550 MHz 64

MPU PLL

OCP Master 0

OCP Master 1

T2ASYNC
200 MHz

T2ASYNC
200 MHz

CLK_M_OSC Frm Master OSC

To L3

To L3

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3.1.1 Features
This section outlines the key features of the MPU subsystem: ARM Microprocessor CortexA8 ARM Architecture version 7 ISA. 2-issue, in-order execution pipeline. L1 and L2 Instruction and Data Cache of 32 KB , 4-way, 16 word line with 128 bit interface. Integrated L2 cache of 256 KB, 8-way, 16 word line, 128 bit interface to L1 along with ECC/Parity supported. Includes the Neon Media coprocessor (NEON) which implements the Advanced SIMD media processing architecture. Includes the VFP coprocessor which implements the VFPv3 architecture and is fully compliant with IEEE 754 standard. The external interface uses the AXI protocol configured to 128-bit data width. Includes the Embedded Trace Macrocell (ETM) support for non-invasive debugging. Implements the ARMv7 debug with watch-point and breakpoint registers and 32-bit Advanced Peripheral Bus (APB) slave interface to CoreSight debug systems. AXI2OCP Bridge Support OCP 2.2. Single Request Multiple Data Protocol on two ports. Multiple targets, including three OCP ports (128-bit, 64-bit and 32-bit). Interrupt Controller Support up to 128 interrupt requests Emulation/Debug Compatible with CoreSight Architecture. Clock Generation Through PRCM DFT Integrated PBIST controller to test L2 tag and data ram, L1I and L1D data ram and OCM RAM.

3.1.2 MPU Subsystem Integration

The MPU subsystem integrates the following group of submodules: ARM Cortex-A8 Processor: Provides a high processing capability, including the NEON technology for mobile multimedia acceleration. The ARM communicates through an AXI bus with the AXI2OCP bridge and receives interrupts from the MPU subsystem interrupt controller (MPU INTC). Interrupt controller: Handles the module interrupts (for details, see the Interrupt Controller chapter). AXI2OCP bridge: Allows communication between the ARM (AXI), the INTC (OCP), and the modules (OCP L3). I2Async bridge: This is an asynchronous bridge interface providing an asynchronous OCP to OCP interface. This interface is between the AXI2OCP bridge within the MPU subsystem and the T2Async bridge external to the MPU subsystem. Clock Divider: Provides the required divided clocks to the internal modules of the MPU subsystem and has a clock input from SYSCLK2 which is fed by the power, reset, and clock management (PRCM) module of the device. In-Circuit Emulator: It is fully Compatible with CoreSight Architecture and enables debugging capabilities.

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Device

MPU subsystem ARM Cortex-A8 NEON NEON_RST

MPU_MSTANDBY

MPU_INTC_IRQ

MPU_INTC_FIQ

Device modules

AXI

sys_nirq

Interrupts

PRCM INTC AXI MOCP (P) AXI2OCP MOCP (P) MPU clock generator MPU_CLK CORE_RST

L3_ICLK MPU_RST

I2Async

Non-OCP

Level T2Async shift

L3

Figure 3-2. Microprocessor Unit (MPU) Subsystem Signal Interface

3.1.3 MPU Subsystem Clock and Reset Distribution

3.1.3.1 Clock Distribution

The MPU subsystem includes an embedded DPLL which sources the clock for the ARM Cortex-A8 processor. A clock divider within the subsystem is used for deriving the clocks for other internal modules.

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All major modules inside the MPU subsystem are clocked at half the frequency of the ARM core. The divider of the output clock can be programmed with the PRCM.CM_CLKSEL2_PLL_MPU[4:0]MPU_DPLL_CLKOUT_DIV register field, the frequency is relative to the ARM core. For details see the Power, Reset, and Clock Management (PRCM) chapter. The clock generator generates the following functional clocks: ARM (ARM_FCLK): This is the core clock. It is the base fast clock that is routed internally to the ARM logic and internal RAMs, including NEON, L2 cache, the ETM core (emulation), and the ARM core. AXI2OCP Clock (AXI_FCLK): This clock is half the frequency of the ARM clock (ARM_FCLK). The OCP interface thus performs at one half the frequency of ARM. Interrupt Controller Functional Clock (MPU_INTC_FCLK): This clock, which is part of the INTC module, is half the frequency of the ARM clock (ARM_FCLK). ICE-Crusher Functional Clock (ICECRUSHER_FCLK): ICE-Crusher clocking operates on the APB interface, using the ARM core clocking. This clock is half the frequency of the ARM clock (ARM_FCLK). I2Async Clock (I2ASYNC_FCLK): This clock is half the frequency of the ARM clock (ARM_FCLK). It matches the OCP interface of the AXI2OCP bridge.
NOTE: The second half of the asynchronous bridge (T2ASYNC) is clocked directly by the PRCM with the core clock. T2ASYNC is not part of the MPU subsystem.

Emulation Clocking: Emulation clocks are distributed by the PRCM module and are asynchronous to the ARM core clock (ARM_FCLK) and can run at a maximum of 1/3 the ARM core clock. Table Table 3-1 and summarizes the clocks generated in the MPU subsystem by the MPU clock generator.
MPU subsystem INTC_FCLK (ARM_FCLK/2) AXI2OP_FCLK (ARM_FCLK/2) AXI2OCP MPU_CLK PRCM MPU I2ASYNC_FCLK (ARM_FCLK/2) clock generator ICECRUSHER_FCLK (ARM_FCLK/2) ARM_FCLK ARM Cortex-A8 EMU DPLL EMU_CLOCKS Emulation/ trace/debug I2Async ICECrusher

INTC

Figure 3-3. MPU Subsystem Clocking Scheme Table 3-1. MPU Subsystem Clock Frequencies
Clock signal Cortex A8 Core Functional Clock AXI2OCP Bridge Functional Clock Device Clock I2Async Bridge Functional Clock Frequency MPU_CLK MPU_CLK / 2 MPU_CLK / 2 MPU_CLK / 2

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3.1.3.2

Reset Distribution

Resets to the MPU subsystem are provided by the PRCM and controlled by the clock generator module.
MPU subsystem

CORE_RST INTC

MPU_RST AXI2OCP

I2Async PRCM

ARM Cortex-A8 NEON_RST

NEON

EMU_RST EMU_RSTPWRON EMU

MPU_RSTPWRON ICECrusher

Figure 3-4. Reset Scheme of the MPU Subsystem Table 3-2. Reset Scheme of the MPU Subsystem
Signal Name MPU_RST NEON_RST CORE_RST MPU_RSTPWRON EMU_RST EMU_RSTPWRON I/O I I I I I I Interface PRCM PRCM PRCM PRCM PRCM PRCM

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For details about clocks, resets, and power domains, see Chapter 8, Power, Reset, and Clock Management (PRCM).

3.1.4 ARM Subchip

3.1.4.1 ARM Overview

The ARM Cortex-A8 processor incorporates the technologies available in the ARM7 architecture. These technologies include NEON for media and signal processing and Jazelle RCT for acceleration of realtime compilers, Thumb-2 technology for code density and the VFPv3 floating point architecture. For details, see the ARM Cortex-A8 Technical Reference Manual. 3.1.4.2 ARM Description

3.1.4.2.1 ARM Cotrex-A8 Instruction, Data, and Private Peripheral Port The AXI bus interface is the main interface to the ARM system bus. It performs L2 cache fills and noncacheable accesses for both instructions and data. The AXI interface supports 128bit and 64-bit wide input and output data buses. It supports multiple outstanding requests on the AXI bus and a wide range of bus clock to core clock ratios. The bus clock is synchronous with the core clock. See the ARM Cortex-A8 Technical Reference Manual for a complete programming model of the transaction rules (ordering, posting, and pipeline synchronization) that are applied depending on the memory region attribute associated with the transaction destination address. 3.1.4.2.2 ARM Core Supported Features Table 3-3 provides a list of main functions of the Cortex-A8 core supported inside the MPU Subsystem. Table 3-3. ARM Core Supported Features
Features ARM version 7 ISA Comments Standard ARM instruction set + Thumb2, JazelleX Java accelerator, and Media extensions. Backward compatible with previous ARM ISA versions. L1 Icache and Dcache L2 Cache 32 KB , 4-way, 16 word line, 128 bit interface. 256 KB, 8-way, 16 word line, 128 bit interface to L1, ECC/Parity is supported. The L2 cache and cache controller are embedded within the ARM core. L2 valid bits cleared by software loop or by hardware. TLB CoreSight ETM Branch Target Address Cache Enhanced Memory Management Unit Neon Flat Memories Buses Fully associative and separate ITLB with 32 entries and DTLB with 32 entries. The CoreSight ETM is embedded with the ARM core. The 32KB buffer (ETB) exists at the Chip Level (DebugSS) 512 entries Mapping sizes are 4KB, 64KB, 1MB, and 16MB. (ARM MMU adds extended physical address ranges) Gives greatly enhanced throughput for media workloads and VFP-Lite support. 176 Kbytes of ROM 64 Kbytes of RAM 128 bit AXI internal bus from CortexA8 routed by an AXI2OCP bridge to the interrupt controller, ROM, RAM, and 3 asynchronous OCP bridges (128 bits, and 64 bits) Closely coupled INTC to the ARM core with 128 interrupt lines Present. Supported via DAP Supported via TPIU

Low interrupt latency Vectored Interrupt Controller Port JTAG based debug Trace support

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Table 3-3. ARM Core Supported Features (continued)

Features External Coprocessor Comments Not supported

For more information, see the ARM Cortex-A8 Technical Reference Manual.

3.1.5 Interrupt Controller

The Host ARM Interrupt Controller (AINTC) is responsible for prioritizing all service requests from the system peripherals and generating either nIRQ or nFIQ to the host. The type of the interrupt (nIRQ or nFIQ) and the priority of the interrupt inputs are programmable. The AINTC interfaces to the ARM processor via the AXI port through an AXI2OCP bridge and runs at half the processor speed. It has the capability to handle up to 128 requests which can be steered/prioritized as A8 nFIQ or nIRQ interrupt requests. The general features of the AINTC are: Up to 128 level sensitive interrupts inputs Individual priority for each interrupt input Each interrupt can be steered to nFIQ or nIRQ Independent priority sorting for nFIQ and nIRQ

3.1.6 Power Management

3.1.6.1 Power Domains

The MPU subsystem is divided into 5 power domains controlled by the PRCM, as shown in Figure Figure 3-5.
NOTE: The emulation domain and the core domain are not fully embedded in MPU subsystem.

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MPU subsystem MPU_RST MPU domain ARM Cortex-A8 I2Async AXI2OCP SRAM L1 SRAM L2 MPU_RSTPWRON IceCrusher EMU_RSTPWRON Emulation domain EMU_RST NEON_RST NEON domain

INTC CORE_RST Core domain

Figure 3-5. MPU Subsystem Power Domain Overview Power management requirements at the device level govern power domains for the MPU subsystem. The device-level power domains are directly aligned with voltage domains and thus can be represented as a cross reference to the different voltage domains. Table 3-4 shows the different power domains of the MPU subsystem and the modules inside. Table 3-4. Overview of the MPU Subsystem Power Domain
Functional Power Domain MPU subsystem domain MPU NEON domain CORE domain EMU domain Physical Power Domain per System/Module ARM, AXI2OCP, I2Asynch Bridge, ARM L1 and L2 periphery logic and array, ICE-Crusher, ETM, APB modules ARM NEON accelerator MPU interrupt controller EMU (ETB,DAP)

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NOTE: L1 and L2 array memories have separate control signals into the in MPU Subsystem, thus directly controlled by PRCM For details on the physical power domains and the voltage domains, see the Power, Reset, and Clock Management (PRCM) chapter.

3.1.6.2

Power States

Each power domain can be driven by the PRCM in 4 different states, depending on the functional mode required by the user. For each power domain the PRCM manages all transitions by controlling domain clocks, domain resets, domain logic power switches and memory power switches. Table 3-5. MPU Power States
Power State Active Inactive Off Logic Power On On Off Memory Power On or Off On or Off Off Clocks On (at least one clock) Off Off (all clocks)

3.1.6.3

Power Modes

The major part of the MPU subsystem belongs to the MPU power domain. The modules inside this power domain can be off at a time when the ARM processor is in an OFF or standby mode. IDLE/WAKEUP control is managed by the clock generator block but initiated by the PRCM module. The MPU Standby status can be checked with PRCM.CM_IDLEST_MPU[0] ST_MPU bit. For the MPU to be on, the core (referred here as the device core) power must be on. Device power management does not allow INTC to go to OFF state when MPU domain is on (active or one of retention modes). The NEON core has independent power off mode when not in use. Enabling and disabling of NEON can be controlled by software. CAUTION The MPU L1 cache memory does not support retention mode, and its array switch is controlled together with the MPU logic. For compliance, the L1 retention control signals exist at the PRCM boundary, but are not used. The ARM L2 can be put into retention independently of the other domains. Table 3-6 outlines the supported operational power modes. All other combinations are illegal. The ARM L2, NEON, and ETM/Debug can be powered up/down independently. The APB/ATB ETM/Debug column refers to all three features: ARM emulation, trace, and debug. The MPU subsystem must be in a power mode where the MPU power domain, NEON power domain, debug power domain, and INTC power domain are in standby, or off state.

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Table 3-6. MPU Subsystem Operation Power Modes

Mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 MPU and ARM Core Logic Active Active Active Active Active Active OFF Standby Standby Standby Standby Standby Standby OFF ARM L2 RAM Active Active RET RET OFF OFF RET Active Active RET RET OFF OFF OFF NEON INTC Active OFF Active OFF Active OFF OFF Standby OFF Standby OFF Standby OFF OFF Device Core and ETM Active Active Active Active Active Active OFF Active Active Active Active Active Active OFF APB/ATB Debug Disabled or enabled Disabled or enabled Disabled or enabled Disabled or enabled Disabled or enabled Disabled or enabled Disabled or enabled Disabled or enabled Disabled or enabled Disabled or enabled Disabled or enabled Disabled or enabled Disabled or enabled Disabled or enabled

3.1.7 ARM Programming Model

For detailed descriptions of registers used for MPU configuration, see Chapter 8, Power, Reset, and Clock Management (PRCM). 3.1.7.1 Clock Control

For clock configuration settings, see Chapter 8, Power, Reset, and Clock Management (PRCM). 3.1.7.2 MPU Power Mode Transitions

The following subsections describe transitions of different power modes for MPU power domain: Basic power on reset MPU into standby mode MPU out of standby mode MPU power on from a powered off state 3.1.7.2.1 Basic Power-On Reset The power-on reset follows the following sequence of operation and is applicable to initial power-up and wakeup from device off mode: Reset the INTC (CORE_RST) and the MPU subsystem modules (MPU_RST). The clocks must be active during the MPU reset and CORE reset. 3.1.7.2.2 MPU Into Standby Mode The MPU into standby mode follows the following sequence of operation and is applicable to initial powerup and wakeup from device Off mode. 1. The ARM core initiates entering into standby via software only (CP15 - WFI). 2. MPU modules requested internally of MPU subsystem to enter idle, after ARM core standby detected. 3. MPU is in standby output asserted for PRCM (all outputs guaranteed to be at reset values). 4. PRCM can now request INTC to enter into idle mode. Acknowledge from INTC goes to PRCM.
NOTE: The INTC SWAKEUP output is a pure hardware signal to PRCM for the status of its IDLE request and IDLE acknowledge handshake.
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NOTE: In debug mode, ICE-Crusher could prevent MPU subsystem from entering into IDLE mode.

3.1.7.2.3 MPU Out Of Standby Mode The MPU out of standby mode follows the following sequence of operation and is applicable to initial power-up and wakeup from device Off mode. 1. PRCM must start clocks through DPLL programming. 2. Detect active clocking via status output of DPLL. 3. Initiate an interrupt through the INTC to wake up the ARM core from STANDBYWFI mode. 3.1.7.2.4 MPU Power On From a Powered-Off State 1. MPU Power On, NEON Power On, Core Power On (INTC) should follow the ordered sequence per power switch daisy chain to minimize the peaking of current during power-up.
NOTE: The core domain must be on, and reset, before the MPU can be reset.

2. Follow the reset sequence as described in the Basic Power-On Reset section. 3.1.7.3 NEON Power Mode Transition

When NEON power domain transition is configured to Automatic Hardware-supervised mode (CM_CLKSTCTRL_NEON[1:0] CLKTRCTRL_NEON bits are set to 0x3), it can not transition into idle unless MPU goes into Standby, because of the Hardware Sleep dependency between NEON and the MPU domain. In that case, the MPU domain must also be configured in Automatic Hardware Supervised mode (CM_CLKSTCTRL_MPU[1:0] CLKTRCTRL_MPU bits must be set to 0x3) for the NEON power domain transition to happen. For the complete programming model, see the ARM Cortex-A8 Technical Reference Manual.

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