KMM366S1723T

Revision History
Revision .1 (July 1998)
- Package Dimensions is revised.

Preliminary PC100 SDRAM MODULE

REV. 1 July 1998

KMM366S1723T
KMM366S1723T SDRAM DIMM

Preliminary PC100 SDRAM MODULE

16Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION
The Samsung KMM366S1723T is a 16M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung KMM366S1723T consists of eight CMOS 16M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The KMM366S1723T is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURE
Performance range Part No. KMM366S1723T-G8 KMM366S1723T-GH KMM366S1723T-GL Max Freq. (Speed) 125MHz (8ns @ CL=3) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3)

Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Serial presence detect with EEPROM PCB : Height (1,375mil), single sided component

PIN CONFIGURATIONS (Front side/back side)

Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 *CB0 *CB1 VSS NC NC VDD WE DQM0 Front Pin Front Pin Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 *CB4 *CB5 VSS NC NC VDD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 *CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD *CLK1 *A12 VSS CKE0 *CS3 DQM6 DQM7 *A13 VDD NC NC *CB6 *CB7 VSS DQ48 DQ49 Pin Back 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ50 DQ51 VDD DQ52 NC *VREF NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS *CLK3 NC **SA0 **SA1 **SA2 VDD 29 DQM1 57 DQ18 85 58 DQ19 86 CS0 30 59 87 VDD 31 DU 60 DQ20 88 32 VSS 61 89 NC 33 A0 62 *VREF 90 34 A2 63 *CKE1 91 35 A4 64 92 VSS 36 A6 65 DQ21 93 37 A8 38 A10/AP 66 DQ22 94 67 DQ23 95 39 BA1 68 96 VSS 40 VDD 69 DQ24 97 41 VDD 42 CLK0 70 DQ25 98 71 DQ26 99 43 VSS 72 DQ27 100 44 DU 73 VDD 101 45 CS2 46 DQM2 74 DQ28 102 47 DQM3 75 DQ29 103 76 DQ30 104 48 DU 77 DQ31 105 49 VDD 78 VSS 106 50 NC 79 CLK2 107 51 NC NC 108 52 *CB2 80 WP 109 53 *CB3 81 82 **SDA 110 54 VSS 55 DQ16 83 **SCL 111 VDD 112 56 DQ17 84

PIN NAMES
Pin Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 CLK0, CLK2 CKE0 CS0, CS2 RAS CAS WE DQM0 ~ 7 VDD VSS *VREF SDA SCL SA0 ~ 2 WP DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Serial data I/O Serial clock Address in EEPROM Write protection Dont use No connection

* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

REV. 1 July 1998

KMM366S1723T
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select

Preliminary PC100 SDRAM MODULE

Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. WP pin is connected to VSS through 47K Resistor. When WP is "high", EEPROM Programming will be inhibited and the entire memory will be write-protected. Power and ground for the input buffers and the core logic.

CKE

Clock enable

A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7 DQ0 ~ 63 WP VDD/VSS

Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Write protection Power supply/ground

REV. 1 July 1998

KMM366S1723T
FUNCTIONAL BLOCK DIAGRAM
CS0 DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS2 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM4 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5

Preliminary PC100 SDRAM MODULE

U0

DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

CS

U4

U1

DQM CS DQ0 DQ1 DQ2 U5 DQ3 DQ4 DQ5 DQ6 DQ7

DQM6 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS

U2

U6

U3

U7

Serial PD A0 ~ An, BA0 & 1 RAS CAS WE CKE0 10 DQn VDD Vss Two 0.1uF Capacitors per each SDRAM To all SDRAMs Every DQpin of SDRAM 10 CLK1/3 10pF 3.3pF SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 10 CLK0/2 SCL SDA A0 A1 A2 WP 47K

SA0 SA1 SA2

U0/U2 U4/U6 U1/U3 U5/U7

REV. 1 July 1998

KMM366S1723T
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS

Preliminary PC100 SDRAM MODULE

Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 8 50 Unit V V C W mA

Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current (Inputs) Input leakage current (I/O pins) Symbol VDD, VDDQ VIH VIL VOH VOL IIL IIL Min 3.0 2.0 -0.3 2.4 -8 -1.5 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 8 1.5 Unit V V V V V uA uA 1 2 IOH = -2mA IOL = 2mA 3 3,4 Note

Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V VOUT VDDQ.

CAPACITANCE

(VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200 mV) Pin Symbol CADD CIN CCKE CCLK CCS CDQM COUT Min 40 40 35 25 25 5 5 Max 60 60 55 35 35 15 15 Unit pF pF pF pF pF pF pF

Address (A0 ~ A11, BA0 ~ BA1) RAS, CAS, WE CKE (CKE0) Clock (CLK0, CLK2) CS (CS0, CS2) DQM (DQM0 ~ DQM7) DQ (DQ0 ~ DQ63)

REV. 1 July 1998

KMM366S1723T
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Symbol Test Condition Burst length = 1 tRC tRC(min) IOL = 0 mA CKE VIL(max), tCC = 15ns CKE & CLK VIL(max), tCC =

Preliminary PC100 SDRAM MODULE

CAS Latency

Version -8 960 -H 880 8 8 120 -L 880

Unit

Note

Operating current (One bank active) Precharge standby current in power-down mode

ICC1 ICC2P ICC2PS ICC2N

mA

mA

Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode ICC3P ICC3PS ICC3N ICC3NS

CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 15ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IOL = 0 mA Page burst 2Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V 3 2 1,200 920

mA 56 40 40 240 160 1,000 1,000 1,600 12 1,000 mA 920 mA mA 2 1 mA mA

mA

Active standby current in non power-down mode (One bank active)

Operating current (Burst mode) Refresh current Self refresh current

ICC4

ICC5 ICC6

Notes : 1. Measured with outputs open. 2. Refresh period is 64ms.

REV. 1 July 1998

KMM366S1723T
AC OPERATING TEST CONDITIONS
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
3.3V

Preliminary PC100 SDRAM MODULE

(VDD = 3.3V 0.3V, TA = 0 to 70C) Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
Vtt = 1.4V

Unit V V ns V

1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50

50

50pF

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol -8 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 68 16 20 20 48 Version -H 20 20 20 50 100 70 1 1 1 1 2 1 70 -L 20 20 20 50 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2 2 2 3 4 1 1 1 1 Unit Note

Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.

REV. 1 July 1998

KMM366S1723T

Preliminary PC100 SDRAM MODULE

AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter CAS latency=3 CAS latency=2 CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 3 3 3 3 2 1 1 6 6 tSAC Symbol Min CLK cycle time tCC 8 12 6 6 3 3 3 3 2 1 1 6 6 -8 Max 1000 Min 10 10 6 6 3 3 3 3 2 1 1 6 7 ns ns ns ns ns ns 3 3 3 3 2 -H Max 1000 Min 10 12 6 7 ns 2 ns 1,2 -L Max 1000 ns 1 Unit Note

Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.

REV. 1 July 1998

KMM366S1723T
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
KMM366S1723T- G8
Frequency 125MHz (8.0ns) 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) CAS Latency 3 3 2 2 2 tRC 68ns 9 7 6 6 5 tRAS 48ns 6 5 4 4 4 tRP 20ns 3 2 2 2 2 tRRD 16ns 2 2 2 2 2

Preliminary PC100 SDRAM MODULE

(Unit : Number of clock) tRCD 20ns 3 2 2 2 2 tCCD 8ns 1 1 1 1 1 tCDL 8ns 1 1 1 1 1 tRDL 8ns 1 1 1 1 1

KMM366S1723T- GH
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) CAS Latency 2 2 2 2 2 tRC 70ns 7 6 6 5 5 tRAS 50ns 5 5 4 4 3 tRP 20ns 2 2 2 2 2 tRRD 20ns 2 2 2 2 2 tRCD 20ns 2 2 2 2 2 tCCD 10ns 1 1 1 1 1

(Unit : Number of clock) tCDL 10ns 1 1 1 1 1 tRDL 10ns 1 1 1 1 1

KMM366S1723T- GL
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) CAS Latency 3 2 2 2 2 tRC 70ns 7 6 6 5 5 tRAS 50ns 5 5 4 4 3 tRP 20ns 2 2 2 2 2 tRRD 20ns 2 2 2 2 2 tRCD 20ns 2 2 2 2 2 tCCD 10ns 1 1 1 1 1

(Unit : Number of clock) tCDL 10ns 1 1 1 1 1 tRDL 10ns 1 1 1 1 1

REV. 1 July 1998

KMM366S1723T
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H
CKEn-1 CKEn CS RAS CAS

Preliminary PC100 SDRAM MODULE

A11, A9 ~ A0

WE

DQM

BA0,1

A10/AP

Note

H H

X H L H X X

L L L H

L L H X L H

L L H X H L

L H H X H H

X X

OP code X

1,2 3 3

X X X V V

X Row address L H
Column address (A0 ~ A9) Column address (A0 ~ A9)

3 3

Bank active & row addr. Read & column address Write & column address Burst stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable

L L

4 4,5 4 4,5 6

H H H

X X X

L L L H L

H H L X V X X H X V X

L H H X V X X H X V

L L L X V X X H X V

X X X

L H X

V X

L H

H L H

L H L

X X X X X X V X X 7

X H L

L H H

H L

H L

X H

X H

X H

(V=Valid, X=Dont care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

REV. 1 July 1998

KMM366S1723T
PACKAGE DIMENSIONS

Preliminary PC100 SDRAM MODULE

Units : Inches (Millimeters)

5.250 (133.350) 0.118 (3.000) 0.375 (9.525) 0.096 (2.44) 0.125 (3.175) 5.014 (127.350)

0.089 (2.26)

R 0.050+0.04 (R 1.27+0.1) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100)

1.375 (34.925)

0.118 (3.000)

.118DIA 0.004 (3.000DIA 0.100) 0.350 (8.890)

A 0.250 (6.350) .450 (11.430) 1.450 (36.830)

B 0.250 (6.350)

2.150 (54.61) 4.550 (115.57)

0.100 Min (2.540 Min)

0.700 (17.780)

0.100 Max (2.54 Max) (5.08 Min) 0.200 Min

0.050 0.0039 (1.270 0.10)

0.250 (6.350)

0.250 (6.350)

(2.540 Min)

0.100 Min

0.039 0.002 (1.000 0.050)

0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)

0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)

0.010 Max (0.250 Max) 0.050 (1.270)

Detail A

Detail B

Detail C

Tolerances : .005(.13) unless otherwise specified The used device is 16Mx8 SDRAM, TSOP SDRAM Part No. : KM48S16030T

REV. 1 July 1998