Freescale Semiconductor Data Sheet: Technical Data

Document Number: KL16P64M48SF5 Rev. 2, 10/2013

KL16 Sub-Family Data Sheet

Supports the following: MKL16Z32VFM4, MKL16Z64VFM4, MKL16Z128VFM4, MKL16Z32VFT4, MKL16Z64VFT4, MKL16Z128VFT4, MKL16Z32VLH4, MKL16Z64VLH4, MKL16Z128VLH4
Features Operating Characteristics Voltage range: 1.71 to 3.6 V Flash write voltage range: 1.71 to 3.6 V Temperature range (ambient): -40 to 105C Performance Up to 48 MHz ARM Cortex-M0+ core Memories and memory interfaces 128 KB program flash memory 16 KB RAM Clocks 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator Multi-purpose clock source System peripherals Nine low-power modes to provide power optimization based on application requirements 4-channel DMA controller, supporting up to 63 request sources COP Software watchdog Low-leakage wakeup unit SWD interface and Micro Trace buffer Bit Manipulation Engine (BME)

KL16P64M48SF5

Security and integrity modules 80-bit unique identification (ID) number per chip Human-machine interface Low-power hardware touch sensor interface (TSI) General-purpose input/output Analog modules 16-bit SAR ADC 12-bit DAC Analog comparator (CMP) containing a 6-bit DAC and programmable reference input Timers Six channel Timer/PWM (TPM) Two 2-channel Timer/PWM (TPM) Periodic interrupt timers 16-bit low-power timer (LPTMR) Real-time clock Communication interfaces Two 16-bit SPI modules Two I2C modules I2S (SAI) module One low power UART module Two UART modules

Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2013 Freescale Semiconductor, Inc.

Table of Contents
1 Ordering parts...........................................................................3 1.1 Determining valid orderable parts......................................3 2 Part identification......................................................................3 2.1 Description.........................................................................3 2.2 Format...............................................................................3 2.3 Fields.................................................................................3 2.4 Example............................................................................4 3 Terminology and guidelines......................................................4 3.1 Definition: Operating requirement......................................4 3.2 Definition: Operating behavior...........................................4 3.3 Definition: Attribute............................................................5 3.4 Definition: Rating...............................................................5 3.5 Result of exceeding a rating..............................................6 3.6 Relationship between ratings and operating requirements......................................................................6 3.7 Guidelines for ratings and operating requirements............6 3.8 Definition: Typical value.....................................................7 3.9 Typical value conditions....................................................8 4 Ratings......................................................................................8 4.1 Thermal handling ratings...................................................8 4.2 Moisture handling ratings..................................................8 4.3 ESD handling ratings.........................................................8 4.4 Voltage and current operating ratings...............................9 5 General.....................................................................................9 5.1 AC electrical characteristics..............................................9 5.2 Nonswitching electrical specifications...............................10 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 Voltage and current operating requirements.........10 LVD and POR operating requirements.................11 Voltage and current operating behaviors..............11 Power mode transition operating behaviors..........12 Power consumption operating behaviors..............13 EMC radiated emissions operating behaviors.......19 Designing with radiated emissions in mind...........20 Capacitance attributes..........................................20 5.3 Switching specifications.....................................................20 5.3.1 5.3.2 Device clock specifications...................................20 General switching specifications...........................21 5.4 Thermal specifications.......................................................21 5.4.1 5.4.2 Thermal operating requirements...........................21 Thermal attributes.................................................21

6 Peripheral operating requirements and behaviors....................22 6.1 Core modules....................................................................22 6.1.1 SWD electricals ....................................................22

6.2 System modules................................................................23 6.3 Clock modules...................................................................24 6.3.1 6.3.2 MCG specifications...............................................24 Oscillator electrical specifications.........................25

6.4 Memories and memory interfaces.....................................28 6.4.1 Flash electrical specifications................................28

6.5 Security and integrity modules..........................................29 6.6 Analog...............................................................................29 6.6.1 6.6.2 6.6.3 ADC electrical specifications.................................29 CMP and 6-bit DAC electrical specifications.........34 12-bit DAC electrical characteristics.....................36

6.7 Timers................................................................................39 6.8 Communication interfaces.................................................39 6.8.1 6.8.2 6.8.3 6.8.4 SPI switching specifications..................................39 Inter-Integrated Circuit Interface (I2C) timing........43 UART....................................................................44 I2S/SAI switching specifications............................45

6.9 Human-machine interfaces (HMI)......................................49 6.9.1 TSI electrical specifications...................................49

7 Dimensions...............................................................................49 7.1 Obtaining package dimensions.........................................49 8 Pinout........................................................................................50 8.1 KL16 Signal Multiplexing and Pin Assignments................50 8.2 KL16 pinouts.....................................................................52

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Ordering parts

1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PKL16 and MKL16

2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

2.2 Format
Part numbers for this device have the following format: Q KL## A FFF R T PP CC N

2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid):
Field Q KL## A FFF Qualification status Kinetis family Key attribute Program flash memory size Description Values M = Fully qualified, general market flow P = Prequalification KL16 Z = Cortex-M0+ 32 = 32 KB 64 = 64 KB 128 = 128 KB (Blank) = Main A = Revision after main Table continues on the next page...

Silicon revision

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Terminology and guidelines Field T PP Package identifier Description Temperature range (C) V = 40 to 105 FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) 4 = 48 MHz R = Tape and reel Values

CC N

Maximum CPU frequency (MHz) Packaging type

2.4 Example
This is an example part number: MKL16Z128VFM4

3 Terminology and guidelines

3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.

3.1.1 Example
This is an example of an operating requirement:
Symbol VDD Description 1.0 V core supply voltage 0.9 Min. 1.1 Max. V Unit

3.2 Definition: Operating behavior

An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.

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Terminology and guidelines

3.2.1 Example
This is an example of an operating behavior:
Symbol IWP Description Digital I/O weak pullup/ 10 pulldown current Min. 130 Max. A Unit

3.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.

3.3.1 Example
This is an example of an attribute:
Symbol CIN_D Description Input capacitance: digital pins Min. 7 Max. pF Unit

3.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: Operating ratings apply during operation of the chip. Handling ratings apply when the chip is not powered.

3.4.1 Example
This is an example of an operating rating:
Symbol VDD Description 1.0 V core supply voltage 0.3 Min. 1.2 Max. V Unit

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Terminology and guidelines

3.5 Result of exceeding a rating

40 Failures in time (ppm) 30

20

The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.

10

0 Operating rating Measured characteristic

3.6 Relationship between ratings and operating requirements

tin g in rat g( m ) in. era tin g u req ire m t en (m in. ) u req ire m t en (m ax .) in rat g( ma x.) tin g tin g

Op

era

Op

Op

era

Op

era

Fatal range
Expected permanent failure

Degraded operating range

- No permanent failure - Possible decreased life - Possible incorrect operation

Normal operating range

- No permanent failure - Correct operation

Degraded operating range

- No permanent failure - Possible decreased life - Possible incorrect operation

Fatal range
Expected permanent failure

Operating (power on)

mi n.) nd lin g ma x.)

n Ha

dli

ng

rat

( ing

( ing rat

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Fatal range
Expected permanent failure

Handling range
No permanent failure

Fatal range
Expected permanent failure

Handling (power off)

3.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements: Never exceed any of the chips ratings. During normal operation, dont exceed any of the chips operating requirements. If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
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Terminology and guidelines

3.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that: Lies within the range of values specified by the operating behavior Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.

3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol IWP Description Digital I/O weak pullup/pulldown current 10 Min. 70 Typ. 130 Max. A Unit

3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions:
5000 4500 4000 3500 IDD_STOP (A) 3000 2500 2000 1500 1000 500 0 0.90 0.95 1.00 VDD (V) 1.05 1.10 TJ 150 C 105 C 25 C 40 C

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Ratings

3.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as specified):
Table 1. Typical value conditions
Symbol TA VDD Description Ambient temperature 3.3 V supply voltage Value 25 3.3 Unit C V

4 Ratings
4.1 Thermal handling ratings
Table 2. Thermal handling ratings
Symbol TSTG TSDR Description Storage temperature Solder temperature, lead-free Min. 55 Max. 150 260 Unit C C Notes 1 2

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.2 Moisture handling ratings

Table 3. Moisture handling ratings
Symbol MSL Description Moisture sensitivity level Min. Max. 3 Unit Notes 1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

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General

4.3 ESD handling ratings

Table 4. ESD handling ratings
Symbol VHBM VCDM ILAT Description Electrostatic discharge voltage, human body model Electrostatic discharge voltage, charged-device model Latch-up current at ambient temperature of 105 C Min. 2000 500 100 Max. +2000 +500 +100 Unit V V mA Notes 1 2 3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

4.4 Voltage and current operating ratings

Table 5. Voltage and current operating ratings
Symbol VDD IDD VIO ID VDDA Description Digital supply voltage Digital supply current IO pin input voltage Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage Min. 0.3 0.3 25 VDD 0.3 Max. 3.8 120 VDD + 0.3 25 VDD + 0.3 Unit V mA V mA V

5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure.

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General

Figure 1. Input signal measurement reference

All digital I/O switching characteristics, unless otherwise specified, assume the output pins have the following characteristics. CL=30 pF loads Slew rate disabled Normal drive strength

5.2 Nonswitching electrical specifications

5.2.1 Voltage and current operating requirements
Table 6. Voltage and current operating requirements
Symbol VDD VDDA Description Supply voltage Analog supply voltage Min. 1.71 1.71 0.1 0.1 0.7 VDD 0.75 VDD Max. 3.6 3.6 0.1 0.1 Unit V V V V V V Notes

VDD VDDA VDD-to-VDDA differential voltage VSS VSSA VSS-to-VSSA differential voltage VIH Input high voltage 2.7 V VDD 3.6 V 1.7 V VDD 2.7 V VIL Input low voltage 2.7 V VDD 3.6 V 1.7 V VDD 2.7 V VHYS IICIO Input hysteresis IO pin negative DC injection current single pin VIN < VSS-0.3V IICcont Contiguous pin DC injection current regional limit, includes sum of negative injection currents of 16 contiguous pins Negative current injection

0.06 VDD -3

0.35 VDD 0.3 VDD

V V V 1 mA

-25

mA

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General

Table 6. Voltage and current operating requirements (continued)

Symbol VODPU VRAM Description Open drain pullup voltage level VDD voltage required to retain RAM Min. VDD 1.2 Max. VDD Unit V V Notes 2

1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD.

5.2.2 LVD and POR operating requirements

Table 7. VDD supply LVD and POR operating requirements
Symbol VPOR VLVDH Description Falling VDD POR detect voltage Falling low-voltage detect threshold high range (LVDV = 01) Low-voltage warning thresholds high range VLVW1H VLVW2H VLVW3H VLVW4H VHYSH VLVDL Level 1 falling (LVWV = 00) Level 2 falling (LVWV = 01) Level 3 falling (LVWV = 10) Level 4 falling (LVWV = 11) Low-voltage inhibit reset/recover hysteresis high range Falling low-voltage detect threshold low range (LVDV=00) Low-voltage warning thresholds low range VLVW1L VLVW2L VLVW3L VLVW4L VHYSL VBG tLPO Level 1 falling (LVWV = 00) Level 2 falling (LVWV = 01) Level 3 falling (LVWV = 10) Level 4 falling (LVWV = 11) Low-voltage inhibit reset/recover hysteresis low range Bandgap voltage reference Internal low power oscillator period factory trimmed 1.74 1.84 1.94 2.04 0.97 900 1.80 1.90 2.00 2.10 40 1.00 1000 1.86 1.96 2.06 2.16 1.03 1100 V V V V mV V s 2.62 2.72 2.82 2.92 1.54 2.70 2.80 2.90 3.00 60 1.60 2.78 2.88 2.98 3.08 1.66 V V V V mV V 1 Min. 0.8 2.48 Typ. 1.1 2.56 Max. 1.5 2.64 Unit V V Notes 1

1. Rising thresholds are falling threshold + hysteresis voltage

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General

5.2.3 Voltage and current operating behaviors

Table 8. Voltage and current operating behaviors
Symbol VOH Description Output high voltage Normal drive pad (except RESET_b) 2.7 V VDD 3.6 V, IOH = -5 mA 1.71 V VDD 2.7 V, IOH = -2.5 mA VOH Output high voltage High drive pad (except RESET_b) 2.7 V VDD 3.6 V, IOH = -20 mA 1.71 V VDD 2.7 V, IOH = -10 mA IOHT VOL Output high current total for all ports Output low voltage Normal drive pad 2.7 V VDD 3.6 V, IOL = 5 mA 1.71 V VDD 2.7 V, IOL = 2.5 mA VOL Output low voltage High drive pad 2.7 V VDD 3.6 V, IOL = 20 mA 1.71 V VDD 2.7 V, IOL = 10 mA IOLT IIN IIN IIN IOZ RPU Output low current total for all ports Input leakage current (per pin) for full temperature range Input leakage current (per pin) at 25 C Input leakage current (total all pins) for full temperature range Hi-Z (off-state) leakage current (per pin) Internal pullup resistors 20 0.5 0.5 100 1 0.025 65 1 50 V V mA A A A A k 4 3 3 3 0.5 0.5 V V 1 Min. VDD 0.5 VDD 0.5 Max. Unit V V 1,2 VDD 0.5 VDD 0.5 100 V V mA 1 Notes 1, 2

1. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 2. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 3. Measured at VDD = 3.6 V 4. Measured at VDD supply voltage = VDD min and Vinput = VSS

5.2.4 Power mode transition operating behaviors

All specifications except tPOR and VLLSxRUN recovery times in the following table assume this clock configuration: CPU and system clocks = 48 MHz Bus and flash clock = 24 MHz FEI clock mode
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General

POR and VLLSxRUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 9. Power mode transition operating behaviors
Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first instruction across the operating temperature range of the chip. VLLS0 RUN VLLS1 RUN VLLS3 RUN LLS RUN VLPS RUN STOP RUN 1. Normal boot (FTFA_FOPT[LPBOOT]=11). 4.5 5.0 s 4.5 5.0 s 4.5 5.0 s 47 54 s 105 117 s 106 120 s Min. Typ. Max. 300 Unit s Notes 1

5.2.5 Power consumption operating behaviors

Table 10. Power consumption operating behaviors
Symbol IDDA Description Analog supply current Min. Typ. Max. See note Unit mA Notes 1 2 6.1 mA

IDD_RUNCO_ Run mode current in compute operation - 48 MHz core / 24 MHz flash / bus disabled, LPTMR CM running using 4 MHz internal reference clock, CoreMark benchmark code executing from flash at 3.0 V IDD_RUNCO Run mode current in compute operation - 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash at 3.0 V IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash at 3.0 V

3 3.8 5.9 mA 3 4.6 6.1 mA

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General

Table 10. Power consumption operating behaviors (continued)

Symbol IDD_RUN Description Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash at 3.0 V at 25 C at 70 C at 125 C IDD_WAIT Wait mode current - core disabled / 48 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled at 3.0 V Wait mode current - core disabled / 24 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled at 3.0 V 6.0 6.2 6.3 6.5 6.8 7.1 mA mA mA 3 2.7 5.7 mA Min. Typ. Max. Unit Notes 3, 4

IDD_WAIT

3 2.1 5.5 mA

IDD_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus at 3.0 V IDD_VLPRCO Very-low-power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus _CM clock disabled, LPTMR running with 4 MHz internal reference clock, CoreMark benchmark code executing from flash at 3.0 V IDD_VLPRCO Very-low-power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code of while(1) loop executing from flash at 3.0 V IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash at 3.0 V Very-low-power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash at 3.0 V Very-low-power wait mode current - core disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled at 3.0 V

3 2.2 4.1 mA

5 732 A

6 161 367 A

6 185 372 A

IDD_VLPR

4, 6 256 420 A

IDD_VLPW

110

355

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General

Table 10. Power consumption operating behaviors (continued)

Symbol IDD_STOP Description Stop mode current at 3.0 V at 25 C at 50 C at 70 C at 85 C at 105 C IDD_VLPS Very-low-power stop mode current at 3.0 V at 25 C at 50 C at 70 C at 85 C at 105 C IDD_LLS Low-leakage stop mode current at 3.0 V at 25 C at 50 C at 70 C at 85 C at 105 C IDD_VLLS3 Very-low-leakage stop mode 3 current at 3.0 V at 25 C at 50 C at 70 C at 85 C at 105 C IDD_VLLS1 Very-low-leakage stop mode 1 current at 3.0V at 25C at 50C at 70C at 85C at 105C IDD_VLLS0 Very-low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 0) at 3.0 V at 25 C at 50 C at 70 C at 85 C at 105 C 310 778 1928 3906 10097 844 3861 13055 15457 23116 0.7 1.2 2.2 4.8 12.4 1.3 11.7 12.6 15.3 22.6 nA A 1.3 2.3 4.7 8.5 19.5 3.0 17.6 19.5 24.1 35.3 A 1.7 3.2 5.8 11.6 26.8 3.3 34.9 38.5 43.8 61.7 A 2.3 5.2 10.5 19.3 42.3 8.4 18.3 26.1 58.5 105.1 A 301 311 342 382 481 428 722 758 809 929 A Min. Typ. Max. Unit Notes

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General

Table 10. Power consumption operating behaviors (continued)

Symbol IDD_VLLS0 Description Very-low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 1) at 3.0 V at 25 C at 50 C at 70 C at 85 C at 105 C 139 600 1674 3554 9580 747 3418 11143 13683 20463 nA Min. Typ. Max. Unit Notes 7

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG configured for PEE mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized for balanced. 3. MCG configured for FEI mode. 4. Incremental current consumption from peripheral activity is not included. 5. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized for balanced. 6. MCG configured for BLPI mode. 7. No brownout

Table 11. Low power mode peripheral adders typical value

Symbol IIREFSTEN4MHz Description -40 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. 32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 32 kHz IRC enabled. External 4 MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled. External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled. VLLS1 VLLS3 LLS VLPS STOP ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 22 22 22 22 22 22 A 56 25 56 Temperature (C) 50 56 70 56 85 56 105 56 A Unit

IIREFSTEN32KHz

52

52

52

52

52

52

IEREFSTEN4MHz

250

262

266

268

272

274

uA

IEREFSTEN32KHz

440 440 490 510 510

490 490 490 560 560

540 540 540 560 560

560 560 560 560 560

570 570 570 610 610

580 580 680 680 680 nA

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General

Table 11. Low power mode peripheral adders typical value (continued)
Symbol IRTC Description -40 RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. MCGIRCLK (4 MHz internal reference clock) OSCERCLK (4 MHz external crystal) ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents. MCGIRCLK (4 MHz internal reference clock) OSCERCLK (4 MHz external crystal) IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode. ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low-power mode using the internal clock and continuous conversions. 86 275 45 86 288 45 86 290 45 86 295 45 86 300 45 86 306 45 A 66 259 66 271 66 275 66 277 66 281 66 283 A 432 25 357 Temperature (C) 50 388 70 475 85 532 105 810 nA Unit

IUART

IADC

366

366

366

366

366

366

5.2.5.1

Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions: MCG in FBE for run mode, and BLPE for VLPR mode No GPIOs toggled Code execution from flash with cache enabled For the ALLOFF curve, all peripheral clocks are disabled except FTFA

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General

Figure 2. Run mode supply current vs. core frequency

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General

Figure 3. VLPR mode current vs. core frequency

5.2.6 EMC radiated emissions operating behaviors

Table 12. EMC radiated emissions operating behaviors
Symbol VRE1 VRE2 VRE3 VRE4 VRE_IEC Description Radiated emissions voltage, band 1 Radiated emissions voltage, band 2 Radiated emissions voltage, band 3 Radiated emissions voltage, band 4 IEC level Frequency band (MHz) 0.1550 50150 150500 5001000 0.151000 Typ. 16 18 11 13 M Unit dBV dBV dBV dBV 2, 3 Notes 1, 2

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated EmissionsTEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported

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General emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VDD = 3.3 V, TA = 25 C, fOSC = 8 MHz (crystal), fSYS = 48 MHz, fBUS = 24 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated EmissionsTEM Cell and Wideband TEM Cell Method

5.2.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for EMC design.

5.2.8 Capacitance attributes

Table 13. Capacitance attributes
Symbol CIN Description Input capacitance Min. Max. 7 Unit pF

5.3 Switching specifications

5.3.1 Device clock specifications
Table 14. Device clock specifications
Symbol fSYS fBUS fFLASH fLPTMR fSYS fBUS fFLASH fLPTMR fERCLK Description Normal run mode System and core clock Bus clock Flash clock LPTMR clock VLPR and VLPS System and core clock Bus clock Flash clock LPTMR clock2 External reference clock modes1 4 1 1 24 16 16 MHz MHz MHz MHz MHz MHz 48 24 24 24 MHz MHz MHz MHz Min. Max. Unit

fLPTMR_ERCLK LPTMR external reference clock Table continues on the next page...

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General

Table 14. Device clock specifications (continued)

Symbol fosc_hi_2 fTPM fUART0 Description Oscillator crystal or resonator frequency high frequency mode (high range) (MCG_C2[RANGE]=1x) TPM asynchronous clock UART0 asynchronous clock Min. Max. 16 8 8 Unit MHz MHz MHz

1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or from VLPR. 2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

5.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO and UART signals.
Table 15. General switching specifications
Description GPIO pin interrupt pulse width (digital glitch filter disabled) Synchronous path External RESET and NMI pin interrupt pulse width Asynchronous path GPIO pin interrupt pulse width Asynchronous path Port rise and fall time 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75 pF load Min. 1.5 100 16 Max. 36 Unit Bus clock cycles ns ns ns Notes 1 2 2 3

5.4 Thermal specifications

5.4.1 Thermal operating requirements
Table 16. Thermal operating requirements
Symbol TJ TA Description Die junction temperature Ambient temperature Min. 40 40 Max. 125 105 Unit C C

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Peripheral operating requirements and behaviors

5.4.2 Thermal attributes

Table 17. Thermal attributes
Board type Single-layer (1S) Four-layer (2s2p) Single-layer (1S) Four-layer (2s2p) Symbol RJA RJA RJMA RJMA RJB RJC JT Description Thermal resistance, junction to ambient (natural convection) Thermal resistance, junction to ambient (natural convection) Thermal resistance, junction to ambient (200 ft./min. air speed) Thermal resistance, junction to ambient (200 ft./min. air speed) Thermal resistance, junction to board Thermal resistance, junction to case Thermal characterization parameter, junction to package top outside center (natural convection) 64 LQFP 71 53 59 46 35 21 6 48 QFN 83 30 68 24 12 2.3 5 32 QFN 98 34 82 28 13 2.3 8 Unit C/W C/W C/W C/W C/W C/W C/W 2 3 4 Notes 1

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental ConditionsForced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions Natural Convection (Still Air).

6 Peripheral operating requirements and behaviors

6.1 Core modules
6.1.1 SWD electricals
Table 18. SWD full voltage range electricals
Symbol J1 Description Operating voltage SWD_CLK frequency of operation Serial wire debug J2 SWD_CLK cycle period Table continues on the next page... 0 1/J1 25 MHz ns Min. 1.71 Max. 3.6 Unit V

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Peripheral operating requirements and behaviors

Table 18. SWD full voltage range electricals (continued)

Symbol J3 Description SWD_CLK clock pulse width Serial wire debug J4 J9 J10 J11 J12 SWD_CLK rise and fall times SWD_DIO input data setup time to SWD_CLK rise SWD_DIO input data hold time after SWD_CLK rise SWD_CLK high to SWD_DIO data valid SWD_CLK high to SWD_DIO high-Z 20 10 0 5 3 32 ns ns ns ns ns ns Min. Max. Unit

J2 J3 J3

SWD_CLK (input)

J4

J4

Figure 4. Serial wire clock input timing

SWD_CLK
J9 J10

SWD_DIO
J11

Input data valid

SWD_DIO
J12

Output data valid

SWD_DIO
J11

SWD_DIO

Output data valid

Figure 5. Serial wire data timing

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Peripheral operating requirements and behaviors

6.2 System modules

There are no specifications necessary for the device's system modules.

6.3 Clock modules

6.3.1 MCG specifications
Table 19. MCG specifications
Symbol fints_ft fints_t Description Internal reference frequency (slow clock) factory trimmed at nominal VDD and 25 C Internal reference frequency (slow clock) user trimmed Min. 31.25 Typ. 32.768 0.3 Max. 39.0625 0.6 Unit kHz kHz %fdco 1 Notes

fdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature using C3[SCTRIM] and C4[SCFTRIM] fdco_t fdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 070 C Internal reference frequency (fast clock) factory trimmed at nominal VDD and 25 C Frequency deviation of internal reference clock (fast clock) over temperature and voltage factory trimmed at nominal VDD and 25 C Internal reference frequency (fast clock) user trimmed at nominal VDD and 25 C Loss of external clock minimum frequency RANGE = 00 Loss of external clock minimum frequency RANGE = 01, 10, or 11 FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS = 00) 640 ffll_ref Mid range (DRS = 01) 1280 ffll_ref fdco_t_DMX32 DCO output frequency Low range (DRS = 00) 732 ffll_ref Mid range (DRS = 01) 1464 ffll_ref

+0.5/-0.7 0.4

3 1.5

%fdco %fdco

1, 2 1, 2

fintf_ft fintf_ft

4 +1/-2

MHz %fintf_ft 2

fintf_t floc_low floc_high

3 (3/5) x fints_t (16/5) x fints_t 31.25 20 40

MHz kHz kHz

20.97 41.94 23.99 47.97

39.0625 25 48

kHz MHz MHz MHz MHz 5, 6 3, 4

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 19. MCG specifications (continued)

Symbol Jcyc_fll tfll_acquire fvco Ipll Description FLL period jitter fVCO = 48 MHz FLL target frequency acquisition time PLL VCO operating frequency PLL operating current PLL at 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) PLL operating current PLL at 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) PLL reference frequency range PLL period jitter (RMS) fvco = 48 MHz fvco = 100 MHz Jacc_pll PLL accumulated jitter over 1s (RMS) fvco = 48 MHz fvco = 100 MHz Dlock Dunl tpll_lock Lock entry frequency tolerance Lock exit frequency tolerance Lock detector detection time 1.49 4.47 1350 600 2.98 5.97 150 10-6 + 1075(1/ fpll_ref) ps ps % % s 11 120 50 ps ps 10 48.0 1060 100 MHz A 9 1 ms 8 Min. Typ. 180 Max. Unit ps Notes 7

Ipll

2.0

600

4.0

A MHz

fpll_ref Jcyc_pll

10

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. Excludes any oscillator currents that are also consuming power while PLL is in operation. 10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

6.3.2 Oscillator electrical specifications

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Peripheral operating requirements and behaviors

6.3.2.1
Symbol VDD IDDOSC

Oscillator DC electrical specifications

Description Supply voltage Supply current low-power mode (HGO=0) 32 kHz 4 MHz 8 MHz (RANGE=01) 16 MHz 24 MHz 32 MHz Min. 1.71

Table 20. Oscillator DC electrical specifications

Typ. 500 200 300 950 1.2 1.5 Max. 3.6 Unit V 1 nA A A A mA mA 1 25 400 500 2.5 3 4 10 1 200 M M M M k k k A A A mA mA mA 2, 3 2, 3 2, 4 Notes

IDDOSC

Supply current high gain mode (HGO=1) 32 kHz 4 MHz 8 MHz (RANGE=01) 16 MHz 24 MHz 32 MHz

Cx Cy RF

EXTAL load capacitance XTAL load capacitance Feedback resistor low-frequency, low-power mode (HGO=0) Feedback resistor low-frequency, high-gain mode (HGO=1) Feedback resistor high-frequency, low-power mode (HGO=0) Feedback resistor high-frequency, high-gain mode (HGO=1)

RS

Series resistor low-frequency, low-power mode (HGO=0) Series resistor low-frequency, high-gain mode (HGO=1) Series resistor high-frequency, low-power mode (HGO=0) Series resistor high-frequency, high-gain mode (HGO=1)

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 20. Oscillator DC electrical specifications (continued)

Symbol Vpp5 Description Peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (HGO=1) Peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (HGO=1) Min. Typ. 0.6 Max. Unit V Notes

VDD

0.6

VDD

1. VDD=3.3 V, Temperature =25 C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices.

6.3.2.2
Symbol fosc_lo fosc_hi_1

Oscillator frequency specifications

Description Oscillator crystal or resonator frequency lowfrequency mode (MCG_C2[RANGE]=00) Oscillator crystal or resonator frequency highfrequency mode (low range) (MCG_C2[RANGE]=01) Oscillator crystal or resonator frequency high frequency mode (high range) (MCG_C2[RANGE]=1x) Input clock frequency (external clock mode) Input clock duty cycle (external clock mode) Crystal startup time 32 kHz low-frequency, low-power mode (HGO=0) Crystal startup time 32 kHz low-frequency, high-gain mode (HGO=1) Crystal startup time 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) Crystal startup time 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) Min. 32 3

Table 21. Oscillator frequency specifications

Typ. Max. 40 8 Unit kHz MHz Notes

fosc_hi_2

32

MHz

fec_extal tdc_extal tcst

40

50 750 250 0.6

48 60

MHz % ms ms ms

1, 2 3, 4

ms

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency.

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Peripheral operating requirements and behaviors 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set.

6.4 Memories and memory interfaces

6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module. 6.4.1.1 Flash timing specifications program and erase

The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead.
Table 22. NVM program/erase timing specifications
Symbol thvpgm4 thversscr thversall Description Longword Program high-voltage time Sector Erase high-voltage time Erase All high-voltage time Min. Typ. 7.5 13 52 Max. 18 113 452 Unit s ms ms 1 1 Notes

1. Maximum time based on expectations at cycling end-of-life.

6.4.1.2
Symbol trd1sec1k tpgmchk trdrsrc tpgm4 tersscr trd1all trdonce tpgmonce tersall tvfykey

Flash timing specifications commands

Description Read 1s Section execution time (flash sector) Program Check execution time Read Resource execution time Program Longword execution time Erase Flash Sector execution time Read 1s All Blocks execution time Read Once execution time Program Once execution time Erase All Blocks execution time Verify Backdoor Access Key execution time Min.

Table 23. Flash command timing specifications

Typ. 65 14 65 88 Max. 60 45 30 145 114 1.8 25 650 30 Unit s s s s ms ms s s ms s 2 1 1 2 Notes 1 1 1

1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life.

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Peripheral operating requirements and behaviors

6.4.1.3
Symbol IDD_PGM IDD_ERS

Flash high voltage current behaviors

Description Average current adder during high voltage flash programming operation Average current adder during high voltage flash erase operation Min.

Table 24. Flash high voltage current behaviors

Typ. 2.5 1.5 Max. 6.0 4.0 Unit mA mA

6.4.1.4
Symbol

Reliability specifications
Description

Table 25. NVM reliability specifications

Min. Program Flash 5 20 10 K Typ.1 50 100 50 K Max. Unit years years cycles 2 Notes

tnvmretp10k Data retention after up to 10 K cycles tnvmretp1k nnvmcycp Data retention after up to 1 K cycles Cycling endurance

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 C Tj 125 C.

6.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 26 and Table 27 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications.

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Peripheral operating requirements and behaviors

6.6.1.1
Symbol VDDA VDDA VSSA VREFH VREFL VADIN

16-bit ADC operating conditions

Description Supply voltage Supply voltage Ground voltage ADC reference voltage high ADC reference voltage low Input voltage 16-bit differential mode All other modes Conditions Absolute Delta to VDD (VDD VDDA) Delta to VSS (VSS VSSA)

Table 26. 16-bit ADC operating conditions

Min. 1.71 -100 -100 1.13 VSSA VREFL VREFL 13-bit / 12-bit modes fADCK < 4 MHz 13-bit mode 16-bit mode 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 818.330 Ksps 1.0 2.0 5 18.0 12.0 k MHz MHz 5 5 6 Typ.1 0 0 VDDA VSSA 8 4 2 Max. 3.6 +100 +100 VDDA VSSA 31/32 * VREFH VREFH 10 5 5 k 4 pF Unit V mV mV V V V 2 2 3 3 Notes

CADIN

Input capacitance

16-bit mode 8-bit / 10-bit / 12-bit modes

RADIN RAS

Input resistance Analog source resistance

fADCK fADCK Crate

ADC conversion clock frequency ADC conversion clock frequency ADC conversion rate

Crate

ADC conversion rate

16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 461.467 Ksps

1. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSSA. 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

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Peripheral operating requirements and behaviors

SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT

Z ADIN
SIMPLIFIED CHANNEL SELECT CIRCUIT

Z AS R AS V ADIN V AS C AS

Pad leakage due to input protection

R ADIN

ADC SAR ENGINE

R ADIN INPUT PIN

R ADIN

INPUT PIN

R ADIN C ADIN

INPUT PIN

Figure 6. ADC input impedance equivalency diagram

6.6.1.2

16-bit ADC electrical characteristics

Table 27. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)

Symbol IDDA_ADC

Description Supply current ADC asynchronous clock source

Conditions1. ADLPC = 1, ADHSC = 0 ADLPC = 1, ADHSC = 1 ADLPC = 0, ADHSC = 0 ADLPC = 0, ADHSC = 1

Min. 0.215 1.2 2.4 3.0 4.4

Typ.2 2.4 4.0 5.2 6.2

Max. 1.7 3.9 6.1 7.3 9.5

Unit mA MHz MHz MHz MHz LSB4

Notes 3 tADACK = 1/ fADACK

fADACK

Sample Time TUE Total unadjusted error Differential nonlinearity

See Reference Manual chapter for sample times 12-bit modes <12-bit modes 12-bit modes <12-bit modes 4 1.4 0.7 0.2 1.0 0.5 6.8 2.1 1.1 to +1.9 0.3 to 0.5 2.7 to +1.9 0.7 to +0.5 LSB4 5 LSB4 5 5

DNL

INL

Integral nonlinearity

12-bit modes <12-bit modes

Table continues on the next page...

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Table 27. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol EFS EQ Description Full-scale error Quantization error Conditions1. 12-bit modes <12-bit modes 16-bit modes 13-bit modes Min. Typ.2 4 1.4 1 to 0 Max. 5.4 1.8 0.5 6 12.8 11.9 14.5 13.8 bits bits LSB4 Unit LSB4 Notes VADIN = VDDA5

ENOB

Effective number 16-bit differential mode of bits Avg = 32 Avg = 4 16-bit single-ended mode Avg = 32 Avg = 4

12.2 11.4

13.9 13.1 6.02 ENOB + 1.76

bits bits dB 7

SINAD THD

Signal-to-noise plus distortion Total harmonic distortion

See ENOB 16-bit differential mode Avg = 32 16-bit single-ended mode Avg = 32

-94 -85

dB dB 7

SFDR

Spurious free dynamic range

16-bit differential mode Avg = 32 16-bit single-ended mode Avg = 32 82 78 95 90 IIn RAS dB dB mV

EIL

Input leakage error

IIn = leakage current (refer to the MCU's voltage and current operating ratings)

Temp sensor slope VTEMP25 Temp sensor voltage

Across the full temperature range of the device 25 C

1.55 706

1.62 716

1.69 726

mV/C mV

8 8

1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N

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Peripheral operating requirements and behaviors 5. 6. 7. 8. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. ADC conversion clock < 3 MHz

Figure 7. Typical ENOB vs. ADC_CLK for 16-bit differential mode

Figure 8. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

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Peripheral operating requirements and behaviors

6.6.2 CMP and 6-bit DAC electrical specifications

Table 28. Comparator and 6-bit DAC electrical specifications
Symbol VDD IDDHS IDDLS VAIN VAIO VH Description Supply voltage Supply current, High-speed mode (EN=1, PMODE=1) Supply current, low-speed mode (EN=1, PMODE=0) Analog input voltage Analog input offset voltage Analog comparator hysteresis1 CR0[HYSTCTR] = 00 CR0[HYSTCTR] = 01 CR0[HYSTCTR] = 10 CR0[HYSTCTR] = 11 VCMPOh VCMPOl tDHS tDLS Output high Output low Propagation delay, high-speed mode (EN=1, PMODE=1) Propagation delay, low-speed mode (EN=1, PMODE=0) Analog comparator initialization delay2 IDAC6b INL DNL 6-bit DAC current adder (enabled) 6-bit DAC integral non-linearity 6-bit DAC differential non-linearity VDD 0.5 20 80 0.5 0.3 5 10 20 30 50 250 7 0.5 200 600 40 0.5 0.3 mV mV mV mV V V ns ns s A LSB3 LSB Min. 1.71 VSS 0.3 Typ. Max. 3.6 200 20 VDD 20 Unit V A A V mV

1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64

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Peripheral operating requirements and behaviors

0.08 0.07 0.06 0.05

CM P Hystereris (V)

HYSTCTR Setting
00 01
10

0.04 0.03 0.02 0.01 0

11

0.1

0.4

0.7

1.3

1.6

Vin level (V)

1.9

2.2

2.5

2.8

3.1

Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

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Peripheral operating requirements and behaviors

0.18 0.16 0.14 0.12

CMP P Hystereris (V)

HYSTCTR Setting
00 01 10 11

0.1 0 08 0.08 0.06 0.04 0.02 0

0.1

0.4

0.7

1.3

Vin level (V)

1.6

1.9

2.2

2.5

2.8

3.1

Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

6.6.3 12-bit DAC electrical characteristics

6.6.3.1
Symbol VDDA VDACR CL IL

12-bit DAC operating requirements

Desciption Supply voltage Reference voltage Output load capacitance Output load current

Table 29. 12-bit DAC operating requirements

Min. 1.71 1.13 Max. 3.6 3.6 100 1 Unit V V pF mA 1 2 Notes

1. The DAC reference can be selected to be VDDA or VREFH. 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC

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Peripheral operating requirements and behaviors

6.6.3.2
Symbol
P

12-bit DAC operating behaviors

Description Min. VDACR 100 60 1.2 0.05

Table 30. 12-bit DAC operating behaviors

Typ. 100 15 0.7 0.4 0.1 3.7 0.000421 1.7 0.12 90 250 kHz 550 40 Max. 250 900 200 30 1 100 VDACR 8 1 1 Unit A A s s s mV mV LSB LSB LSB %FSR %FSR dB V/C %FSR/C V/s 6 2 3 4 5 5 1 1 1 Notes

IDDA_DACL Supply current low-power mode IDDA_DACH Supply current high-speed mode
P

tDACLP tDACHP

Full-scale settling time (0x080 to 0xF7F) low-power mode Full-scale settling time (0x080 to 0xF7F) high-power mode

tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) low-power mode and high-speed mode Vdacoutl Vdacouth INL DNL DNL DAC output voltage range low high-speed mode, no load, DAC set to 0x000 DAC output voltage range high highspeed mode, no load, DAC set to 0xFFF Integral non-linearity error high speed mode Differential non-linearity error VDACR > 2 V Differential non-linearity error VDACR = VREF_OUT Gain error Power supply rejection ratio, VDDA 2.4 V Temperature coefficient offset voltage Temperature coefficient gain error Output resistance (load = 3 k) Slew rate -80h F7Fh 80h High power (SPHP) Low power (SPLP) BW 3dB bandwidth High power (SPHP) Low power (SPLP)

VOFFSET Offset error EG PSRR TCO TGE Rop SR

1. 2. 3. 4. 5. 6.

Settling within 1 LSB The INL is measured for 0 + 100 mV to VDACR 100 mV The DNL is measured for 0 + 100 mV to VDACR 100 mV The DNL is measured for 0 + 100 mV to VDACR 100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR 100 mV VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device

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Peripheral operating requirements and behaviors

Figure 11. Typical INL error vs. digital code

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Peripheral operating requirements and behaviors

Figure 12. Offset at half scale vs. temperature

6.7 Timers
See General switching specifications.

6.8 Communication interfaces

6.8.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices.
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Peripheral operating requirements and behaviors

All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 31. SPI master mode timing on slew rate disabled pads
Num. 1 2 3 4 5 6 7 8 9 10 11 Symbol fop tSPSCK tLead tLag tWSPSCK tSU tHI tv tHO tRI tFI tRO tFO Description Frequency of operation SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output 25 ns Min. fperiph/2048 2 x tperiph 1/2 1/2 tperiph - 30 18 0 0 Max. fperiph/2 2048 x tperiph 1024 x tperiph 15 tperiph - 25 Unit Hz ns tSPSCK tSPSCK ns ns ns ns ns ns Note 1 2

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). 2. tperiph = 1/fperiph

Table 32. SPI master mode timing on slew rate enabled pads
Num. 1 2 3 4 5 6 7 8 9 10 11 Symbol fop tSPSCK tLead tLag tWSPSCK tSU tHI tv tHO tRI tFI tRO tFO Description Frequency of operation SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output 36 ns Min. fperiph/2048 2 x tperiph 1/2 1/2 tperiph - 30 96 0 0 Max. fperiph/2 2048 x tperiph 1024 x tperiph 52 tperiph - 25 Unit Hz ns tSPSCK tSPSCK ns ns ns ns ns ns Note 1 2

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). 2. tperiph = 1/fperiph

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

40 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors SS1 (OUTPUT) 3

SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT)

2 5 5

10

11

10

11

6 MISO (INPUT)

7 MSB IN2 BIT 6 . . . 1 8 LSB IN 9 LSB OUT

MOSI (OUTPUT)

MSB OUT2

BIT 6 . . . 1

1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 13. SPI master mode timing (CPHA = 0)

SS1 (OUTPUT) 2
SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT)

10

11

10

11

6 MISO (INPUT)

7 MSB IN2 BIT 6 . . . 1

9

LSB IN

8 MOSI 2 (OUTPUT)PORT DATA MASTER MSB OUT

1.If configured as output

BIT 6 . . . 1

MASTER LSB OUT

PORT DATA

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 14. SPI master mode timing (CPHA = 1) Table 33. SPI slave mode timing on slew rate disabled pads
Num. 1 2 3 4 5 Symbol fop tSPSCK tLead tLag tWSPSCK Description Frequency of operation SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Min. 0 4 x tperiph 1 1 tperiph - 30 Max. fperiph/4 Unit Hz ns tperiph tperiph ns Note 1 2

Table continues on the next page...

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

Freescale Semiconductor, Inc. 41

Peripheral operating requirements and behaviors

Table 33. SPI slave mode timing on slew rate disabled pads (continued)
Num. 6 7 8 9 10 11 12 13 Symbol tSU tHI ta tdis tv tHO tRI tFI tRO tFO 1. 2. 3. 4. Description Data setup time (inputs) Data hold time (inputs) Slave access time Slave MISO disable time Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output 25 ns Min. 2.5 3.5 0 Max. tperiph tperiph 31 tperiph - 25 Unit ns ns ns ns ns ns ns Note 3 4

For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state

Table 34. SPI slave mode timing on slew rate enabled pads
Num. 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol fop tSPSCK tLead tLag tWSPSCK tSU tHI ta tdis tv tHO tRI tFI tRO tFO 1. 2. 3. 4. Description Frequency of operation SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Slave access time Slave MISO disable time Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output 36 ns Min. 0 4 x tperiph 1 1 tperiph - 30 2 7 0 Max. fperiph/4 tperiph tperiph 122 tperiph - 25 Unit Hz ns tperiph tperiph ns ns ns ns ns ns ns ns Note 1 2 3 4

For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

42 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

SS (INPUT) 2 12 13 4

SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT)

12

13 9

8 MISO (OUTPUT) see note 6 MOSI (INPUT) NOTE: Not defined SLAVE MSB 7 MSB IN

10 BIT 6 . . . 1

11

11 SEE NOTE

SLAVE LSB OUT

BIT 6 . . . 1

LSB IN

Figure 15. SPI slave mode timing (CPHA = 0)

SS (INPUT) 2
SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT)

4 12 13

12

13

10 MISO (OUTPUT) MOSI (INPUT) NOTE: Not defined see note 8 SLAVE 6 MSB IN MSB OUT 7

11 BIT 6 . . . 1 SLAVE LSB OUT

BIT 6 . . . 1

LSB IN

Figure 16. SPI slave mode timing (CPHA = 1)

6.8.2 Inter-Integrated Circuit Interface (I2C) timing

Table 35. I 2C timing
Characteristic SCL Clock Frequency Symbol fSCL Standard Mode Minimum 0 Maximum 100 0 Fast Mode Minimum Maximum 400 kHz Unit

Table continues on the next page...

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

Freescale Semiconductor, Inc. 43

Peripheral operating requirements and behaviors

Table 35. I 2C timing (continued)

Characteristic Hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time for I2C bus devices Data set-up time Rise time of SDA and SCL signals Fall time of SDA and SCL signals Set-up time for STOP condition Bus free time between STOP and START condition Pulse width of spikes that must be suppressed by the input filter Symbol tHD; STA Standard Mode Minimum 4 Maximum 0.6 Fast Mode Minimum Maximum s Unit

tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tr tf tSU; STO tBUF tSP

4.7 4 4.7 01 2504 4 4.7 N/A

3.452 1000 300 N/A

1.3 0.6 0.6 03 1002, 5 20 +0.1Cb 20 +0.1Cb 0.6 1.3 0

6 5

0.91 300 300 50

s s s s ns ns ns s s ns

1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 3. Input signal Slew = 10 ns and Output Load = 50 pF 4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. 6. Cb = total capacitance of the one bus line in pF.
SDA tSU; DAT tf

tf SCL

tLOW

tr

tHD; STA

tSP

tr

tBUF

tHD; STA

tHD; DAT

tHIGH

tSU; STA

SR

tSU; STO

Figure 17. Timing definition for fast and standard mode devices on the I2C bus

6.8.3 UART
See General switching specifications.
KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.
44 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

6.8.4 I2S/SAI switching specifications

This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input). All timing is given for noninverted serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures. 6.8.4.1 Normal Run, Wait and Stop mode performance over the full operating voltage range

This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes.
Table 36. I2S/SAI master mode timing
Num. Operating voltage S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 I2S_MCLK cycle time I2S_MCLK (as an input) pulse width high/low I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid I2S_TX_BCLK to I2S_TXD valid I2S_TX_BCLK to I2S_TXD invalid I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK Characteristic 1.71 40 45% 80 45% 0 0 26 0 Min. 3.6 55% 55% 15.5 19 Max. V ns MCLK period ns BCLK period ns ns ns ns ns ns Unit

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

Freescale Semiconductor, Inc. 45

Peripheral operating requirements and behaviors

S1 S2 S2

I2S_MCLK (output)
S3

I2S_TX_BCLK/ I2S_RX_BCLK (output)

S5

S4 S4 S6

I2S_TX_FS/ I2S_RX_FS (output)

S9 S10

I2S_TX_FS/ I2S_RX_FS (input)

S7 S8

S7 S8

I2S_TXD
S9 S10

I2S_RXD

Figure 18. I2S/SAI timing master modes Table 37. I2S/SAI slave mode timing
Num. Operating voltage S11 S12 S13 S14 S15 S16 S17 S18 S19 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid I2S_RXD setup before I2S_RX_BCLK I2S_RXD hold after I2S_RX_BCLK I2S_TX_FS input assertion to I2S_TXD output valid1 Characteristic 1.71 80 45% 10 2 0 10 2 Min. 3.6 55% 33 28 Max. V ns MCLK period ns ns ns ns ns ns ns Unit

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

46 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

S11 S12

I2S_TX_BCLK/ I2S_RX_BCLK (input)

S15

S12 S16

I2S_TX_FS/ I2S_RX_FS (output) I2S_TX_FS/ I2S_RX_FS (input)

S15

S13

S14

S19 S16

S15 S16

I2S_TXD
S17 S18

I2S_RXD

Figure 19. I2S/SAI timing slave modes

6.8.4.2

VLPR, VLPW, and VLPS mode performance over the full operating voltage range

This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes.
Table 38. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num. Operating voltage S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 I2S_MCLK cycle time I2S_MCLK pulse width high/low I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid I2S_TX_BCLK to I2S_TXD valid I2S_TX_BCLK to I2S_TXD invalid I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 Characteristic 1.71 62.5 45% 250 45% 0 Min. 3.6 55% 55% 45 45 Max. V ns MCLK period ns BCLK period ns ns ns ns ns ns Unit

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

Freescale Semiconductor, Inc. 47

Peripheral operating requirements and behaviors

S1 S2 S2

I2S_MCLK (output)
S3

I2S_TX_BCLK/ I2S_RX_BCLK (output)

S5

S4 S4 S6

I2S_TX_FS/ I2S_RX_FS (output)

S9 S10

I2S_TX_FS/ I2S_RX_FS (input)

S7 S8

S7 S8

I2S_TXD
S9 S10

I2S_RXD

Figure 20. I2S/SAI timing master modes Table 39. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num. Operating voltage S11 S12 S13 S14 S15 S16 S17 S18 S19 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid I2S_RXD setup before I2S_RX_BCLK I2S_RXD hold after I2S_RX_BCLK I2S_TX_FS input assertion to I2S_TXD output valid1 0 30 2 72 Characteristic 1.71 250 45% 30 Min. 3.6 55% Max. V ns MCLK period ns ns ns ns ns ns ns Unit

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

48 Freescale Semiconductor, Inc.

Dimensions
S11 S12

I2S_TX_BCLK/ I2S_RX_BCLK (input)

S15

S12 S16

I2S_TX_FS/ I2S_RX_FS (output) I2S_TX_FS/ I2S_RX_FS (input)

S15

S13

S14

S19 S16

S15 S16

I2S_TXD
S17 S18

I2S_RXD

Figure 21. I2S/SAI timing slave modes

6.9 Human-machine interfaces (HMI)

6.9.1 TSI electrical specifications
Table 40. TSI electrical specifications
Symbol TSI_RUNF TSI_RUNV TSI_EN TSI_DIS TSI_TEN TSI_CREF TSI_DVOLT Description Fixed power consumption in run mode Variable power consumption in run mode (depends on oscillator's current selection) Power consumption in enable mode Power consumption in disable mode TSI analog enable time TSI reference capacitor Voltage variation of VP & VM around nominal values Min. 1.0 0.19 Typ. 100 100 1.2 66 1.0 Max. 128 1.03 Unit A A A A s pF V

7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

Freescale Semiconductor, Inc. 49

Pinout

To find a package drawing, go to freescale.com and perform a keyword search for the drawings document number:
If you want the drawing for this package 32-pin QFN 48-pin QFN 64-pin LQFP Then use this document number 98ASA00473D 98ASA00466D 98ASS23234W

8 Pinout
8.1 KL16 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin.
64 LQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 QFN 1 2 3 4 5 6 7 8 9 10 11 12 32 QFN 1 2 3 4 5 6 7 8 Pin Name PTE0 PTE1 VDD VSS PTE16 PTE17 PTE18 PTE19 PTE20 PTE21 PTE22 PTE23 VDDA VREFH VREFL VSSA Default DISABLED DISABLED VDD VSS ADC0_DP1/ ADC0_SE1 ADC0_DM1/ ADC0_SE5a ADC0_DP2/ ADC0_SE2 ADC0_DM2/ ADC0_SE6a ADC0_DP0/ ADC0_SE0 ADC0_DM0/ ADC0_SE4a ADC0_DP3/ ADC0_SE3 ADC0_DM3/ ADC0_SE7a VDDA VREFH VREFL VSSA VDD VSS ADC0_DP1/ ADC0_SE1 ADC0_DM1/ ADC0_SE5a ADC0_DP2/ ADC0_SE2 ADC0_DM2/ ADC0_SE6a ADC0_DP0/ ADC0_SE0 ADC0_DM0/ ADC0_SE4a ADC0_DP3/ ADC0_SE3 ADC0_DM3/ ADC0_SE7a VDDA VREFH VREFL VSSA PTE16 PTE17 PTE18 PTE19 PTE20 PTE21 PTE22 PTE23 SPI0_PCS0 SPI0_SCK SPI0_MOSI SPI0_MISO TPM1_CH0 TPM1_CH1 TPM2_CH0 TPM2_CH1 UART2_TX UART2_RX TPM_CLKIN0 TPM_CLKIN1 I2C0_SDA I2C0_SCL UART0_TX UART0_RX UART2_TX UART2_RX SPI0_MISO SPI0_MOSI LPTMR0_ALT3 ALT0 ALT1 PTE0 PTE1 ALT2 SPI1_MISO SPI1_MOSI ALT3 UART1_TX UART1_RX ALT4 RTC_CLKOUT ALT5 CMP0_OUT SPI1_MISO ALT6 I2C1_SDA I2C1_SCL ALT7

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

50 Freescale Semiconductor, Inc.

Pinout 64 LQFP 17 18 48 QFN 13 14 32 QFN 9 Pin Name PTE29 PTE30 Default CMP0_IN5/ ADC0_SE4b DAC0_OUT/ ADC0_SE23/ CMP0_IN4 DISABLED DISABLED DISABLED SWD_CLK DISABLED DISABLED SWD_DIO NMI_b DISABLED DISABLED DISABLED VDD VSS EXTAL0 XTAL0 RESET_b ADC0_SE8/ TSI0_CH0 ADC0_SE9/ TSI0_CH6 ADC0_SE12/ TSI0_CH7 ADC0_SE13/ TSI0_CH8 TSI0_CH9 TSI0_CH10 TSI0_CH11 TSI0_CH12 ADC0_SE14/ TSI0_CH13 ADC0_SE15/ TSI0_CH14 ADC0_SE11/ TSI0_CH15 DISABLED VSS VDD VSS VDD ADC0_SE8/ TSI0_CH0 ADC0_SE9/ TSI0_CH6 ADC0_SE12/ TSI0_CH7 ADC0_SE13/ TSI0_CH8 TSI0_CH9 TSI0_CH10 TSI0_CH11 TSI0_CH12 ADC0_SE14/ TSI0_CH13 ADC0_SE15/ TSI0_CH14 ADC0_SE11/ TSI0_CH15 VDD VSS EXTAL0 XTAL0 PTA18 PTA19 PTA20 PTB0/ LLWU_P5 PTB1 PTB2 PTB3 PTB16 PTB17 PTB18 PTB19 PTC0 PTC1/ LLWU_P6/ RTC_CLKIN PTC2 PTC3/ LLWU_P7 I2C1_SCL I2C0_SCL I2C0_SDA I2C0_SCL I2C0_SDA SPI1_MOSI SPI1_MISO TPM1_CH0 TPM1_CH1 TPM2_CH0 TPM2_CH1 UART0_RX UART0_TX TPM2_CH0 TPM2_CH1 EXTRG_IN TPM0_CH0 TPM_CLKIN0 TPM_CLKIN1 I2S0_TX_BCLK I2S0_TX_FS CMP0_OUT I2S0_TXD0 I2S0_TXD0 SPI1_MISO SPI1_MOSI UART1_RX UART1_TX TPM_CLKIN0 TPM_CLKIN1 LPTMR0_ALT1 RESET_b TSI0_CH1 TSI0_CH2 TSI0_CH3 TSI0_CH4 TSI0_CH5 ALT0 CMP0_IN5/ ADC0_SE4b DAC0_OUT/ ADC0_SE23/ CMP0_IN4 ALT1 PTE29 PTE30 ALT2 ALT3 TPM0_CH2 TPM0_CH3 ALT4 TPM_CLKIN0 TPM_CLKIN1 ALT5 ALT6 ALT7

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

10 11 12 13 14 15 16 17 18 19 20 21 22

PTE31 PTE24 PTE25 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTA12 PTA13 VDD VSS PTA18 PTA19 PTA20 PTB0/ LLWU_P5 PTB1 PTB2 PTB3 PTB16 PTB17 PTB18 PTB19 PTC0 PTC1/ LLWU_P6/ RTC_CLKIN PTC2 PTC3/ LLWU_P7 VSS VDD

PTE31 PTE24 PTE25 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTA12 PTA13 UART0_RX UART0_TX I2C1_SCL I2C1_SDA

TPM0_CH4 TPM0_CH0 TPM0_CH1 TPM0_CH5 TPM2_CH0 TPM2_CH1 TPM0_CH0 TPM0_CH1 TPM0_CH2 TPM1_CH0 TPM1_CH1 I2S0_TX_BCLK I2S0_TXD0 I2S0_TX_FS SWD_DIO NMI_b I2C0_SCL I2C0_SDA SWD_CLK

45 46 47 48

35 36

23 24

I2C1_SDA UART1_RX

TPM0_CH1 TPM0_CH2 CLKOUT

I2S0_TX_FS I2S0_TX_BCLK

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

Freescale Semiconductor, Inc. 51

Pinout 64 LQFP 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 QFN 37 38 39 40 41 42 43 44 45 46 47 48 32 QFN 25 26 27 28 29 30 31 32 Pin Name PTC4/ LLWU_P8 PTC5/ LLWU_P9 PTC6/ LLWU_P10 PTC7 PTC8 PTC9 PTC10 PTC11 PTD0 PTD1 PTD2 PTD3 PTD4/ LLWU_P14 PTD5 PTD6/ LLWU_P15 PTD7 Default DISABLED DISABLED CMP0_IN0 CMP0_IN1 CMP0_IN2 CMP0_IN3 DISABLED DISABLED DISABLED ADC0_SE5b DISABLED DISABLED DISABLED ADC0_SE6b ADC0_SE7b DISABLED ADC0_SE6b ADC0_SE7b ADC0_SE5b CMP0_IN0 CMP0_IN1 CMP0_IN2 CMP0_IN3 ALT0 ALT1 PTC4/ LLWU_P8 PTC5/ LLWU_P9 PTC6/ LLWU_P10 PTC7 PTC8 PTC9 PTC10 PTC11 PTD0 PTD1 PTD2 PTD3 PTD4/ LLWU_P14 PTD5 PTD6/ LLWU_P15 PTD7 ALT2 SPI0_PCS0 SPI0_SCK SPI0_MOSI SPI0_MISO I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA SPI0_PCS0 SPI0_SCK SPI0_MOSI SPI0_MISO SPI1_PCS0 SPI1_SCK SPI1_MOSI SPI1_MISO UART2_RX UART2_TX UART2_RX UART2_TX UART0_RX UART0_TX TPM0_CH4 TPM0_CH5 ALT3 UART1_TX ALT4 TPM0_CH3 ALT5 I2S0_MCLK CMP0_OUT I2S0_MCLK ALT6 ALT7

LPTMR0_ALT2 I2S0_RXD0 EXTRG_IN I2S0_RX_BCLK SPI0_MISO I2S0_RX_FS I2S0_MCLK I2S0_RX_BCLK I2S0_RX_FS I2S0_RXD0 TPM0_CH0 TPM0_CH1 TPM0_CH2 TPM0_CH3 TPM0_CH4 TPM0_CH5 SPI1_MISO SPI1_MOSI SPI0_MISO SPI0_MOSI SPI0_MOSI

8.2 KL16 pinouts

The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see KL16 Signal Multiplexing and Pin Assignments.

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

52 Freescale Semiconductor, Inc.

Pinout
PTD6/LLWU_P15 PTD4/LLWU_P14 PTC6/LLWU_P10 PTC5/LLWU_P9 50 PTC4/LLWU_P8 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 22 25 26 23 24 27 28 29 31 30 32

PTC11

PTC10

PTD5

PTD3

PTD2

PTD1

PTD0

PTC9

PTD7

PTC8

PTC7 52

62

61

59

58

64

60

57

56

55

54

PTE0 PTE1 VDD VSS PTE16 PTE17 PTE18 PTE19 PTE20 PTE21 PTE22 PTE23 VDDA VREFH VREFL VSSA

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

63

53

51

VDD VSS PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTC0 PTB19 PTB18 PTB17 PTB16 PTB3 PTB2 PTB1 PTB0/LLWU_P5 PTA20 PTA19

PTE30

PTE31

PTE29

PTE24

PTE25

PTA0

PTA3

PTA12

PTA13

PTA4

VSS

Figure 22. KL16 64-pin LQFP pinout diagram

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

Freescale Semiconductor, Inc. 53

PTA18

PTA1

PTA2

PTA5

VDD

Pinout

PTD6/LLWU_P15

PTD4/LLWU_P14

PTC6/LLWU_P10

PTC5/LLWU_P9
38

48

46

45

47

44

43

42

41

40

39

37

PTC4/LLWU_P8

PTD7

PTD5

PTD3

PTD2

PTD1

PTD0

PTC7

VDD VSS PTE16 PTE17 PTE18 PTE19 PTE20 PTE21 VDDA VREFH VREFL VSSA

1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 13 14 15 16 17 18 19 20 24

36 35 34 33 32 31 30 29 28 27 26 25

PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTC0 PTB17 PTB16 PTB3 PTB2 PTB1 PTB0/LLWU_P5 PTA20 PTA19

PTE24

PTE25

PTA1

PTA2

PTE29

PTE30

PTA0

PTA3

PTA4

VDD

Figure 23. KL16 48-pin QFN pinout diagram

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

54 Freescale Semiconductor, Inc.

PTA18

VSS

Pinout

PTD6/LLWU_P15

PTD4/LLWU_P14

PTC6/LLWU_P10

PTC5/LLWU_P9
26

32

31

29

30

28

27

25

PTC4/LLWU_P8

PTD7

PTD5

PTC7

PTE0 PTE1 PTE16 PTE17 PTE18 PTE19 VDDA VSSA

1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9

24 23 22 21 20 19 18 17

PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTB1 PTB0/LLWU_P5 PTA20 PTA19 PTA18

PTA1

PTA2

PTE30

VDD

PTA0

PTA3

Figure 24. KL16 32-pin QFN pinout diagram

KL16 Sub-Family Data Sheet Data Sheet, Rev. 2, 10/2013.

Freescale Semiconductor, Inc. 55

PTA4

VSS

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Document Number: KL16P64M48SF5 Rev. 2 10/2013