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NXP S32K39 S32K37

The document provides technical data for the S32K396, S32K394, S32K376, S32K374, S32K366, and S32K364 microcontroller series, detailing electrical specifications, features, and functional characteristics. It highlights the advanced capabilities of the S32K396 series, including multiple Cortex-M7 cores, motor control coprocessors, and extensive safety features designed for automotive applications. Additionally, it outlines the product's architecture, memory specifications, and various communication interfaces.

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0% found this document useful (0 votes)

36 views120 pages

NXP S32K39 S32K37

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S32K39, S32K37 and S32K36 Data Sheet

Supports S32K396, S32K394, S32K376, S32K374, S32K366 and S32K364.

Rev. 4 — 06/2024 Data Sheet: Technical Data

This document provides electrical specifications for S32K396, S32K394, S32K376, S32K374, S32K366 and S32K364 .
For functional characteristics and the programming model, see S32K39, S32K37 and S32K36 Reference Manual.

NXP reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products.
Contents

1 S32K396 product series..................................... 4 12.1 Flash memory program and erase

2 Block diagrams...................................................4 specifications................................................ 49
3 Features............................................................. 5 12.2 Flash memory Array Integrity and Margin Read
3.1 Feature comparison........................................ 5 specifications................................................ 50
3.2 Feature summary............................................ 8 12.3 Flash memory module life specifications...... 51
4 Ordering information.........................................13 12.3.1 Data retention vs program/erase cycles....... 51
5 General.............................................................13 12.4 Flash memory AC timing specifications........ 52
5.1 Absolute maximum ratings............................13 12.5 Flash memory read timing parameters......... 52
5.2 Voltage and current operating requirements.15 13 Analog modules................................................53
5.2.1 Supported voltage supply use-cases............ 17 13.1 SAR_ADC..................................................... 53
5.3 Thermal operating characteristics................. 18 13.2 Sigma Delta Analog to Digital Converter...... 55
5.4 ESD and Latch-up Protection Characteristics 13.3 Low Power Comparator (LPCMP)................ 74
...................................................................... 18 13.4 Sine wave generator..................................... 78
6 Power management......................................... 18 13.5 Supply Diagnosis.......................................... 79
6.1 Supply Monitoring......................................... 18 13.6 Temperature Sensor..................................... 79
6.2 Recommended Decoupling Capacitors........ 20 14 Clocking modules............................................. 80
6.3 V15 regulator (SMPS option) electrical 14.1 Fast External Oscillator (FXOSC)................. 80
specifications................................................ 24 14.2 FIRC..............................................................82
6.4 V11 regulator (NMOS ballast transistor control) 14.3 SIRC............................................................. 83
electrical specifications................................. 25 14.4 PLL................................................................83
6.5 Supply currents............................................. 26 15 Communication interfaces................................84
6.6 Operating mode............................................ 29 15.1 LPSPI............................................................84
6.7 Cyclic wake-up current .................................31 15.1.1 LPSPI............................................................84
7 I/O parameters................................................. 31 15.1.2 LPSPI0 20 MHz and 15 MHz Combinations. 89
7.1 GPIO DC electrical specifications, 3.3V Range 15.1.3 LPSPI Pad Type........................................... 89
(2.97V - 3.63V)..............................................31 15.2 MDIO timing specifications........................... 91
7.2 GPIO DC electrical specifications, 5.0V (4.5V - 15.3 Ethernet MII (10/100 Mbps).......................... 92
5.5V)............................................................. 35 15.4 Ethernet MII (200 Mbps)............................... 94
7.3 3.3V (2.97V - 3.63V) GPIO Output AC 15.5 Ethernet RMII (10/100 Mbps)........................96
Specification..................................................39 15.6 I2C................................................................ 97
7.4 5.0V (4.5V - 5.5V) GPIO Output AC 15.7 FlexCAN characteristics................................97
Specification..................................................41 15.8 LPUART characteristics................................ 98
8 Real-time control.............................................. 43 15.9 SPI................................................................ 98
8.1 eTPU timing.................................................. 43 15.10 Microsecond channel (MSC).......................100
8.2 eTPU skew characteristics............................44 15.11 Zipwire........................................................ 101
8.3 eMIOS...........................................................44 15.12 LFAST PLL................................................. 101
8.4 LCU...............................................................45 16 Memory interfaces..........................................102
8.5 LCU skew characteristics..............................45 16.1 QuadSPI Octal 3.3V DDR 120MHz............ 102
9 Glitch Filter....................................................... 46 16.2 QuadSPI Quad 3.3V SDR 120MHz............ 103
10 LVDS specifications......................................... 46 16.3 QuadSPI configurations.............................. 104
10.1 LVDS 3.3V Receiver Electrical Specifications 17 Debug modules.............................................. 106
...................................................................... 46 17.1 Debug trace timing specifications............... 106
10.2 LVDS 3.3V Transmitter Electrical 17.2 JTAG electrical specifications..................... 106
Specifications................................................47 17.3 SWD electrical specifications...................... 109
10.3 LVDS 5V Transmitter Electrical Specifications 18 Thermal Attributes.......................................... 110
...................................................................... 48 18.1 Description.................................................. 110
11 eFlexPWM........................................................48 18.2 Thermal Characteristics.............................. 110
11.1 eFlexPWM skew characteristics................... 49 19 Dimensions.....................................................111
12 Flash memory specification.............................. 49 19.1 Obtaining package dimensions...................111
20 Revision history.............................................. 112
Chapter Legal information............................................118
NXP Semiconductors
S32K396 product series

1 S32K396 product series

The S32K396 product series further extends the highly scalable portfolio of Arm® Cortex®-M7 K3xx MCUs in the automotive
industry. It features:
• The Cortex-M7 core at a higher frequency.
• Advanced motor control coprocessors.
• An extended analog, including a high-resolution PWM.
S32K396 is developed to meet the next generation SiC traction inverter requirements and to enable high efficiency, low latency,
and system-level BOM cost savings. Because of its versatile architecture, S32K396 is also well suited to address a wide range
of xEV applications.
The S32K39x MCUs extend the high-performance capabilities of S32K37x with two programmable motor control coprocessors.
Additionally, S32K36x MCUs are optimized solution targeted at single traction motor control application. The last digit denotes the
size of Flash memory size. See the Feature comparison for a detailed overview of the differences between variants. When the
S32K396 is referenced in the RM it means the conditions, configurations or features are valid for all the variants of the device.
S32K396 can also be used in combination with powerful 16 nm NXP MCUs or MPUs (S32Z2 and S3E2), in these ways:
• As a companion die: connected locally (same ECU) to S32Z2 and S3E2 through the Zipwire interface to extend 5V I/O and
analog capabilities
• As a smart actuator: connected remotely via Ethernet or FlexCAN

2 Block diagrams

Arm

Figure 1. S32K39x (x=4 or 6)

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 4 / 120
NXP Semiconductors
Features

Figure 2. S32K37x (x=4 or 6)

S32K36

Memory External Memory IF CPU Platform DSP Security and Isolation

704 KB SRAM with ECC Permanent Lock HSE-B
(including 64 KB Standby SRAM and TCMs)
Cortex-M7 Asymmetric Hardware Accelerators
128 KB Data Flash Memory w/ECC CoolFlux
1x Quad SPI Cortex-M7
16 KB I-cache 16 KB D-cache Cortex-M7 Symmetric Hardware Accelerators
DSP 16L
4/6 MB Program Flash Memory w/ECC (1Core/2Thread)
16 KB I-cache 16 KB
TDM:32K-L D-cache
64 K-D 16 KB I-cache 16 KB D-cache 64 KB Secure SRAM
8-bit, 120 MHz DTR TCM: 32K-I, 64K-D
DP-FPU, DSP TCM: 32K-I, 64K-D 32 KB Code RAM
System Security FW
XRDC
DP-FPU, DSP DP-FPU, DSP 24 KB Data RAM Upgrade
PMC Access Control
Management

1x Lock-Step DMA 32 ch + 1x DMA 32 ch

Debug and Trace Unit and Calibration

XBAR
FXOSC (8-40 MHz)

FIRC (48 MHz)/SIRC (32 kHz)

Networking Timers and Analog Serial Communication
2x PLL
1x Ethernet, 100 Mbps 2x Adv. MotorControlCo-Processors 2x eFlexPWM/Nanoedge (8 ch each) 8 ch FlexIO
AVB/TSN + 2x 16 ch Programmable I/O timers Emulating:
Functional Safety
UART, I2C, SPI
FCCU MPU 1x eMIOS (16 ch)
2x SD ADC with CoolFlux DSP I2S, SENT, PWM
6x FlexCAN (FD)
MBIST/LBIST CMU
1x ZipWire 4x SAR ADC 1 Msps 2x TRGMUX/2x LCU/1x BCTU
6x LPSPI
STCU CRC

SWT EIM/ERM 4x LPUART (LIN) 1x SWG 1x ACMP 1x MSC forTimer Serialization 2x I2C

Specifications: Key features:

Cores and Accelerators: Motor Control: 1x 3-phase with resolver
3x Arm Cortex-M7 cores at 320 MHz (1xLockstep core pair + 1 core) Functional Safety: Developed as per ISO 26262 with target ASIL D
1x DSP at 160 MHz SW Enablement: MCAL, Security FW and production quality level drivers
External Memory I/F: Security: HSE with AES, RSA, ECC, and Hash acceleration
x4 SDR SerialFlash up to 120 MHz or x4 DDR SerialFlash up to 80 MHz Connectivity: 10/100 Ethernet, FlexCAN (with FD) and ZipWire, QSPI
x8 DDR OctalFlash, Hyper Flash and HyperRAM up to 120 MHz Calibration: supported by dedicated HW and memory interface
TempRange (Ta): -40 to 125 °C
Power Supply: External PMIC
Packaging: 176LQFP-EP/289MAPBGA

Figure 3. S32K36x (x=4 or 6)

3 Features

3.1 Feature comparison

The following table compares some of the prominent features of the S32K396 product series.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 5 / 120
NXP Semiconductors
Features

Table 1. Feature comparison

Feature S32K396 S32K394 S32K376 S32K374 S32K366 S32K364

Safety/ASIL ASIL D

Number of CPU Three Arm® Cortex®-M7 cores Two Arm® Cortex®-M7 cores
cores

Core One lockstep core pair and Two split-lock configurable cores One lockstep core pair and One
configurations Cortex-M7_0 core

Core frequency 320

(MHz)

Program flash 6 4 6 4 6 4
memory (MB)

Data flash 128

memory (KB)

Total RAM (KB) 800 (including 64 KB standby RAM and 288 KB TCM) 704 (including 64 KB standby RAM
and 192 KB TCM)

Standby RAM 64
(KB)

Security HSE_B

DMA 2 x 32-channel eDMA (1 eDMA implemented as a lock-step pair)

Maximum 2218-3101-6509 1478-2067-4339

performance
(DMIPS)1 1 core in lockstep (ASIL D) and 2 cores in split-lock (ASIL B) 1 core in lockstep (ASIL D) and 1
core (ASIL B)

ASIL D 1478-2067-4339 739-1034-2170

(DMIPS)1

Advanced motor 2 x eTPU engines at a frequency of N/A 2 x eTPU engines at a frequency of

control 320 MHz (32 channels each) with 320 MHz (16 channels each) with
coprocessor an input glitch filter an input glitch filter
configuration

DSP 160 (4 threads) 160 (2 threads)

(CoolFlux)
[MHz]

eFlexPWM 2 x eFlexPWM with NanoEdge (8 channels each)

configuration

FlexCAN 6
instances

EMAC 1 x 10/100 Mbit/s

configuration

LPUART (LIN) 4
instances

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 6 / 120
NXP Semiconductors
Features

Table 1. Feature comparison (continued)

Feature S32K396 S32K394 S32K376 S32K374 S32K366 S32K364

Zipwire 1
instances2

QuadSPI 1
instances

LPSPI instances 63

I2C instances 2

FlexIO 8 channels, 32 pins

configuration
Emulating UART, I2C, SPI, I2S, single edge nibble transmission (SENT), PWM, and camera interface

MSC instances4 1

SAR_ADC 1- 7 4
Msps instances

SDADC 4 2
instances

SGEN instances 2 1

LPCMP 2 1
instances

PIT instances 3

SWT instances 3

STM instances 3

LCU instances 2

BCTU instances 2 1

TRGMUX 2
instances

eMIOS 1 (24 channels) 1 (16 channels)

instances

RTC instances 1

289-ball Yes
MAPBGA
included?

176 LQFP-EP Yes

included?

1. The first result abides by all of the "ground rules" out in Dhrystone documentation, the second permits inlining of functions,
not just permitted C strings libraries, while the third additionally permits simultaneous ("multi-file") compilation. All are with the
original (K and R) v2.1 of Dhrystone. Arm Compiler 6.17. See https://developer.arm.com/Processors/Cortex-M7 for details.
2. This feature is available for 289 MAPBGA.
3. You can increase the number of channels by using FlexIO emulation.
4. LVDS and single-ended in 289 MAPBGA; single-ended only in 176 LQFP-EP.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 7 / 120
NXP Semiconductors
Features

3.2 Feature summary

The following table provides a list of Cortex-M7 core features that the S32K396 product family supports.

Table 2. Feature summary

Feature Inclusions

Core and architecture • Cortex-M7 core running up to 320 MHz

• Arm core based on the Armv7 architecture and ThumbR-2 ISA
• 16 KB D-cache and 16 KB I-cache for optimizing wait state execution
from memories
• 96 KB TCM associated with each core
• On-core MPU for dynamic task protection (16 regions)
• IEEE 754-compliant SPFPU
• Harvard bus architecture implementing dedicated instruction and data
path
• 6-stage pipeline with branch speculation
• XRDC integrated with a crossbar switch to provide memory and
peripheral protection
• DSP and SIMD extension
• I/O protection (VIRT_WRAPPER)
• embedded trace macrocell (ETM) supporting instruction trace
• Arm third-party ecosystem support: software and tools to help
minimize development time and cost

DSP and coprocessors • CoolFlux DSP16L with:

— A frequency of 160 MHz
— One core and four threads
— 32 KB Instruction RAM and 24 KB Data RAM
• Two coprocessor cores at a frequency of 320 MHz each that help
with:
— Software running independently of the Cortex-M7 CPUs
— 32 KB code RAM and 8 KB data RAM
— DSP and mathematical capabilities
• Extra safety features such as ECC, watchdog, latency monitor, and
idle counter

DMA • 2 x 64-channel DMAMUX per eDMA

• 2 x 32-channel eDMAs (1 eDMA implemented as a lock-step pair)
• Complex data transfers performed with minimal intervention from a
host processor
• Programmable support for scatter-gather DMA processing

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 8 / 120
NXP Semiconductors
Features

Table 2. Feature summary (continued)

Feature Inclusions

System and power management • Support for simplified power modes (Run and Standby)
• Support for clock gating of unused modules; specific peripherals
continue to work in low-power modes
• Support for an external ballast transistor to generate core supply
• Fully independent CPU and peripheral clocking scheme
• Rapid start-up from a 48 MHz FIRC
• Low-power oscillator such as the 32 kHz SIRC
• PMC with LVD and selectable trip points
• Support for multiple power modes
• NMI

Memory and memory interfaces • Up to 6 MB program flash memory with an ECC

• Up to 128 KB data flash memory with an ECC
• Up to 800 KB SRAM with an ECC
• 8-bit QuadSPI
• 120 MHz DTR

Clocks • External 8–40 MHz crystal oscillator or resonator

• Internal clock references:
— 48 MHz FIRC ± 5%
— 32 kHz SIRC ± 10%
• Up to 640 MHz PLL for divided system clock operation

Security and integrity • HSE_B: Upgradable firmware that NXP delivers and you can program
• Security ciphers:
— Symmetric: AES with 128, 192, or 256 bits
— Cipher modes: ECB, CBC, cipher-based message authentication
code (CMAC), GMAC, Counter-Based Block Cipher mode
(CTR), Output-Feedback-Based Block Cipher mode (OFB),
counter with cipher block chaining message authentication code
(CCM), and Galois/Counter mode (GCM)
— Asymmetric: RSA (up to 4096 bytes) and ECC (up to 521 bytes)
— Hash: Miyaguchi-Preneel, SHA-2/SHA-3 (up to 512 bytes)
— Number of keys that the HSE_B firmware configures and
controls
— Random number generator
• Security use cases supported:

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 9 / 120
NXP Semiconductors
Features

Table 2. Feature summary (continued)

Feature Inclusions

— OTA update
— Secure boot
— Secure communication
— Component protection
— Secure storage
— Key exchange

Safety ISO26262 • Classification up to ASIL D

• ERM and EIM support
• Watchdog timers with an independent clock source
• Voltage monitors
• Bandgap voltage available as ADC input
• External clock source monitoring using an independent reference
• PLL lock and loss-of-lock protection
• XRDC
• Access control, memory protection, and peripheral isolation
• ECC on code flash memory, data flash memory, and system RAM
• ADC self-test feature
• Internal analog monitoring of all supplies available
• CRC generation module
• FCCU failure output

Analog • 12-bit ADC:

— Up to 69 external analog inputs
— 1 μs conversion time
— Internal bandgap voltage reference channel, supporting
automatic compare and an optional hardware trigger
— Up to five internal reference inputs
— Automatic compare with interrupt
— Self-test and self-calibration scheme
• SDADC:
— Integrated digital filtering (CoolFlux DSP)
• SGEN (Sine Wave Generator)
— Input clock frequency range: 12 MHz–20 MHz
— Output sinusoidal signal frequency range: 1 kHz–50 kHz

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 10 / 120
NXP Semiconductors
Features

Table 2. Feature summary (continued)

Feature Inclusions

• LPCMP with an internal 8-bit DAC as a reference:

— LPCMP with both positive and negative inputs, with separately
selectable interrupts on rising and falling comparator outputs
— Ability to cross-trigger the timers from both the ADC and LPCMP
outputs
• Temperature sensor (TempSense) with an output that ADC measures

I/O timers • eFlexPWM with NanoEdge (high-resolution PWM):

— 16 bits (+5 with NanoEdge) of resolution for center-aligned, edge-
aligned, and asymmetrical PWMs
— Support for double switching PWM outputs
— Fault inputs that can be assigned to control multiple PWM
outputs
— Independent top and bottom hardware deadtime insertion
— Multiple output trigger events that can be generated per PWM
cycle via hardware
• 24-bit eMIOS timer, offering up to 24 standard channels:
— Input Capture, Output Compare, and PWM modes
— Fault input support with global fault control
— Multiple features such as deadtime insertion, configurable
polarity, quadrature decoding, and so on
• Motor control and power conversion using a combination of eTPU,
eFlexPWM, eMIOS, LCU, BCTU, and SWG
• 3 x STMs, with four channels each
• 32-bit RTC
• 3 x 32-bit PITs, with four channels for raising interrupts and triggering
DMA channels

Communications • LPSPI supporting DMA with full-duplex or single-wire bidirectional

communication in Master or Slave mode
• LPI2C modules with:
— DMA support
— Low-power availability
— Master or slave support
— System management bus
• FlexIO, with an option to configure as different communication
peripherals, offering support for SENT
• LPUART with DMA support, having:

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 11 / 120
NXP Semiconductors
Features

Table 2. Feature summary (continued)

Feature Inclusions

— An optional 13-bit break

— Full-duplex NRZ
— LIN 2.1 extension support
— Low-power availability
• FlexCAN modules with ISOCAN-FD and DMA support
• EMAC complex (10/100 Ethernet) that supports 1588 timers, MII/RMII
interface, and AVB and TSN support
• Microsecond channel (MSC)
• Zipwire (high-speed SIPI and LFAST)

Debug • Debug watchpoint and trace (DWT), with four configurable

comparators as hardware watch points
• SWO-synchronous trace data support
• Instrumentation trace macrocell (ITM) with software and hardware
trace plus timestamping
• FPB with an ability to patch code and data from code space to system
space
• All execution units and bus masters made traceable through TPIU
over GPIO pins; a very-low-bandwidth trace option also available via
the SWO
• embedded trace FIFO (ETF): a dedicated trace buffer available for
each of the core masters, allowing data to be captured internally
before being optionally routed to external trace pins
• Serial wire viewer (SWV): trace capability providing displays of:
— Reads
— Writes
— Exceptions
— PC samples
— Print

I/O and package • Up to 237 GPIO pins

• Up to 144 GPIO pins with interrupt functionality
• Up to 77 GPIO pins with wakeup capability
• Pseudo open-drain support on LPUART, FlexIO, and LPI2C
• Package options of 289 MAPBGA and 176 LQFP-EP

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 12 / 120
NXP Semiconductors
Ordering information

4 Ordering information
P/S 1 Product status 1th character 8th character 13th and 14th character
Product status for ordering and marking Extra feature Package suffix
P for prototype and
32 2-3 Product type/brand S for qualified ordering P/N No 100 Mbps pins BGA LQPF
ethernet ethernet
MAC MAC 176 KU
K 4 Product line 2nd and 3rd character
Product type/brand 289 JB -
N E
32 for automotive 32 bit MCU/MPU
3 5 Series/family
Ordering part number (always 16 characters)

4th character 9th character

9 6 Core platform Product line Security
K = General purpose MCU
6 7 Memory size HSE B

5th character H 15th character

Series/family Software configuration
E 8 Features
3 = K3 product family/arm cortex M7 based S = Standard family SW package, including:
• Real time driver including Autosar MCAL
H 9 Security and Non Autosar driver package (ISO26262
6th character compliant, crypto driver included)
Core platform • Standard security firmware
T0 10-11 Fab and mask rev letter 6 = 1x M7 LS core + 1x M7 core + DSP + dual eTPU
7 = 1x M7 LS core + 2x M7 split-lock cores + DSP 10th and 11 th character
9 = 1x M7 LS core + 2x M7 split-lock cores + DSP + dual eTPU Fab and mask rev
M 12 Temperature suffix Tx = Global foundry

7th character x0 = 1th fab revision

JB 13-14 Package suffix Memory size x1 = 2nd fab revision

4 6
S 15 Software 12th character 16th character
configuration P-flash 4 MB 6M Ambient temperature (Ta) Tape and reel
V = -40 °C to 105 °C T = Trays/tubes
T 16 Tape and reel M = -40 °C to 125 °C R = Tape and reel
indicator

Figure 4. Ordering information

5 General

5.1 Absolute maximum ratings

CAUTION
When the MCU is in an unpowered state, current injected through the chip pins may bias internal chip structures
(for example, ESD diodes) and incorrectly power up these internal structures through inadvertent paths. The
presence of such residual voltage may influence different chip-internal blocks in an unpredictable manner and
may ultimately result in unpredictable chip behavior (for example, POR flag not set). Once in the illegal state,
powering up the chip further and then applying reset will clear the illegal state. Injection current specified for the
chip under the aspect of absolute maximum ratings represent the capability of the internal circuitry to withstand
such condition without causing physical damage. Functional operation of the chip under conditions - specified
as absolute maximum ratings - is not implied.

NOTE
Functional operating conditions appear in the DC electrical characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maximum values is not guaranteed. See footnotes in the following table
for specific conditions. Stress beyond the listed maximum values may affect device reliability or cause permanent
damage to the device. All the limits defined in the datasheet specification must be honored together and any
violation to any one or more will not guarantee desired operation. Unless otherwise specified, all maximum and
minimum values in the datasheet are across process, voltage, and temperature.

Table 3. Absolute maximum ratings

Symbol Description Min Typ Max Unit Condition Spec

Number

VDD_HV_A Main I/O and -0.3 — 6.0 V — —

analog supply
voltage 1,2

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 13 / 120
NXP Semiconductors
General

Table 3. Absolute maximum ratings (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

VDD_HV_B Secondary I/O -0.3 — 6.0 V — —

supply voltage 1,2

VDD_DCDC Supply voltage for -0.3 — 6.0 V — —

the SMPS gate
driver 1,2,3

V15 Voltage sensing -0.3 — 2.75 V — —

input 1,2

V25 Flash memory -0.3 — 2.9 V — —

supply (2.5 V),
internally regulated 1

V11 High-current core -0.3 — 1.26 V — —

logic supply input 1

VDDA_SWG Supply voltage for -0.3 — 6.0 V — —

SWG 1,2

VDD_LVDS Supply voltage for -0.3 — 3.96 V — —

LVDS 1,2

VREFH_ADC_ ADC high reference -0.3 — 6.0 V — —

0123, VREFH_ voltage 1,2
ADC_456

VREFL_ADC_ ADC low reference -0.3 — 0.3 V — —

0123, VREFL_ voltage 1
ADC_456

VREFH_SDADC_ SDADC high -0.3 — 6.0 V — —

01, VREFH_ reference voltage 1,2
SDADC_23

VREFL_SDADC_ SDADC low -0.3 — 0.3 V — —

01, VREFL_ reference voltage 1
SDADC_23

VGPIO_trans Transient - — 6.0 V — —

overshoot voltage
allowed on I/
O pin 1,2,4

I_INJPAD_DC_ Continuous DC -3 — 3 mA — —
ABS input current
(positive/negative)
that can be injected
into an I/O pin 5

I_INJSUM_DC_ Sum of absolute — — 30 mA — —

ABS value of injected
currents on all the
I/O pins (continuous
DC limit) 5

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 14 / 120
NXP Semiconductors
General

Table 3. Absolute maximum ratings (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

TSTG Storage ambient -55 — 150 °C — —

temperature 6

1. All voltages are referred to VSS unless otherwise specified.

2. 6.0 V maximum for 10 hours over lifetime; 7.0 V maximum for 60 seconds over lifetime.
3. Voltage at VDD_DCDC cannot be higher than VDD_HV_A.
4. Absolute max rating must be honored under all conditions, including current injection.
5. When input pad voltage levels are close to VDD_HV_A (respectively to VDD_HV_B) or VSS, practically no current injection
is possible. See application note AN4731 for a description of injection current on NXP automotive microcontrollers.
6. TSTG specifies the storage temperature range. It is not the operating temperature range. Please refer to the Thermal
operating characteristics table.

5.2 Voltage and current operating requirements

NOTE
Device functionality is guaranteed down to the LVR assert level, however electrical performance of 12-bit ADC,
CMP with 8-bit DAC, IO electrical characteristics, and communication modules electrical characteristics will be
degraded when voltage drops below 2.97 V.

NOTE
DSPI/MSC interface is supported only at VDD_HV_A = 5V.

Table 4. Voltage and current operating requirements

Symbol Description Min Typ Max Unit Condition Spec

Number

VDD_HV_A Main I/O and analog 2.97 3.3 or 5.0 5.5 V — —

supply voltage 1

VDD_HV_B Secondary I/O 2.97 3.3 or 5.0 5.5 V — —

supply voltage 1

VDD_DCDC Supply voltage for 2.97 3.3 or 5.0 5.5 V — —

the SMPS gate
driver 1,2

V15 Voltage sensing 1.425 1.5 1.65 V — —

input 1,3

VDDA_SWG Supply voltage for 2.97 3.3 or 5.0 5.5 V — —

SWG 1,4

VDD_LVDS Supply voltage for 2.97 3.3 3.63 V — —

LVDS 1,5

VDD_SDADC Supply voltage for 4.5 5 5.5 V — —

SDADC 1,4,6

VREFH_SAR_ SAR ADC 2.97 3.3 or 5.0 5.5 V — —

0123, VREFH_ high reference
SAR_456 voltage 1,7,8

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 15 / 120
NXP Semiconductors
General

Table 4. Voltage and current operating requirements (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

VREFL_SAR_ SAR ADC low -0.1 0 0.1 V — —

0123, VREFL_ reference voltage 1
SAR_456

VREFH_SDADC_ SDADC high 4.5 5.0 5.5 V — —

01, VREFH_ reference
SDADC_23 voltage 1,6,7,8

VREFL_SDADC_ SDADC low -0.1 0 0.1 V — —

01, VREFL_ reference voltage 1
SDADC_23

VREFH_R2R R2R high reference 4.5 5.0 5.5 V — —

voltage 8

VREFL_R2R R2R low reference -0.1 0 0.1 V — —

voltage

VSS_DCDC Power ground for the -0.1 0 0.1 V — —

SMPS gate driver 1

V25 Flash memory — 2.5 — V — —

and clock
supply (2.5 V),
internally regulated 1

V11 High-current core — 1.14 — V — —

logic supply input 1

VGPIO Input voltage range -0.3 — VDD_HV V — —

at any I/O or analog _A/B +
pin 1 0.3

VODPU Open-drain pull-up — — VDD_HV V — —

voltage 1,9 _A/B

IINJPAD_DC_OP Continuous DC input -3 — 3 mA VDD_HV_A >= 3.6V —

current (positive/
negative) that can be
injected into an I/O
pin 10

IINJPAD_DC_OP Continuous DC input -2 — 3 mA VDD_HV_A >= 2.97V —

current (positive/
negative) that can be
injected into an I/O
pin 10

IINJSUM_DC_OP Sum of -30 — 30 mA VDD_HV_A >= 3.6V —

absolute value of
injected currents
on all the I/O
pins (continuous
DC limit) 10

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 16 / 120
NXP Semiconductors
General

Table 4. Voltage and current operating requirements (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

IINJSUM_DC_OP Sum of -20 — 30 mA VDD_HV_A >= 2.97V —

absolute value of
injected currents
on all the I/O
pins (continuous
DC limit) 10

IINJ_LVDS Max LVDS RX or TX 0 — 100 µA — —

pin injection current

Vramp_slow Supply ramp rate 0.5 — — V/min — —

(slow) 1,11

Vramp_fast Supply ramp rate — — 100 V/ms — —

(fast) 1,11

1. All voltages are referred to VSS unless otherwise specified.

2. Voltage at VDD_DCDC cannot be higher than VDD_HV_A
3. Min and Max values are applicable only for non-SMPS mode where V15 is sourced externally.
4. Must be shorted to VDD_HV_A at the PCB level
5. Ensure that VDD_HV_A ramps before VDD_LVDS.
6. SDADC is intended to be used only when VDD_HV_A is supplied with 5V. In case of VDD_HV_A is supplied with 3.3V it is
recommended to disable SDADC in MC_ME module
7. VREFH should always be equal to or less than VDD_HV_A +0.1. Any positive differential voltage between VREFH and
VDD_HV_A i.e., VDD_HV_A < VREFH <= VDD_HV_A + 0.1V) is for RF-AC only. Appropriate decoupling capacitors should
be used to filter noise on the supplies. See application note AN5032 for reference supply design for SAR ADC
8. All the VREFH_xx except of VREFH_R2R must be shorted to single supply source at the PCB level, either isolated
voltage reference or shorted to VDD_HV_A. Isolated VREFH_R2R is required to avoid SDADC performance degradation.
If isolated supply cannot be used, then appropriate filtration is needed to isolate the VREFH_R2R noise
9. Open-drain outputs must be pulled respectively to their supply rail (VDD_HV_A or VDD_HV_B).
10. When input pad voltage levels are close to VDD_HV_A (respectively to VDD_HV_B) or VSS, practically no current injection
is possible.
11. The MCU supply ramp rate parameter must be applicable to the MCU input/external supplies. The ramp rate assumes that
the S32K396 Hardware design guidelines document available on http://www.nxp.comare followed.

If total power dissipation and maximum junction temperature allows. Please refer to Thermal operating characteristics table for
the maximum junction temperature, and Thermal characteristics table for the thermal characteristics, to determine the maximum
power dissipation allowed for a given package.
Voltage at VDD_DCDC cannot be higher than VDD_HV_A.

5.2.1 Supported voltage supply use-cases

Table 5. Supported voltage supply use-cases

VDD_HV_A is 3.3 V VDD_HV_A is 5 V

VDD_HV_B is 3.3 V yes yes

VDD_HV_B is 5 V no yes

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 17 / 120
NXP Semiconductors
Power management

5.3 Thermal operating characteristics

Table 6. Thermal operating characteristics

Symbol Description Min Typ Max Unit Condition Spec

Number

Tamb Ambient temperature -40 — 125 °C — —

TJ Junction -40 — 150 °C — —

temperature

5.4 ESD and Latch-up Protection Characteristics

Table 7. ESD and Latch-up Protection Characteristics

Symbol Description Min Typ Max Unit Condition Spec

Number

Vhbm Electrostatic -2000 — 2000 V — —

discharge voltage,
human body model
(HBM) 1,2,3

Vcdm Electrostatic -500 — 500 V — —

discharge voltage,
charged-device
model (CDM),
all pins except
corner 1,3,4

Vcdm Electrostatic -750 — 750 V — —

discharge voltage,
charged-device
model (CDM), corner
pins 1,3,4

Ilat Latch-up current at -100 — 100 mA — —

ambient temperature
of 125°C 5

1. Device failure is defined as: "If after exposure to ESD pulses, the device does not meet specification requirements."
2. This parameter is tested in conformity with AEC-Q100-002.
3. All ESD testing conforms with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
4. This parameter is tested in conformity with AEC-Q100-011.
5. This parameter is tested in conformity with AEC-Q100-004.

6 Power management

6.1 Supply Monitoring

Table 8. Supply Monitoring

Symbol Description Min Typ Max Unit Condition Spec

Number

HVD_V15 High Voltage Detect — 2.5 — V — —

(HVD) on V15,

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 18 / 120
NXP Semiconductors
Power management

Detect (LVD5A) on
VDD_HV_A, assert
threshold (in FPM)

— VDD_HV_A — 37.5 — mV — —
LVD monitor
hysteresis

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 19 / 120
NXP Semiconductors
Power management

Table 8. Supply Monitoring (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

VPOR_VDD_HV_A Power-On-Reset 0.9 1.5 2.2 V — —

(VPOR) on
VDD_HV_A,
deassert threshold

VREF12 Bandgap reference, 1.18 1.2 1.22 V — —

trimmed

1. The HVD_V15 monitor is provided to indicate if the V15 rail is far above the standard V15 operating range , to ensure
failures in the V15 regulator are detected

6.2 Recommended Decoupling Capacitors

Table 9. Recommended Decoupling Capacitors

Symbol Description Min Typ Max Unit Condition Spec

Number

CDEC Decoupling 70 100 — nF — —

capacitor (one per
supply pin, at least
one per side) 1,2,3

CBULK Input supply bulk — 4.7 — µF — —

capacitor 3,4,5,6

COUT_V11 V11 (1.1V — 22 — µF — —

Regulator)
output capacitor 3

COUT_V25 V25 (2.5V 140 220 — nF — —

Regulator) output
capacitor 2,3

1. Optionally, 10 nF capacitors can be added in parallel to the decoupling capacitors.

2. These capacitors must be placed as close as possible to the corresponding supply and ground pins. For BGA
packages, the capacitors must be placed on the other side of the PCB to minimize the trace lengths.
3. All capacitors must be low ESR ceramic capacitors (for example, X7R). The minimum recommendation is after
considering component aging and tolerance.
4. For devices where the VDD_HV_B domain is present, if the VDD_HV_B supply is different supply from VDD_HV_A, a
dedicated bulk capacitor is needed.
5. It is also possible to use higher capacitance values (for example, 10 μF) in place of the 4.7 μF capacitor.
6. These capacitors must be placed close to the source.

Only needed when internal SMPS is used to generate V15 and VDD_DCDC is supplied with isolated source from VDD_HV_A
or VDD_HV_B
For devices where V15 is present, the V15 regulator output capacitor and the filter capacitors are required when using an
NPN bipolar ballast transistor for the regulation stage. When V15 is supplied from an external regulator, these capacitance
recommendations can be followed in addition to the capacitance requirements of the external voltage regulator.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 20 / 120
NXP Semiconductors
Power management

S32K396
176LQFP

V25
20 V25
COUT_V25

V11
22 V11
37 V11
COUT_V11 CDEC CDEC CDEC CDEC 61 V11
80 V11
108 V11
129 V11
152 V11
171 V11

PMIC option
V15
21 V15 VSSA_SWG01 161
CDEC VSSA_SDADC 142
CBULK 27
VSS_DCDC

VREFL_R2R 157
CBULK should be defined as per PMIC VREFL_SAR_0123 18
VREFL_SAR_456 155
VREFL_SDADC_01 143
V15 V11 VREFL_SDADC_23 139

12 NMOS_CTRL VSS 23
VSS 25
CNMOS NC 28 PMOS_CTRL VSS 38
VDD_HV_A /B VSS 60
29 VDD_DCDC VSS 79
VSS 109
VDD_HV_B VSS 130
39 VDD_HV_B VSS 153
59 VDD_HV_B VSS 172
CBULK CDEC 78 VDD_HV_B

VDD_HV_A
19 VDD_HV_A
110 VDD_HV_A
CBULK CDEC CDEC CDEC CDEC
131 VDD_HV_A
154 VDD_HV_A
173 VDD_HV_A

VDD_HV_A
141 VDDA_SDADC
VDD_HV_A
CDEC CDEC_EMI 162 VDDA_SWG01

CDEC

VDD_HV_A / VREF

17 VREFH_SAR_0123
156 VREFH_SAR_456

CDEC 144 VREFH_SDADC_01

CDEC_EMI CDEC CDEC_EMI CDEC CDEC_EMI CDEC CDEC_EMI
140 VREFH_SDADC_23
VREFH_R2R
158 VREFH_R2R

CBULK
CDEC CDEC_EMI

Figure 5. 176LQFP decoupling capacitor pinout diagram

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 21 / 120
NXP Semiconductors
Power management

S32K396
176LQFP

V25
20 V25
COUT_V25

V11
22 V11
37 V11
COUT_V11 CDEC CDEC CDEC CDEC 61 V11
80 V11
108 V11
129 V11
152 V11
171 V11

V15
21 V15 VSSA_SWG01 161
CDEC VSSA_SDADC 142
SMPS option VDD_DCDC can be supplied either from VDD_HV_A VSS_DCDC 27
or VDD_HV_B
VDD_DCDC V15 V11
V15 N-MOS VREFL_R2R 157
P-MOS VREFL_SAR_0123 18
L VREFL_SAR_456 155
VREFL_SDADC_01 143
COUT_V15_SMPS VREFL_SDADC_23 139
CNMOS
12 NMOS_CTRL
VSS 23
VSS 25
28 PMOS_CTRL VSS 38
VSS 60
29 VDD_DCDC VSS 79
CBULK_SMPS CDEC VSS 109
VDD_HV_B VSS 130
39 VDD_HV_B VSS 153
59 VDD_HV_B VSS 172
CBULK CDEC 78 VDD_HV_B

VDD_HV_A
19 VDD_HV_A
110 VDD_HV_A
CBULK CDEC CDEC CDEC CDEC
131 VDD_HV_A
154 VDD_HV_A
173 VDD_HV_A

VDD_HV_A
141 VDDA_SDADC
VDD_HV_A
CDEC CDEC_EMI 162 VDDA_SWG01

CDEC

VDD_HV_A / VREF

17 VREFH_SAR_0123
156 VREFH_SAR_456
144 VREFH_SDADC_01
CDEC CDEC_EMI CDEC CDEC_EMI CDEC CDEC_EMI CDEC CDEC_EMI 140 VREFH_SDADC_23
VREFH_R2R
158 VREFH_R2R

CBULK
CDEC CDEC_EMI

Figure 6. 176LQFP decoupling capacitor pinout diagram (SMPS)

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024
Data Sheet: Technical Data 22 / 120
NXP Semiconductors
Power management

S32K396
289MBGA

V25
J7 V25
COUT_V25

V11
E8 V11
H8 V11
COUT_V11 CDEC CDEC CDEC CDEC H9 V11
H10 V11
J8 V11
J10 V11
J13 V11
K8 V11
K9 V11
K10 V11
N7 V11
V15 PMIC option
H5 V15 VSSA_SWG01 B8
CDEC VSSA_SDADC E11
CBULK J6
VSS_DCDC
V15 V11
N-MOS VREFL_R2R B9
VREFL_SAR_0123 J6
CBULK should be defined as per PMIC
VREFL_SAR_456 E7
VREFL_SDADC_01 E9
VREFL_SDADC_23 G13
CNMOS
F1 NMOS_CTRL
VSS B2
VSS B16
VDD_HV_A/B NC K5 PMOS_CTRL VSS D4
VSS D9
L5 VDD_DCDC VSS E13
VSS F5
VDD_HV_B VSS G5
N4 VDD_HV_B VSS G7
R7 VDD_HV_B VSS G11
CBULK CDEC VSS J1
R10 VDD_HV_B
VSS J4
VSS J9
VSS J14
VDD_HV_A
VSS L7
D14 VDD_HV_A VSS L11
E5 VDD_HV_A VSS
CBULK CDEC CDEC CDEC CDEC M5
G10 VDD_HV_A VSS
N6
H7 VDD_HV_A VSS
N8
H13 VDD_HV_A VSS
N10
K11 VSS
VDD_HV_A P4
L8 VDD_HV_A VSS
P14
N9 VSS
VDD_HV_A VDD_HV_A T2
VSS
T7
E12 VDDA_SDADC VSS
VDD_HV_A T10
VSS
CDEC CDEC_EMI A7 VDDA_SWG01 T16

CDEC VDD_LVDS
N5 VDD_LVDS

CBULK CDEC

Can be connected to VDD_HV_B only

VDD_HV_A / VREF when operated at 3.3V or supplied externally

H6 VREFH_SAR_0123
E6 VREFH_SAR_456
CDEC CDEC CDEC_EMI E10 VREFH_SDADC_01
CDEC_EMI CDEC CDEC_EMI CDEC CDEC_EMI
F13 VREFH_SDADC_23
VREFH_R2R
A9 VREFH_R2R

CBULK
CDEC CDEC_EMI

Figure 7. 289BGA decoupling capacitor pinout diagram

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 23 / 120
NXP Semiconductors
Power management

S32K396
289MBGA

V25
J7 V25
COUT_V25

V11
E8 V11
H8 V11
COUT_V11 CDEC CDEC CDEC CDEC H9 V11
H10 V11
J8 V11
J10 V11
J13 V11
K8 V11
K9 V11
K10 V11
N7 V11
V15
H5 V15 VSSA_SWG01 B8
CDEC VSSA_SDADC E11
SMPS option VDD_DCDC can be supplied either from VDD_HV_A VSS_DCDC J6
or VDD_HV_B
VDD_DCDC V15 V11
V15 N-MOS VREFL_R2R B9
P-MOS
VREFL_SAR_0123 J6
L VREFL_SAR_456 E7
VREFL_SDADC_01 E9
COUT_V15_SMPS VREFL_SDADC_23 G13
CNMOS
F1 NMOS_CTRL
VSS B2
VSS B16
K5 PMOS_CTRL VSS D4
VSS D9
L5 VDD_DCDC VSS E13
CBULK_SMPS CDEC VSS F5
VDD_HV_B VSS G5
N4 VDD_HV_B VSS G7
R7 VDD_HV_B VSS G11
CBULK CDEC VSS J1
R10 VDD_HV_B
VSS J4
VSS J9
VSS J14
VDD_HV_A
VSS L7
D14 VDD_HV_A VSS L11
E5 VDD_HV_A VSS
CBULK CDEC CDEC CDEC CDEC M5
G10 VDD_HV_A VSS
N6
H7 VDD_HV_A VSS
N8
H13 VDD_HV_A VSS
N10
K11 VSS
VDD_HV_A P4
L8 VDD_HV_A VSS
P14
N9 VSS
VDD_HV_A VDD_HV_A T2
VSS
T7
E12 VDDA_SDADC VSS
VDD_HV_A T10
VSS
CDEC CDEC_EMI A7 VDDA_SWG01 T16

CDEC VDD_LVDS
N5 VDD_LVDS

CBULK CDEC

Can be connected to VDD_HV_B only

VDD_HV_A / VREF when operated at 3.3V or supplied externally

H6 VREFH_SAR_0123
E6 VREFH_SAR_456
CDEC CDEC CDEC_EMI E10 VREFH_SDADC_01
CDEC_EMI CDEC CDEC_EMI CDEC CDEC_EMI
F13 VREFH_SDADC_23
VREFH_R2R
A9 VREFH_R2R

CBULK
CDEC CDEC_EMI

Figure 8. 289BGA decoupling capacitor pinout diagram (SMPS)

6.3 V15 regulator (SMPS option) electrical specifications

The chip hardware design guidelines document lists the recommended part numbers for PMOS, Schottky diode and inductor.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 24 / 120
NXP Semiconductors
Power management

Table 10. V15 regulator (SMPS option) electrical specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

V15 V15 output — 1.5 — V — —

L_SMPS External coil — 4.7 — uH — —

inductance

COUT_V15_SMPS External bypass — 20-22 — uF — —

capacitor

— External bypass — 40-44 — uF — —

capacitor

D_SMPS External Schottky — 2 — A — —

diode average
forward current

VR Schottky diode 5.0 — — V — —

reverse voltage

IF Schottky diode 1.0 — — A — —

forward current

— External P-channel — — 10 nC VDD_DCDC = 5V —

MOSFET total gate
charge

— External P-channel — — 2 V — —
MOSFET threshold
voltage

CBULK_SMPS Input supply bulk — 22 — µF — —

capacitor for internal
SMPS 1

1. Only needed when internal SMPS is used to generate V15 and VDD_DCDC is supplied with isolated source from
VDD_HV_A or VDD_HV_B.

6.4 V11 regulator (NMOS ballast transistor control) electrical specifications

The chip hardware design guidelines document lists the recommended part number for NMOS.

Table 11. V11 regulator (NMOS ballast transistor control) electrical specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

V11 V11 output — 1.14 — V — —

V15 V15 input — 1.5 — V — —

VTH_NMOS Vth of external — — 1.5 V For 3.3 V supply —

NMOS

VTH_NMOS Vth of external — — 2 V For 5.0 V supply —

NMOS

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 25 / 120
NXP Semiconductors
Power management

Table 11. V11 regulator (NMOS ballast transistor control) electrical specifications (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

IDS_NMOS IDS of external 3 — — A — —

NMOS

tsettle_lm Required setting 10 — — us — —

time from V11 in
FPM to load change

CNMOS NMOS gate stability — 1 — nF — —

capacitor

6.5 Supply currents

NOTE
All data in this table is preliminary and based on first samples.

Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user
configuration. Typical conditions assumes VDD_HV_A = VREFH = 5 V, VDD_HV_B = 5V (if the VDD_HV_B domain present in the
device), temperature = 25 °C, and typical silicon process unless otherwise stated. In STANDBY configuration, no current flows
through the V15 supply.

Table 12. STANDBY mode supply currents

STANDBY 1

All clocks & SIRC ON FIRC ON (24 All

peripherals (µA) MHz) Configurations
OFF
(µA) (µA)
(µA)
VDD_HV_A 2

VDD_HV_A 2

VDD_HV_B 2
VDD_HV_A2

Chip Ambient Temperature (°C)

S32K396, 25, typ 3 75 78 1500 3

S32K394,
S32K376, 25, max 4 153 156 1693 3.8
S32K374,
S32K366, S32K364 105, typ 3 458 461 1869 16

105, max 4 1693 1721 3143 62

125, typ 3 756 759 2160 27

125, max 4 3034 3087 4490 108

1. See the configurations in Table 15.

2. IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the
application.
3. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A =
5.0V, VDD_HV_B = 5.0V, for the typical silicon process..

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 26 / 120
NXP Semiconductors
Power management

4. “max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),
VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, for the fast silicon process.

NOTE
All data in this table is preliminary and based on first samples.

Table 13. Low speed RUN mode supply currents

Low Speed RUN Mode (mA) 1

BOOT Mode 2 Low Speed RUN 2 All

Configurations
[Clock Option C] FIRC @ [Clock Option D] 2.
24 MHz
FIRC @48 MHz
VDD_HV_A 3, 4

VDD_HV_A 3, 4
V115

V115
Ambient VDD_HV_B 3
Temperature
Chip (°C)

S32K396, S32K394, 25, typ 6 3.2 61 3.2 93 1.8

S32K376, S32K374,
S32K366, S32K364 25, max 7 3.7 156 3.8 188 2.4

105, typ 6 3.3 215 3.3 244 1.6

105, max 7 4.3 760 4.3 790 2.0

125, typ 6 3.4 299 3.4 330 1.5

125, max 7, 8 5.3 1105 5.4 1127 2.0

1. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
2. See the example configurations in Table 15.
3. IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the
application.
4. RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail.
5. V11 is generated by V15 using external NMOS.
6. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A =
5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for the typical silicon process.
7. “max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),
VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15 = 1.65V, for the fast silicon process.
8. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum
specification, TJ < 150°C, to avoid self-heating.

NOTE
All data in this table is preliminary and based on first samples.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 27 / 120
NXP Semiconductors
Power management

NOTE
The data in this table is preliminary and based on first samples.

Table 14. Example RUN mode configuration supply currents

RUN Mode (mA) 1

2x 3ph Inverters + Resolver

eTPU Control (mA)
Configurations 2 3
,

Ambient Temperature (°C) V116

VDD_HV_A 4, 5

VDD_HV_B4
Chip

S32K396, 25, typ 7 6.4 5.3 547

S32K394,
S32K376, 25, max 8 8.7 6.8 654
S32K374,
S32K366, 105, typ 7 6.2 5.0 695
S32K364
105, max 8 9.4 6.6 1224

125, typ 7 6.3 4.4 777

125, max 8, 9 10.2 6.2 1470

1. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
2. See the configurations in Table 15.
3. VDD_HV_A current will increase/decrease with analog modules as per the use case.
4. IO current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application.
5. RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail.
6. V11 is generated by V15 using external NMOS.
7. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A =
5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for the typical silicon process.
8. “max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),
VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15 = 1.65V, for the fast silicon process.
9. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum
specification, TJ < 150°C, to avoid self-heating.

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Power management

6.6 Operating mode

Table 15. STANDBY and low speed RUN configuration options

STANDBY STANDBY STANDBY BOOT Mode FIRC Mode

(OptionC 1, FIRC
All OFF SIRC ON FIRC ON (OptionD 1, FIRC
@24 MHz)
MODULE @48 MHz)

Core M7_0 OFF OFF OFF OFF OFF

Core M7_1 OFF OFF OFF OFF OFF

Core M7_2/3 OFF OFF OFF 24 MHz Limited Activity

HSE_B OFF OFF OFF OFF OFF

FIRC OFF OFF 24 MHz 24 MHz 48 MHz

FXOSC OFF OFF OFF OFF OFF

SIRC OFF ON OFF ON ON

PLL OFF OFF OFF OFF OFF

Flash OFF OFF OFF ON ON

eDMA All OFF All OFF All OFF All OFF All OFF

FlexCAN All OFF All OFF All OFF All OFF All OFF

LPUART All OFF All OFF All OFF All OFF All OFF

LPSPI All OFF All OFF All OFF All OFF All OFF

LPI2C All OFF All OFF All OFF All OFF All OFF

EMAC OFF OFF OFF OFF OFF

Zipwire OFF OFF OFF OFF OFF

eMIOS All OFF All OFF All OFF All OFF All OFF

eTPU All OFF All OFF All OFF All OFF All OFF

eFlexPWM All OFF All OFF All OFF All OFF All OFF

IGF All OFF All OFF All OFF All OFF All OFF

SD_ADC All OFF All OFF All OFF All OFF All OFF

SWG All OFF All OFF All OFF All OFF All OFF

SAR_ADC All OFF All OFF All OFF All OFF All OFF

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Power management

Table 15. STANDBY and low speed RUN configuration options (continued)

STANDBY STANDBY STANDBY BOOT Mode FIRC Mode

(OptionC 1, FIRC
All OFF SIRC ON FIRC ON (OptionD 1, FIRC
@24 MHz)
MODULE @48 MHz)

LPCMP All OFF All OFF All OFF All OFF All OFF

1. See clocking use case examples in the Clocking chapter of the S32K39, S32K37 and S32K36 Reference Manual.

Table 16. RUN mode configuration options

Config Inverter Use-cases (Standalone or

Smart Actuator)

2x 3ph Inverters + Resolver eTPU

Control

K39x

Ambient Temperature 125C

CORE & PLATFORM CM7_0 320MHz

CM7_1 320MHz

CM7_2/3 (LS) 320MHz

Code Caches ON

Data Caches OFF

eDMA 2

HSE 1 80MHz (WFI)

TIMERS eTPUA 320MHz

eTPUB 320MHz

eFlexPWM2 12 CH

eMIOS 3 6 CH

Microsecond Channel(MSC) OFF

ANALOG 1Msps SAR-ADC 4 7 CH

SD-ADC + Coolflux 4 CH

SWG 2

COMMS Zipwire OFF

Ethernet ON

CAN-FD 4

SPI 5

LIN OFF

I2C 2

MEMORY QuadSPI OFF

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I/O parameters

Table 16. RUN mode configuration options (continued)

Flash Size 4M and 6M

TARGET PACKAGE 176 LQFP-EP Yes

289 MAPBGA Yes

1. HSE: After start-up, the HSE core is in WFI.

2. eFLEXPWM channels assumed evenly split between 2 instances
3. eMIOS0: 6 channels in PWM mode @ 20 KHz.
4. SAR and SD-ADC represents number of active instances.

6.7 Cyclic wake-up current

The cyclic wake-up current is the calculated average current consumption during the periodic switching between RUN mode and
STANDBY mode. This average current can be calculated with the following formula:
ICYCL = RUN Current According to Ratio + STANDBY Current According to Ratio
Where the Current According to Ratio value is calculated as follows:
Current According to Ratio = Supply Current × Ratio of Duration
As an example, the following data represents a case where the code is running a code in RUN mode and spending rest of the time
in STANDBY mode. The numbers in table below are representative only, and the Standby IDD numbers must be matched from
the IDD tables.

Device Supply Current1 Duration 2 [ms] Ratio of Current ICYCL -

Chip Operating Mode [μA] Duration 3 According to Average current
Ratio 4 [μA] 5 [μA]

S32K396, RUN 20000 0.2 0.005 100 159.7

S32K394,
STANDBY 60 39.8 0.995 59.7
S32K376,
S32K374,
S32K366,
S32K364

1. The supply current is obtained through the measurements of the current during the corresponding operating mode.
2. The duration is defined by the application (how much time will the device spend in the according operating mode).
3. The ratio of duration is obtained by dividing the duration of the corresponding operating mode by the total duration of the
application.
4. The current according to ratio is obtained by multiplying the supply current and the ratio of duration related to the proper
operating mode.
5. The average current is calculated by the addition of each device operating mode’s current according to ratio.

7 I/O parameters

7.1 GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)

The leakage current on the GPIO pins is specified as a function of the pad type (Standard, Standard Plus, Medium, Fast, or GPI)
and the number of Analog functions (CMP and ADC channels) multiplexed per pin.
The "Analog Function Count" is defined from the number of CMP and ADC channels multiplexed to a given pin. This information
can be obtained from the "Direct Signals" column in the IOMUX files attached to the Reference Manual. The "Analog Function
Count" is shown in the Condition column of the following table.

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Table 17. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)

Symbol Description Min Typ Max Unit Condition Spec

Number

VIH Input high level DC 0.70 x — VDD_HV V VDD_HV_A/B = 3.3V —

voltage threshold VDD_HV _A/B +
_A/B 0.3

VIL Input low level DC VSS - 0.3 — 0.30 x V VDD_HV_A/B = 3.3V —

voltage threshold VDD_HV
_A/B

WFRST RESET Input — — 33 ns — —

Filtered pulse width 1

WNFRST RESET Input not 100 — — ns — —

filtered pulse width 2

ILKG_33_S0 3.3V input leakage -181 — 600 nA Pins with Analog —

current for Standard Function Count = 0
GPIO 3

ILKG_33_S1 3.3V input leakage -1020 — 870 nA Pins with Analog —

current for Standard Function Count = 1
GPIO 3

ILKG_33_S2 3.3V input leakage -1880 — 1140 nA Pins with Analog —

current for Standard Function Count = 2,
GPIO 3 plus PTA12, PTD1

ILKG_33_S3 3.3V input leakage -2740 — 1410 nA Pins with Analog —

current for Standard Function Count = 3,
GPIO 3 plus PTD0

ILKG_33_SP0 3.3V input leakage -537 — 1270 nA Pins with Analog —

current for Standard Function Count = 0
Plus GPIO and
RESET IO 3

ILKG_33_SP1 3.3V input leakage -1270 — 1530 nA Pins with Analog —

current for Standard Function Count = 1
Plus GPIO and
RESET IO 3

ILKG_33_SP2 3.3V input leakage -2130 — 1800 nA Pins with Analog —

current for Standard Function Count = 2
Plus GPIO and
RESET IO 3

ILKG_33_M0 3.3V GPIO input -1300 — 1630 nA Pins with Analog —

leakage current for Function Count = 0
Medium GPIO 3

ILKG_33_M1 3.3V GPIO input -1560 — 1900 nA Pins with Analog —

leakage current for Function Count = 1,
Medium GPIO 3 plus PTC16, PTD5

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I/O parameters

Table 17. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

ILKG_33_M2 3.3V GPIO input -2410 — 2170 nA Pins PTD6 and PTE8 —
leakage current for
Medium GPIO 3

ILKG_33_F0 3.3V GPIO input -1860 — 2720 nA Pins with Analog —

leakage current for Function Count = 0
Fast GPIO 3

ILKG_33_F1 3.3V GPIO input -2200 — 2990 nA Pins with Analog —

leakage current for Function Count = 1
Fast GPIO 3

ILKG_33_ 3.3V input leakage -0.98 — 0.7 µA — —

TWINANAMUX current for
TWINANAMUX

VHYS_33 Input hysteresis 0.06 x — — mV Always Enabled —

voltage 4 VDD_HV
_A/B

CIN GPIO Input 2 4 6 pF add 2pF for package/ —

capacitance parasitic

IPU_33 3.3V GPIO pull up/ 20 — 60 kΩ pull up @ 0.3 x VDD_ —

down resistance HV_A/B, pull down @
0.7 x VDD_HV_A/B

IOH_33_S 3.3V output 1.0 — — mA VOH >= VDD_HV_A/B —

high current for - 0.7V
Standard GPIO 5,6

IOH_33_SP 3.3V output high 1.5 — — mA DSE = 0, VOH >= —

current for Standard VDD_HV_A/B - 0.7V
Plus GPIO and
RESET IO 5,6

IOH_33_M 3.3V output high 3 — — mA DSE = 0, VOH >= —

current for Medium VDD_HV_A/B - 0.7V
GPIO 5,6

IOH_33_F 3.3V output high 4.5 — — mA DSE = 0, VOH >= —

current for Fast VDD_HV_A/B - 0.7V
GPIO 5,6

IOH_33_SP 3.3V output high 3 — — mA DSE = 1, VOH >= —

current for Standard VDD_HV_A/B - 0.7V
Plus GPIO and
RESET IO 5,6

IOH_33_M 3.3V output high 6 — — mA DSE = 1, VOH >= —

current for Medium VDD_HV_A/B - 0.7V
GPIO 5,6

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I/O parameters

Table 17. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

IOH_33_F 3.3V output high 9 — — mA DSE = 1, VOH >= —

current for Fast VDD_HV_A/B - 0.7V
GPIO 5,6

IOL_33_S 3.3V output low 1.0 — — mA VOL <= 0.7V —

current for Standard
GPIO 5,6

IOL_33_SP 3.3V output low 1.5 — — mA DSE =0, VOL <= 0.7V —
current for Standard
Plus GPIO and
RESET IO 5,6

IOL_33_M 3.3V output low 3.0 — — mA DSE =0, VOL <= 0.7V —
current for Medium
GPIO 5,6

IOL_33_F 3.3V output low 4.5 — — mA DSE =0, VOL <= 0.7V —
current for Fast
GPIO 5,6

IOL_33_SP 3.3V output low 3 — — mA DSE =1, VOL <= 0.7V —

current for Standard
Plus GPIO and
RESET IO 5,6

IOL_33_M 3.3V output low 6 — — mA DSE =1, VOL <= 0.7V —

current for Medium
GPIO 5,6

IOL_33_F 3.3V output low 9 — — mA DSE =1, VOL <= 0.7V —

current for Fast
GPIO 5,6

FMAX_33_S 3.3V maximum — — 10 MHz 2.9V - 3.6V CL(max) = —

frequency for 25pF
Standard GPIO 5,7

FMAX_33_SP 3.3V maximum — — 25 MHz 2.9V - 3.6V CL (max) = —

frequency for 25pF
Standard Plus
GPIO 5,7

FMAX_33_M 3.3V maximum — — 50 MHz 2.9V - 3.6V CL (max) = —

frequency for 25pF
Medium GPIO 5,7

FMAX_33_F 3.3V maximum — — 120 MHz 2.9V - 3.6V CL (max) = —

frequency for Fast 25pF
GPIO 5,7

IOHT Output high current — — 100 mA — —

total for all ports 8

1. Maximum length of RESET pulse will be filtered by an internal filter on this pin.
2. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter.

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I/O parameters

3. A positive value is leakage flowing into pin with pin at VDD_HV_A/B (the GPIO supply level); a negative value is leakage
flowing out the pin with the pin at ground.
4. Hysteresis spec does not apply to fast pad
5. GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for
system level simulations, as discrete values for I/O transition times are not representative of the I/O pad behavior when
connected to an actual transmission line load.
6. I/O output current specifications are valid for the given reference load figure, and the constraints given in the Operating
Conditions of this document.
7. I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below.
A lumped 8pF load is assumed in addition to a 5 inch microstrip trace on standard FR4 with approximately 3.3pF/inch. For
signals with frequency greater than 63MHz, a maximum 2 inch PCB trace is assumed. For best signal integrity, the series
resistance in the transmission line should be matched closely to the selected output resistance (ROUT_*) of the I/O pad.
8. To determine total switching current on any I/O supply, current values per output pin should not be incrementally summed.
I/O interfaces on the device are asynchronous to each other, so not all switching occurs at the same instant. Actual use
case must be considered.

MCUsee note 1 PCB External

device
5 in.
(4 layer FR4)
CPCB = ~3.3 pF/inch * 5 inch

RDSON
RPCB = RDSON

RDSON CL = 8 pF

Notes:
1. See IBIS models for further details.

Figure 9. Reference Load Diagram

7.2 GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)

Table 18. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)

Symbol Description Min Typ Max Unit Condition Spec

Number

VIH Input high level DC 0.65 x — VDD_HV V VDD_HV_A/B = 5.0V —

voltage threshold VDD_HV _A/B +
_A/B 0.3

VIL Input low level DC VSS - 0.3 — 0.35 x V VDD_HV_A/B = 5.0V —

voltage threshold VDD_HV
_A/B

WFRST RESET Input filtered — — 33 ns — —

pulse width 1

WNFRST RESET Input not 100 — — ns — —

filtered pulse width 2

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I/O parameters

Table 18. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

ILKG_50_S0 5.0V input leakage -250 — 800 nA Pins with Analog —

current for Standard Function Count = 0
GPIO 3

ILKG_50_S1 5.0V input leakage -1300 — 1100 nA Pins with Analog —

current for Standard Function Count = 1
GPIO 3

ILKG_50_S2 5.0V input leakage -2300 — 1450 nA Pins with Analog —

current for Standard Function Count = 2,
GPIO 3 plus PTA12, PTD1

ILKG_50_S3 5.0V input leakage -3300 — 1750 nA Pins with Analog —

current for Standard Function Count = 3,
GPIO 3 plus PTD0

ILKG_50_SP0 5.0V input leakage -660 — 1760 nA Pins with Analog —

current for Standard Function Count = 0
Plus GPIO and
RESET IO 3

ILKG_50_SP1 5.0V input leakage -1510 — 2030 nA Pins with Analog —

current for Standard Function Count = 1
Plus GPIO and
RESET IO 3

ILKG_50_SP2 5.0V input leakage -2450 — 2290 nA Pins with Analog —

current for Standard Function Count = 2
Plus GPIO and
RESET IO 3

ILKG_50_M0 5.0V input leakage -1615 — 2270 nA Pins with Analog —

current for Medium Function Count = 0
GPIO 3

ILKG_50_M1 5.0V input leakage -1970 — 2540 nA Pins with Analog —

current for Medium Function Count = 1,
GPIO 3 plus PTC16,PTD5

ILKG_50_M2 5.0V input leakage -2830 — 2810 nA Pins PTD6 and PTE8 —
current for Medium
GPIO 3

ILKG_50_F0 5.0V input leakage -2120 — 3790 nA Pins with Analog —

current for Fast Function Count = 0
GPIO 3

ILKG_50_F1 5.0V input leakage -2980 — 4060 nA Pins with Analog —

current for Fast Function Count = 1
GPIO 3

ILKG_50_ 5.0V input leakage -1.1 — 1.1 µA — —

TWINANAMUX current for
TWINANAMUX

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I/O parameters

Table 18. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

VHYS_50 input hysteresis 0.06 x — — mV Always enabled —

voltage 4 VDD_HV
_A/B

CIN GPIO Input 2 4 6 pF add 2pF for package/ —

capacitance parasitic

IPU_50 5.0V GPIO pull up/ 20 — 55 kΩ pull up @ 0.3 * VDD_ —

down resistance HV_*, pull down @ 0.7
* VDD_HV_*

IOH_50_S 5.0V output 1.6 — — mA VOH >= VDD_HV_A/B —

high current - 0.7V
Standard GPIO 5,6

IOH_50_SP 5.0V output high 2.5 — — mA DSE = 0, VOH >= —

current Standard VDD_HV_A/B - 0.7V
Plus GPIO and
RESET IO 5,6

IOH_50_M 5.0V output high 4.0 — — mA DSE = 0, VOH >= —

current for Medium VDD_HV_A/B - 0.7V
GPIO 5,6

IOH_50_F 5.0V output high 6.0 — — mA DSE = 0, VOH >= —

current for Fast VDD_HV_A/B - 0.7V
GPIO 5,6

IOH_50_SP 5.0V output high 5.0 — — mA DSE = 1, VOH >= —

current for Standard VDD_HV_A/B - 0.7V
Plus GPIO and
RESET IO 5,6

IOH_50_M 5.0V output high 8.0 — — mA DSE = 1, VOH >= —

current for Medium VDD_HV_A/B - 0.7V
GPIO 5,6

IOH_50_F 5.0V GPIO output 12.0 — — mA DSE = 1, VOH >= —

high current for Fast VDD_HV_A/B - 0.7V
GPIO 5,6

IOL_50_S 5.0V output 1.6 — — mA VOL <= 0.7V —

low current for
Standard GPIO 5,6

IOL_50_SP 5.0V output low 2.5 — — mA DSE =0, VOL <= 0.7V —
current for Standard
Plus GPIO and
RESET IO 5,6

IOL_50_M 5.0V output low 4.0 — — mA DSE =0, VOL <= 0.7V —
current for Medium
GPIO 5,6

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I/O parameters

Table 18. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

IOL_50_F 5.0V output low 6.0 — — mA DSE =0, VOL <= 0.7V —
current for Fast
GPIO 5,6

IOL_50_SP 5.0V output low 5.0 — — mA DSE =1, VOL <= 0.7V —
current for Standard
Plus GPIO and
RESET IO 5,6

IOL_50_M 5.0V output low 8.0 — — mA DSE =1, VOL <= 0.7V —
current for medium
GPIO 5,6

IOL_50_F 5.0V output low 12.0 — — mA DSE =1, VOL <= 0.7V —
current for Fast
GPIO 5,6

FMAX_50_S 5.0V maximum — — 10 MHz 3.6V - 5.5V CL (max) = —

frequency for 25pF
Standard GPIO 5,7

FMAX_50_SP 5.0V maximum — — 25 MHz 3.6V - 5.5V CL (max) = —

frequency for 25pF
Standard Plus
GPIO 5,7

FMAX_50_M 5.0V maximum — — 25 MHz 3.6V - 5.5V CL (max) = —

frequency for 25pF
Medium GPIO 5,7

FMAX_50_F 5.0V maximum — — 25 MHz 3.6V - 5.5V CL (max) = —

frequency for Fast 25pF
GPIO 5,7

IOHT Output high current — — 100 mA — —

total for all ports 8

1. Maximum length of RESET pulse will be filtered by an internal filter on this pin.
2. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter.
3. A positive value is leakage flowing into pin with pin at VDD_HV_A/B (the GPIO supply level); a negative value is leakage
flowing out the pin with the pin at ground.
4. Hysteresis spec does not apply to fast pad
5. GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for
system level simulations, as discrete values for I/O transition times are not representative of the I/O pad behavior when
connected to an actual transmission line load.
6. I/O output current specifications are valid for the given reference load figure, and the constraints given in the Operating
Conditions of this document.
7. I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below.
A lumped 8pF load is assumed in addition to a 5 inch microstrip trace on standard FR4 with approximately 3.3pF/inch..
For best signal integrity, the series resistance in the transmission line should be matched closely to the selected output
resistance (ROUT_*) of the I/O pad.
8. To determine total switching current on any I/O supply, current values per output pin should not be incrementally summed.
I/O interfaces on the device are asynchronous to each other, so not all switching occurs at the same instant. Actual use
case must be considered.

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NXP Semiconductors
I/O parameters

MCUsee note 1 PCB External

device
5 in.
(4 layer FR4)
CPCB = ~3.3 pF/inch * 5 inch

RDSON
RPCB = RDSON

RDSON CL = 8 pF

Notes:
1. See IBIS models for further details.

Figure 10. Reference Load Diagram

7.3 3.3V (2.97V - 3.63V) GPIO Output AC Specification

Table 19. 3.3V (2.97V - 3.63V) GPIO Output AC Specification

Symbol Description Min Typ Max Unit Condition Spec

Number

TR_TF_33_S 3.3V Standard GPIO 5 — 28 ns CL (max) = 25pF —

rise/fall time 1,2,3

TR_TF_33_S 3.3V Standard GPIO 9.5 — 43 ns CL (max) = 50pF —

rise/fall time 1,2,3

TR_TF_33_SP 3.3V Standard 4 — 17.5 ns DSE=0 CL (max) = —

Plus GPIO rise/fall 25pF
time 1,2,3

TR_TF_33_SP 3.3V Standard 1.9 — 10 ns DSE=1 CL (max) = —

Plus GPIO rise/fall 25pF
time 1,2,3

TR_TF_33_SP 3.3V Standard 7.5 — 27 ns DSE=0 CL (max) = —

Plus GPIO rise/fall 50pF
time 1,2,3,4

TR_TF_33_SP 3.3V Standard 3.5 — 15 ns DSE=1 CL (max) = —

Plus GPIO rise/fall 50pF
time 1,2,3,4

TR_TF_33_M 3.3V Medium GPIO 2.2 — 12.3 ns DSE=0, SRE=0 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_33_M 3.3V Medium GPIO 3.0 — 14 ns DSE=0, SRE=1 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_33_M 3.3V Medium 0.8 — 6.6 ns DSE=1, SRE=0 CL —

GPIO rise/fall (max) = 25pF
time 1,2,3

TR_TF_33_M 3.3V Medium GPIO 2.4 — 10.5 ns DSE=1, SRE=1 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_33_M 3.3V Medium GPIO 4.5 — 17.3 ns DSE=0, SRE=0 CL —

rise/fall time 1,2,3,4 (max) = 50pF

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I/O parameters

fall time 1,2,3,4 (max) = 50pF

1. I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below.
A lumped 8pF load (typical) is assumed at the end of a 5 inch microstrip trace on standard FR4 with approximately 3.3pF/
inch. For signals with frequency greater than 63MHz, a maximum 2 inch PCB trace is assumed. For best signal integrity,
the series resistance in the transmission line should be matched closely to the selected output resistance (ROUT_*) of the
I/O pad.
2. GPIO rise/fall time specifications are derived from simulation model for the defined operating points (between 20% and
80% of VDD_HV_A/B level). Actual application rise/fall time should be extracted from IBIS model simulations with the
microcontroller models and application PCB.
3. GPIO output transistion time information can be obtained from the device IBIS model. IBIS models are recommended for
system level simulations, as discrete values for I/O transition times are not representative of the I/O pad behavior when
connected to an actual transmission line load.
4. Output timing valid for maximum external load C L = 50pF (includes PCB trace, package trace, and external device input
load).

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NXP Semiconductors
I/O parameters

MCUsee note 1 PCB External

device
5 in.
(4 layer FR4)
CPCB = ~3.3 pF/inch * 5 inch

RDSON
RPCB = RDSON

RDSON CL = 8 pF

Notes:
1. See IBIS models for further details.

Figure 11. Reference Load Diagram

7.4 5.0V (4.5V - 5.5V) GPIO Output AC Specification

Table 20. 5.0V (4.5V - 5.5V) GPIO Output AC Specification

Symbol Description Min Typ Max Unit Condition Spec

Number

TR_TF_50_S 5.0V Standard GPIO 5 — 21 ns CL (max) = 25pF —

rise/fall time 1,2,3

TR_TF_50_S 5.0V Standard GPIO 8.5 — 31 ns CL (max) = 50pF —

rise/fall time 1,2,3,4

TR_TF_50_SP 5.0V Standard 3 — 13.2 ns DSE=0 CL (max) = —

Plus GPIO rise/fall 25pF
time 1,2,3

TR_TF_50_SP 5.0V Standard 1 — 7.1 ns DSE=1 CL (max) = —

Plus GPIO rise/fall 25pF
time 1,2,3

TR_TF_50_SP 5.0V Standard 6.4 — 18.8 ns DSE=0 CL (max) = —

Plus GPIO rise/fall 50pF
time 1,2,3,4

TR_TF_50_SP 5.0V Standard 3.4 — 11 ns DSE=1 CL (max) —

Plus GPIO rise/fall =50pF
time 1,2,3,4

TR_TF_50_M 5.0V Medium GPIO 1.8 — 8.2 ns DSE=0, SRE=0 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_50_M 5.0V Medium GPIO 2.5 — 9.8 ns DSE=0, SRE=1 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_50_M 5.0V Medium GPIO 0.7 — 4.5 ns DSE=1, SRE=0 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_50_M 5.0V Medium GPIO 1.8 — 7.2 ns DSE=1, SRE=1 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_50_M 5.0V Medium GPIO 3.95 — 13.2 ns DSE=0, SRE=0 CL —

rise/fall time 1,2,3,4 (max) = 50pF

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 41 / 120
NXP Semiconductors
I/O parameters

8.1 eTPU timing

Table 21. eTPU timing

Symbol Description Min Typ Max Unit Condition Spec

Number

tICPW eTPU input channel 4 — — tPER_CL — —

pulse width 1,2 K

tOCPW eTPU output 1 — — tPER_CL — —

channel pulse K
width 1,2

1. tPER_CLK is the period of the peripheral clock (PER_CLK) on the device.

2. Value in the table represent the minimum pulse which is the module capable to process. When the input signal is going
from the pins there can be limitation done by the pin parameters and its external circuity

eTPU input

tICPW

tOCPW

eTPU output

Figure 13. eTPU timing

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 43 / 120
NXP Semiconductors
Real-time control

8.2 eTPU skew characteristics

Table 22. eTPU skew characteristics

Symbol Description Min Typ Max Unit Condition Spec

Number

tSCP Skew in — — 3 ns — —
Complementary
Pair 1

tTS Total Skew 2 — — 13 ns — —

1. etpu_A channels only PTC8/PTC29 , PTA7/PTC30 , PTA6/PTC31 , PTD20/PTB16, PTB15/PTB14 , PTD21/PTB13 , PTD3/
PTD2 , PTD23/PTA3 , PTA2/PTD24
2. etpu_A channels only Group1 (PTC8/PTC29, PTA7/PTC30, PTA6/PTC31), Group2(PTD20/PTB16, PTB15/PTB14,
PTD21/PTB13) and Group3 (PTD3/PTD2, PTD23/PTA3, PTA2/PTD24)

8.3 eMIOS
Table 23. eMIOS

Symbol Description Min Typ Max Unit Condition Spec

Number

tMIPW eMIOS input pulse 4 — — tPER_CL — —

width 1,2 K

tMOPW eMIOS output pulse 1 — — tPER_CL — —

width 1,2,3 K

1. tPER_CLK is the period of the peripheral clock (PER_CLK) on the device.

tMOPW

eMIOS
output

eMIOS
input

tMIPW

Figure 14. EMIOS Timing

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 44 / 120
NXP Semiconductors
Real-time control

8.4 LCU
Table 24. LCU

Symbol Description Min Typ Max Unit Condition Spec

Number

tMIPW LCU input pulse 4 — — tPER_CL — —

width 1,2 K

tMOPW LCU output pulse 1 — — tPER_CL — —

width 1,2,3 K

1. tPER_CLK is the period of the peripheral clock (PER_CLK) on the device.

tMOPW

LCU
output

LCU
input

tMIPW

Figure 15. LCU timing

8.5 LCU skew characteristics

Table 25. LCU skew characteristics

Symbol Description Min Typ Max Unit Condition Spec

Number

tSCP Skew in — — 3 ns — —
Complementary
Pair 1

tTS Total Skew 2 — — 13 ns — —

1. Pairs (For LCU_0 (PTD20/PTB16, PTB15/PTB14, PTD21/PTB13)), For LCU_1 (PTC28/PTC9 , PTC8 /PTC29, PTA7/
PTC30, PTA6/PTC31))
2. LCU_0 group:(PTD20/PTB16, PTB15/PTB14, PTD21/PTB13), LCU_1 group: (PTC28 /PTC9 , PTC8/ PTC29, PTA7/
PTC30, PTA6/PTC31)

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 45 / 120
NXP Semiconductors
Glitch Filter

9 Glitch Filter
Table 26. Glitch Filter

Symbol Description Min Typ Max Unit Condition Spec

Number

TFILT Glitch filter max — — 20 ns — —

filtered pulse
width 1,2,3

TUNFILT Glitch filter min 400 — — ns — —

unfiltered pulse
width 2,3,4

1. Pulses shorter than defined by the maximum value are guaranteed to be filtered (not passed).
2. An input signal pulse is defined by the duration between the input signal's crossing of a Vil/Vih threshold voltage level, and
the next crossing of the opposite level.
3. Pulses in between the max filtered and min unfiltered may or may not be passed through.
4. Pulses larger than defined by the minimum value are guaranteed to not be filtered (passed).

10 LVDS specifications

10.1 LVDS 3.3V Receiver Electrical Specifications

These specifications are related to LVDS pads dedicated to Zipwire.

Table 27. LVDS 3.3V Receiver Electrical Specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

Dmax Maximum Data Rate — — 480 Mbps — —

VID Input differential 100 — 400 mV — —

signal swing

VICM Input signal common 0.2 — 1.8 V — —

mode

Duty Cycle Duty Cycle on Core 40 — 60 % — —

side port for a
50% duty cycle input
differential

Rterm On die termination 80 100 135 Ohm — —

resistance

Tstart Startup Time — — 1 us — —

Vfault_fall pad_p,pad_n voltage 50 — 200m mV — —

threshold below
which open driver
detection asserts the
fault indicator

Vfault_rise pad_p,pad_n voltage 50 — 200m mV — —

threshold above
which open driver

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 46 / 120
NXP Semiconductors
LVDS specifications

Table 27. LVDS 3.3V Receiver Electrical Specifications (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

detection de-asserts
the fault indicator

Ipin_leakage_ Pin Leakage with -5 — 5 uA — —

disabled Receiver disabled

Ipin_leakge_ Pin Leakage with -5 — 100 uA — —

enabled Receiver enabled

IDD_VDD33_RUN VDD33 current — — 3 mA — —

consumption when
enabled

10.2 LVDS 3.3V Transmitter Electrical Specifications

These specifications are related to LVDS pads dedicated to Zipwire.

Table 28. LVDS 3.3V Transmitter Electrical Specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

Dmax Maximum Data Rate — — 480 Mbps — —

VOD Output differential 200 300 450 mV — —

swing

VCM Output Common 1.1 1.2 1.3 V — —

Mode

VOH Output High VCM+10 — — V — —

Indicator 0m

VOL Output Low indicator — — VCM-100 V — —

Dj Deterministic Jitter — — 100 ps — —

through the LVDS Tx
I/O

Ipin_leakage Pin -5 — 5 uA — —
Leakage(disabled
condition)

IDD_VDD33_RUN VDD33 current — — 7 mA — —

consumption when
enabled

— Startup Time — — 1 us — —

Cload Max load — — 10 pF — —

specification

Ztline pad_p , pad_n board 47.5 50 52.5 Ohm — —

Tline impedance

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 47 / 120
NXP Semiconductors
eFlexPWM

10.3 LVDS 5V Transmitter Electrical Specifications

These specifications are related to LVDS pads dedicated to MSC.

Table 29. LVDS 5V Transmitter Electrical Specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

Dmax Maximum Data Rate — — 80 Mbps — —

VOD Output differential 200 300 400 mV — —

swing

VCM Output Common 1.1 1.2 1.3 V — —

Mode

VOH Output High VCM+10 — — V — —

Indicator 0m

VOL Output Low indicator — — VCM-100 V — —

Dj Determinstic jitter — — 250 ps — —

through the LVDS Tx
I/O

Ipin_leakage Pin -5.6 — 5.6 uA — —

Leakage(disabled
condition)

IDD_VDDE_RUN VDDE current — — 7.5 mA — —

consumption when
enabled

Cload Max load — — 10 pF — —

specification

Ztline pad_p,pad_n board 47.5 50 52.5 Ohm — —

Tline impedance

ZTLDIFF Transmission 95 100 105 Ohm — —

line differential
impedance

11 eFlexPWM
Table 30. eFlexPWM

Symbol Description Min Typ Max Unit Condition Spec

Number

Fref Input Clock — 320 — MHz — —

frequency

Tdelay PWM Delay — 195 — ps — —

Resolution

Tlock DLL Lock Time — — 25 us — —

IVDD Current — — 8 mA only for single instance —

Consumption of PWM

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 48 / 120
NXP Semiconductors
Flash memory specification

11.1 eFlexPWM skew characteristics

Table 31. eFlexPWM skew characteristics

Symbol Description Min Typ Max Unit Condition Spec

Number

tSCP Skew in — — 3 ns — —
Complementary
Pair 1

tTS Total Skew 2 — — 13 ns — —

1. Pairs(For PWM_0:( PTD4/PTD22, PTD2/PTD3 , PTA3/PTD23, PTD24/PTA2 ), For PWM_1:(PTC9/PTC28, PTC29/PTC8,

PTC30/PTA7, PTC31/PTA6))
2. PWM_0 group:( PTD4/PTD22, PTD2/PTD3 , PTA3/PTD23, PTD24/PTA2 ), For PWM_1 group: (PTC9/PTC28, PTC29/
PTC8, PTC30/PTA7, PTC31/PTA6)

12 Flash memory specification

12.1 Flash memory program and erase specifications

Table 32. Flash memory program and erase specifications

Symbol Characteristic1 Typ2 Factory Field Update Unit

Programming3,4

Initial Max Initial Max, Typical Lifetime Max6

Full Temp End of
Life5

20°C ≤TA -40°C ≤TJ -40°C ≤TJ ≤ 1,000 ≤ 100,000

≤30°C ≤150°C ≤150°C cycles cycles

tdwpgm Doubleword (64 bits) program time 102 122 129 111 150 µs

tppgm Page (256 bits) program time 142 171 180 157 200 µs

tqppgm Quad-page (1024 bits) 314 377 396 341 450 µs

program time

t8kpgm 8 KB Sector program time 20 24 26 22 30 ms

t8kers 8 KB Sector erase time 4.8 8.5 10.6 6.5 30 ms

t256kbers 256KB Block erase time 22.8 27.4 28.8 24.4 40 — ms

t512kbers 512KB Block erase time 25.4 30.5 32.1 27.9 45 — ms

t1mbers 1MB Block erase time 30.6 36.8 38.7 33.6 50 — ms

t2mbers 2MB Block erase time 41.1 49.3 51.8 45.2 60 — ms

1. Program times are actual hardware programming times and do not include software overhead. Sector program times
assume quad-page programming.
2. Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
3. Conditions: ≤ 25 cycles, nominal voltage.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 49 / 120
NXP Semiconductors
Flash memory specification

4. Plant Programing times provide guidance for timeout limits used in the factory.
5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.
6. Conditions: -40°C ≤TJ ≤150°C, full spec voltage.

12.2 Flash memory Array Integrity and Margin Read specifications

Table 33. Flash memory Array Integrity and Margin Read specifications

Symbol Characteristic Min Typical Max1 2 Units3

tai256kseq Array Integrity time and Margin — — 8192 x Tperiod x Nread —

Read time for sequential sequence
(plus 40uS adder required if User
on 256KB block.
Margin Read)

tai512kseq Array Integrity time and Margin — — 16384 x Tperiod x Nread —

Read time for sequential sequence
(plus 40uS adder required if User
on 512KB block.
Margin Read)

tai1mseq Array Integrity time and Margin — — 32768 x Tperiod x Nread —

Read time for sequential sequence
(plus 40uS adder required if User
on 1MB block.
Margin Read)

tai2mseq Array Integrity time and Margin — — 65536 x Tperiod x Nread —

Read time for sequential sequence
(plus 40uS adder required if User
on 2MB block.
Margin Read)

tai256kprop Array Integrity time for proprietary — — 106496 —

sequence on 256KB block. x Tperiod x Nread

tai512kprop Array Integrity time for proprietary — — 229376 —

sequence on 512KB block.
x Tperiod x Nread

tai1mprop Array Integrity time for proprietary — — 491520 —

sequence on 1MB block. x Tperiod x Nread

tai2mprop Array Integrity time for proprietary — — 1048576 —

sequence on 2MB block. x Tperiod x Nread

1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The
equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and
Nread (which is the number of clocks required for read, including single read, dual read, quad read contribution. Thus for a
read setup that requires 6 clocks to read Nread would equal 6.
2. Array Integrity times are actual hardware execution times and do not include software overhead or system code execution
overhead.
3. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 50 / 120
NXP Semiconductors
Flash memory specification

12.3 Flash memory module life specifications

Table 34. Flash memory module life specifications

Symbol Characteristic Conditions Min Typical Units

Array P/E Number of program/erase cycles per block — 100,000 — P/E

cycles for 256 KB and 512 KB blocks using cycles
Sector Erase.

Number of program/erase cycles per block for — 1,000 — P/E

1 MB and 2 MB blocks using Sector Erase. cycles

Number of program/erase cycles per block — 25 — P/E

using Block Erase1 cycles

Data Minimum data retention. Blocks with 0 - 1,000 20 — Years

retention P/E cycles.

Blocks with 100,000 10 — Years

P/E cycles.

1. Program and erase supported for factory conditions. Nominal supply values and operation at 25°C.

12.3.1 Data retention vs program/erase cycles

Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure.
The spec window represents qualified limits.

25
Minimum Data Retention Life (Years)

0
1 10 100 1000 10000 100000 1000000
P/E Cycles (Sector Erases)

Figure 16. Data retention vs program/erase cycles

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 51 / 120
NXP Semiconductors
Flash memory specification

12.4 Flash memory AC timing specifications

Table 35. Flash memory AC timing specifications

Symbol Characteristic Min Typical Max Units

tdone Time from 0 to 1 transition on the MCR[EHV] bit — — 5 ns

initiating a program/erase until the MCR[DONE]
bit is cleared.

tdones Time from 1 to 0 transition on the MCR[EHV] bit 5 plus four — 22 plus four µs
aborting a program/erase until the MCR[DONE] system clock system clock
bit is set to a 1. periods periods1

tdrcv Time to recover once exiting low power mode. 14 plus seven 17.5 plus 21 plus seven µs
system clock seven system system clock
periods2 clock periods periods

taistart Time from 0 to 1 transition of UT0[AIE] initiating a — — 5 ns

Margin Read or Array Integrity until the UT0[AID]
bit is cleared. This time also applies to the
resuming from a suspend or breakpoint by
clearing UT0[AISUS] or clearing UT0[NAIBP]

taistop Time from 1 to 0 transition of UT0[AIE] initiating — — 50 ns

an Array Integrity abort until the UT0[AID] bit is system clock
set. This time also applies to the UT0[AISUS] to periods
UT0[AID] setting in the event of a Array Integrity
suspend request.

tmrstop Time from 1 to 0 transition of UT0[AIE] initiating — — 26 µs

a Margin Read abort until the UT0[AID] bit is
plus fifteen
set. This time also applies to the UT0[AISUS] to
system clock
UT0[AID] setting in the event of a Margin Read
periods
suspend request.

1. For Block Erase, Tdones times may be 3x max spec.

2. In extreme cases (1 block configurations) Tdrcv min may be faster (12uS plus seven system clocks)

12.5 Flash memory read timing parameters

Table 36. Flash Read Wait State Settings (S32K396, S32K394, S32K376, S32K374, S32K366 and S32K364 )

Flash Frequency RWSC setting

250 KHz < Freq ≤ 60 MHz 1

60 MHz < Freq ≤ 90 MHz 2

90 MHz < Freq ≤ 120 MHz 3

120 MHz < Freq ≤ 150 MHz 4

150 MHz < Freq ≤ 180 MHz 5

180 MHz < Freq ≤ 210 MHz 6

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 52 / 120
NXP Semiconductors
Analog modules

Table 36. Flash Read Wait State Settings (S32K396, S32K394, S32K376, S32K374, S32K366 and S32K364 )
(continued)

Flash Frequency RWSC setting

210 MHz < Freq ≤ 240 MHz 7

240 MHz < Freq ≤ 250 MHz 8

13 Analog modules

13.1 SAR_ADC
All below specs are applicable only when one ADC instance is in operation and averaging is used or multiple ADC instances are
operational at the same time but sampling different channels. Best performance can be achieved if only one ADC is operational
at a time sampling one channel

Table 37. SAR_ADC

Symbol Description Min Typ Max Unit Condition Spec

Number

VDD_HV_A ADC Supply 2.97 — 5.5 V — —

Voltage 1

DVREFL VSS / VREFL -100 — 100 mV — —

Voltage Difference 2

VAD_INPUT ADC Input Voltage 3 VREFL — VREFH V — —

fAD_CK ADC Clock 10 — 80 MHz — —

Frequency

tSAMPLE ADC Input Sampling 275 — — ns — —

Time

tCONV ADC Total 1 — — us 12-bit result —

Conversion Time

tCONV ADC Total 0.9 — — us 10-bit result —

Conversion Time

CAD_INPUT ADC Input — — 13.8 pF ADC component —

Capacitance plus pad capacitance
(~2pF)

RAD_INPUT ADC Input — — 4.6 KΩ ADC + mux+SOC —

Resistance routing

RS Source Impedance, — 20 — Ω — —
precision channels

RS Source Impedance, — 20 — Ω — —
standard channels

TUE ADC Total — +/-4 +/-6 LSB without adjacent pin —

Unadjusted Error 4,5 current injection

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 53 / 120
NXP Semiconductors
Analog modules

Table 37. SAR_ADC (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

TUE ADC Total — +/-4 +/-8 LSB with up to +/-3mA —

Unadjusted Error 5 of current injection on
adjacent pins

IAD_REF Current — — 200 uA Per ADC for dedicated —

Consumption on or shared reference
ADC Reference pin, pins
VREFH.

IDDA Current — 2.1 — mA Current consumption —

Consumption on per ADC module, ADC
ADC Supply, enabled and converting
VDD_HV_A

CS Sampling 6.4 7.36 8.32 pF all channels —

Capacitance (gain=0) (gain=0) (gain=0)
9.72 11.12 12.52
pF(gain= pF(gain= (gain=ma
max) max) x)

RAD Sampling Switch 80 170 520 Ohm all channels —

Impedance

CP1 Pin capacitance 1.42 — 5.30 pF all channels —

CP1 Pin capacitance 1.42 — 4.38 pF Precision channels —

CP1 Pin capacitance 1.61 — 5.30 pF Standard channels —

1. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for reference supply design for
SAR ADC.
2. VSS and VREFL should be shorted on PCB. 100mV difference between VSS and VREFL is for transient only (not for DC).
3. This is ADC Input range for ADC accuracy guaranteed in this input range only. For SoC Pin capability, see Operation Condition Section.
4. Spec valid if potential difference between VDD_HV_A and VREFH should follow VDD_HV_A +0.1V >=VREFH >= VDD_HV_A -1.5V
5. TUE spec for precision and standard channels is based on 12-bit level resolution.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 54 / 120
NXP Semiconductors
Analog modules

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

VDD_HV_A
Channel
Selection Sampling
Source Filter Current Limiter

RS RF RL RSW1 RAD

VA CF CP1 CP2 CS

RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL Current Limiter Resistance
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions: CP1, CP2)
CS Sampling Capacitance

Figure 17. SAR ADC Input Circuit

13.2 Sigma Delta Analog to Digital Converter

Table 38. Sigma Delta Analog to Digital Converter

Symbol Description Min Typ Max Unit Condition Spec

Number

VINSE Peak-to-peak input — VREFP/ — V Negative input set to 0 —

voltage range, GAIN
Single-ended

VINSE Peak-to-peak input — +/- — V Negative input set to —

voltage range, VREFP/2 AVDD/2; GAIN=1
Single-ended

VINSE Peak-to-peak input — +/- — V Negative input set to —

voltage range, VREFP/ AVDD/2; GAIN=2, 4, 8,
Single-ended GAIN 16

VINDIFF Peak-to-peak input — +/- — V — —

voltage range, (VREFP-
differential VREFN)/
GAIN

AVDD Analog power supply 4.5 5.0 5.5 V — —

DVDD Digital power supply 0.99 1.1 1.21 V — —

VREFP External reference AVDD - AVDD AVDD + V — —

positive voltage 0.025 0.025

VREFN External reference — 0 — V — —

negative voltage

CMRR Common mode 34 — — dB — —

rejection ratio

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 55 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

R_AAF Anti aliasing filter — 5 20 kOhm — —

- external series
resistance

C_AAF Anti aliasing filter - 180 220 — pF — —

filter capacitance

CS Modulator sampling — — 75 * fF Gain = 1, 2, 4, 8 After —

capacitor GAIN input mux switch

GAIN PGA Gain 1 1 — 16 - — —

RES SDADC resolution — 16 — bits — —

Fm Input clock — 40 44 MHz — —

frequency

Fs Modulator sampling 20 40 — MHz — —

frequency 2

Fd Decimated output 31.25 — 333 kHz — —

conversion
frequency

OSR_EXT Oversampling ratio — 128 — - — —

for external
modulator

OFFSET_ERR Input referred offset — — 10 mV After calibration —

voltage error 3,4

GAIN_ERR Absolute gain — — 10 mV After calibration —

error 3,5

&RIPPLE Passband ripple -1 — 1 % From 10Hz to 0.33*Fd. —

Applicable with NXP
default FIR filter.

SB_ATTEN Stop band 40 — — dB From 0.5Fd to 1.0Fd. —

attenuation Applicable with NXP
default FIR filter.

SB_ATTEN Stop band 45 — — dB From 1.0Fd to 1.5Fd. —

attenuation Applicable with NXP
default FIR filter.

SB_ATTEN Stop band 50 — — dB From 1.5Fd to 2.0Fd. —

attenuation Applicable with NXP
default FIR filter.

SB_ATTEN Stop band 55 — — dB From 2.0Fd to 2.5Fd. —

attenuation Applicable with NXP
default FIR filter.

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 56 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

SB_ATTEN Stop band 60 — — dB From 2.5*Fd to Fs / —

attenuation 2. Applicable with NXP
default FIR filter.

&GROUP Group delay 44.5 — 719.5 1 / Fs Applicable with NXP —

OSR=120 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 37 — 612 1 / Fs Applicable with NXP —

OSR=125 320ksps special case
FIR filter. Min = CIC
filter delay only Max =
CIC + FIR filter delay
Assumes DSP S/W
maintains the periodic
output rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 52 — 839.5 1 / Fs Applicable with NXP —

OSR=140 default FIR filter.
Assumes DSP S/W
maintains the periodic
output rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 59.5 — 959.5 1 / Fs Applicable with NXP —

OSR=160 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 67 — 1079.5 1 / Fs Applicable with NXP —

OSR=180 default FIR filter. Min

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 57 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

= CIC filter delay only

Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 74.5 — 1199.5 1 / Fs Applicable with NXP —

OSR=200 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 82 — 1319.5 1 / Fs Applicable with NXP —

OSR=220 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 89.5 — 1439.5 1 / Fs Applicable with NXP —

OSR=240 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 104.5 — 1679.5 1 / Fs Applicable with NXP —

OSR=280 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 58 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

DSP S/W maintains

the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 119.5 — 1919.5 1 / Fs Applicable with NXP —

OSR=320 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 134.5 — 2159.5 1 / Fs Applicable with NXP —

OSR=360 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 149.5 — 2399.5 1 / Fs Applicable with NXP —

OSR=400 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 164.5 — 2639.5 1 / Fs Applicable with NXP —

OSR=440 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 59 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

given data transfer to

memory delays and
CPU processing.

&GROUP Group delay 179.5 — 2879.5 1 / Fs Applicable with NXP —

OSR=480 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 209.5 — 3359.5 1 / Fs Applicable with NXP —

OSR=560 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 239.5 — 3839.5 1 / Fs Applicable with NXP —

OSR=640 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 269.5 — 4319.5 1 / Fs Applicable with NXP —

OSR=720 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 60 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

&GROUP Group delay 299.5 — 4799.5 1 / Fs Applicable with NXP —

OSR=800 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 329.5 — 5279.5 1 / Fs Applicable with NXP —

OSR=880 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 359.5 — 5759.5 1 / Fs Applicable with NXP —

OSR=960 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 419.5 — 6719.5 1 / Fs Applicable with NXP —

OSR=1120 default FIR filter. Min
= CIC filter delay only
Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

&GROUP Group delay 479.5 — 7679.5 1 / Fs Applicable with NXP —

OSR=1280 default FIR filter. Min

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 61 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

= CIC filter delay only

Max = CIC + FIR
filter delay Assumes
DSP S/W maintains
the periodic output
rate of the ADC
given data transfer to
memory delays and
CPU processing.

tLATENCY Latency between — — &GROU — Does not apply to mux —

input data and P change.
converted output
data

tSETTLING Output settling time — — 2* — — —

after input mux &GROU
change P+2*
(1 / Fd)

tODRECOVERY Overdrive recovery — — 2* — — —

time &GROU
P

tSTARTUP Start up time from — — 100 us — —

power down

IDDA_SDADC VDDA supply current — 0.1 40 uA per SDADC - powered —

- ADC OFF

IDDA_BIAS_GEN VDDA supply current — 0.008 8 uA BIASGEN- powered —

- Bias Generator OFF

IVREF_ADC VREF current - ADC -0.85 -0.47 2.85 uA per SDADC - powered —
ON with differential
input mode

IVREF_ADC VREF current - ADC -0.7 0.007 0.7 uA per SDADC - powered —
OFF

IVREF_BIAS VREF current - Bias 21 21.4 25 uA BIASGEN- Powered —

Generator ON

IVREF_BIAS VREF current - Bias — 0.001 1.1 uA BIASGEN- Powered —

Generator OFF

IDD_SDADC VDD supply current - — 17 38 uA ADC powered ON —

ADC

IDD_SDADC VDD supply current - — 5 28 uA ADC powered OFF —

ADC

IDD_BIAS_GEN VDD supply current - — 4.3 6.1 uA ADC powered ON —

Bias Generator

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 62 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

IDD_BIAS_GEN VDD supply current - — 0.43 6 uA ADC powered OFF —

Bias Generator

ZDIFF Differential input 215 317 380 kOhm Fs = 40MHz —

impedance, Gain = 1

ZDIFF Differential input 130 230 276 kOhm Fs = 40MHz —

impedance, Gain = 2

ZDIFF Differential input 75 159 191 kOhm Fs = 40MHz —

impedance, Gain = 4

ZDIFF Differential input 40 103 124 kOhm Fs = 40MHz —

impedance, Gain = 8

ZDIFF Differential input 40 103 124 kOhm Fs = 40MHz —

impedance, Gain =
16

ZDIFF_20M Differential input 430 634 760 kOhm Fs=20 MHz —

impedance
GAIN=1 6

ZDIFF_20M Differential input 260 460 552 kOhm Fs=20 MHz —

impedance
GAIN=2 6

ZDIFF_20M Differential input 150 320 382 kOhm Fs=20 MHz —

impedance
GAIN=4 6

ZDIFF_20M Differential input 80 206 248 kOhm Fs=20 MHz —

impedance
GAIN=8 6

ZDIFF_20M Differential input 80 206 248 kOhm Fs=20 MHz —

impedance
GAIN=16 6

ZCM Common mode input 200 244 320 kOhm Fs = 40MHz —

impedance, Gain = 1

ZCM Common mode input 120 148 192 kOhm Fs = 40MHz —

impedance, Gain = 2

ZCM Common mode input 65 90 106 kOhm Fs = 40MHz —

impedance, Gain = 4

ZCM Common mode input 35 48 58 kOhm Fs = 40MHz —

impedance, Gain = 8

ZCM Common mode input 35 48 58 kOhm Fs = 40MHz —

impedance, Gain
=16

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 63 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

ZCM_20M Common mode 400 488 640 kOhm Fs=20 MHz —

input impedance
GAIN=1 6

ZCM_20M Common mode 240 296 384 kOhm Fs=20 MHz —

input impedance
GAIN=2 6

ZCM_20M Common mode 130 180 212 kOhm Fs=20 MHz —

input impedance
GAIN=4 6

ZCM_20M Common mode 70 96 116 kOhm Fs=20 MHz —

input impedance
GAIN=8 6

ZCM_20M Common mode 70 96 116 kOhm Fs=20 MHz —

input impedance
GAIN=16 6

OSR_INT Oversampling ratio 120 — 1280 - Fs=40 MHz —

for internal
modulator

OSR_INT_20M Oversampling ratio 60 — 640 — Fs=20 MHz —

for internal
modulator 6

SNRDIFF167 Signal to Noise 79 — — dB Fs=40 MHz, Output —

Ratio GAIN=1, rate = 166.7ksps, full-
Differential 7 scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SNRDIFF167 Signal to Noise 77 — — dB Fs=40 MHz, Output —

Ratio GAIN=2, rate = 166.7ksps, full-
Differential 7 scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SNRDIFF167 Signal to Noise 74 — — dB Fs=40 MHz, Output —

Ratio GAIN=4, rate = 166.7ksps, full-
Differential 7 scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 64 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

SNRDIFF167 Signal to Noise 71 — — dB Fs=40 MHz, Output —

Ratio GAIN=8, rate = 166.7ksps, full-
Differential 7 scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SNRDIFF167 Signal to Noise 68 — — dB Fs=40 MHz, Output —

Ratio GAIN=16, rate = 166.7ksps, full-
Differential 7 scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SNRDIFF167_20M Signal to Noise 76 — — dB Fs=20MHz, Output —

Ratio GAIN=1, rate = 166.7ksps, full-
Differential 6 scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SNRDIFF167_20M Signal to Noise 75 — — dB Fs=20MHz, Output —

Ratio GAIN=2, rate = 166.7ksps, full-
Differential 6 scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SNRDIFF167_20M Signal to Noise 74 — — dB Fs=20MHz, Output —

Ratio GAIN=4, rate = 166.7ksps, full-
Differential 6 scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SNRDIFF167_20M Signal to Noise 71 — — dB Fs=20MHz, Output —

Ratio GAIN=8, rate = 166.7ksps, full-
Differential 6 scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SNRDIFF167_20M Signal to Noise 66 — — dB Fs=20MHz, Output —

Ratio GAIN=16, rate = 166.7ksps, full-
Differential 6 scale 10kHz input,

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 65 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SINADDIFF167 Signal to Noise 72 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 166.7ksps, full-
Gain=1, Differential scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SINADDIFF167 Signal to Noise 69 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 166.7ksps, full-
Gain=2, Differential scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SINADDIFF167 Signal to Noise 66 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 166.7ksps, full-
Gain=4, Differential scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SINADDIFF167 Signal to Noise 63 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 166.7ksps, full-
Gain=8, Differential scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SINADDIFF167 Signal to Noise 60 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 166.7ksps, full-
Gain=16, Differential scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter.

SINADDIF167_ Signal to Noise 72 — — dB Fs=20MHz, Output —

20M Ratio and Distortion rate = 166.7ksps, full-
Gain=1, Differential 6 scale 10kHz input,
integration bandwidth
up to 55.6kHz.

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 66 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

Applicable with NXP

default FIR filter

SINADDIF167_ Signal to Noise 69 — — dB Fs=20MHz, Output —

20M Ratio and Distortion rate = 166.7ksps, full-
Gain=2, Differential 6 scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter

SINADDIF167_ Signal to Noise 66 — — dB Fs=20MHz, Output —

20M Ratio and Distortion rate = 166.7ksps, full-
Gain=4, Differential 6 scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter

SINADDIF167_ Signal to Noise 63 — — dB Fs=20MHz, Output —

20M Ratio and Distortion rate = 166.7ksps, full-
Gain=8, Differential 6 scale 10kHz input,
integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter

SINADDIF167_ Signal to Noise 60 — — dB Fs=20MHz, Output —

20M Ratio and rate = 166.7ksps, full-
Distortion Gain=16, scale 10kHz input,
Differential 6 integration bandwidth
up to 55.6kHz.
Applicable with NXP
default FIR filter

SNRSE333 Signal to Noise 68 — — dB Fs=40 MHz, Output —

Ratio GAIN=1, rate = 320/333ksps,
Single-ended 7 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SNRSE333 Signal to Noise 65 — — dB Fs=40 MHz, Output —

Ratio GAIN=2, rate = 320/333ksps,
Single-ended 7 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 67 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

SNRSE333 Signal to Noise 62 — — dB Fs=40 MHz, Output —

Ratio GAIN=4, rate = 320/333ksps,
Single-ended 7 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SNRSE333 Signal to Noise 59 — — dB Fs=40 MHz, Output —

Ratio GAIN=8, rate = 320/333ksps,
Single-ended 7 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SNRSE333 Signal to Noise 56 — — dB Fs=40 MHz, Output —

Ratio GAIN=16, rate = 320/333ksps,
Single-ended 7 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SNRSE333_20M Signal to Noise 61 — — dB Fs=20MHz, Output rate —

Ratio GAIN=1, = 320/333ksps, full-
Single-ended 6 scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter

SNRSE333_20M Signal to Noise 60 — — dB Fs=20MHz, Output rate —

Ratio GAIN=2, = 320/333ksps, full-
Single-ended 6 scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter

SNRSE333_20M Signal to Noise 59 — — dB Fs=20MHz, Output rate —

Ratio GAIN=4, = 320/333ksps, full-
Single-ended 6 scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter

SNRSE333_20M Signal to Noise 56 — — dB Fs=20MHz, Output rate —

Ratio GAIN=8, = 320/333ksps, full-
Single-ended 6 scale 20kHz input,

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 68 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter

SNRSE333_20M Signal to Noise 50 — — dB Fs=20MHz, Output rate —

Ratio GAIN=16, = 320/333ksps, full-
Single-ended 6 scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter

SINADSE333 Signal to Noise 60 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 320/333ksps,
Gain=1, Single- full-scale 20kHz input,
ended integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SINADSE333 Signal to Noise 57 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 320/333ksps,
Gain=2, Single- full-scale 20kHz input,
ended integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SINADSE333 Signal to Noise 54 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 320/333ksps,
Gain=4, Single- full-scale 20kHz input,
ended integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SINADSE333 Signal to Noise 51 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 320/333ksps,
Gain=8, Single- full-scale 20kHz input,
ended integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SINADSE333 Signal to Noise 48 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 320/333ksps,
Gain=16, Single- full-scale 20kHz input,
ended integration bandwidth
up to 80/83.3kHz.

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 69 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

Applicable with NXP

default FIR filter.

SINADSE333_20M Signal to Noise 59 — — dB Fs=20MHz, Output rate —

Ratio and Distortion = 320/333ksps, full-
Gain=1, Differential 6 scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter

SINADSE333_20M Signal to Noise 57 — — dB Fs=20MHz, Output rate —

Ratio and Distortion = 320/333ksps, full-
Gain=2, Differential 6 scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter

SINADSE333_20M Signal to Noise Ratio 54 — — dB Fs=20MHz, Output rate —

and = 320/333ksps, full-
Distortion Gain=4, Di scale 20kHz input,
fferential 6 integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter

SINADSE333_20M Signal to Noise 51 — — dB Fs=20MHz, Output rate —

Ratio and Distortion = 320/333ksps, full-
Gain=8, Differential 6 scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter

SINADSE333_20M Signal to Noise 48 — — dB Fs=20MHz, Output rate —

Ratio and = 320/333ksps, full-
Distortion Gain=16, scale 20kHz input,
Differential 6 integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter

SNRDIFF333 Signal to Noise 74 — — dB Fs=40 MHz, Output —

Ratio GAIN=1, rate = 320ksps/
Differential 7 333ksps, full-scale
20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 70 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

SNRDIFF333 Signal to Noise 71 — — dB Fs=40 MHz, Output —

Ratio GAIN=2, rate = 320ksps/
Differential 7 333ksps, full-scale
20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SNRDIFF333 Signal to Noise 68 — — dB Fs=40 MHz, Output —

Ratio GAIN=4, rate = 320ksps/
Differential 7 333ksps, full-scale
20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SNRDIFF333 Signal to Noise 65 — — dB Fs=40 MHz, Output —

Ratio GAIN=8, rate = 320ksps/
Differential 7 333ksps, full-scale
20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SNRDIFF333 Signal to Noise 62 — — dB Fs=40 MHz, Output —

Ratio GAIN=16, rate = 320ksps/
Differential 7 333ksps, full-scale
20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SNRDIFF333_20M Signal to Noise 67 — — dB Fs=20MHz, Output rate —

Ratio GAIN=1, = 320ksps/333ksps,
Differential 6 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SNRDIFF333_20M Signal to Noise 67 — — dB Fs=20MHz, Output rate —

Ratio GAIN=2, = 320ksps/333ksps,
Differential 6 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 71 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

SNRDIFF333_20M Signal to Noise 67 — — dB Fs=20MHz, Output rate —

Ratio GAIN=4, = 320ksps/333ksps,
Differential 6 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SNRDIFF333_20M Signal to Noise 65 — — dB Fs=20MHz, Output rate —

Ratio GAIN=8, = 320ksps/333ksps,
Differential 6 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SNRDIFF333_20M Signal to Noise 60 — — dB Fs=20MHz, Output rate —

Ratio GAIN=16, = 320ksps/333ksps,
Differential 6 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SINADDIFF333 Signal to Noise 66 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 320ksps/
Gain=1, Differential 333ksps, full-scale
20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SINADDIFF333 Signal to Noise 63 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 320ksps/
Gain=2, Differential 333ksps, full-scale
20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SINADDIFF333 Signal to Noise 60 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 320ksps/
Gain=4, Differential 333ksps, full-scale
20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 72 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

SINADDIFF333 Signal to Noise 57 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 320ksps/
Gain=8, Differential 333ksps, full-scale
20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SINADDIFF333 Signal to Noise 54 — — dB Fs=40 MHz, Output —

Ratio and Distortion rate = 320ksps/
Gain=16, Differential 333ksps, full-scale
20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SINADDIFF333_ Signal to Noise 66 — — dB Fs=20MHz, Output rate —

20M Ratio and Distortion = 320ksps/333ksps,
Gain=1, Differential 6 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SINADDIFF333_ Signal to Noise 63 — — dB Fs=20MHz, Output rate —

20M Ratio and Distortion = 320ksps/333ksps,
Gain=2, Differential 6 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SINADDIFF333_ Signal to Noise 60 — — dB Fs=20MHz, Output rate —

20M Ratio and Distortion = 320ksps/333ksps,
Gain=4, Differential 6 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

SINADDIFF333_ Signal to Noise 57 — — dB Fs=20MHz, Output rate —

20M Ratio and Distortion = 320ksps/333ksps,
Gain=8, Differential 6 full-scale 20kHz input,
integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 73 / 120
NXP Semiconductors
Analog modules

Table 38. Sigma Delta Analog to Digital Converter (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

SINADDIFF333_ Signal to Noise 54 — — dB Fs=20MHz, Output rate —

20M Ratio and = 320ksps/333ksps,
Distortion Gain=16, full-scale 20kHz input,
Differential 6 integration bandwidth
up to 80/83.3kHz.
Applicable with NXP
default FIR filter.

IDDA_SDADC_ VDDA supply current — 10.5 13.2 mA Fs=40MHz, 1 SDADC —

BIASGEN - 1 ADC+BIASGEN + BIASGEN - powered
ON

IDDA_SDADC_ VDDA supply current — 9.1 11.2 mA Fs=20MHz, 1 SDADC —

BIASGEN_20M - 1 ADC+BIASGEN 6 + BIASGEN - powered
ON

IDDA_SDADC VDDA supply current — 5.4 6.4 mA Fs=40MHz, per —

- 1 ADC SDADC -powered ON

IDDA_SDADC_ VDDA supply current — 4.3 5 mA Fs=20MHz, per —

20M - 1 ADC 6 SDADC- powered ON

1. When using a GAIN setting of 16, the conversion result will always have a value of zero in the least significant bit. The
gives an effective resolution of 15 bits.
2. Fs=40MHz is preferred mode except for applications requiring high input impedance. Fs=20MHz mode provides higher
input impedance while trading off few other specs, which are specified with condition Fs=20MHz and suffix _20M added
to thier symbol names.
3. Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the dev
4. Conversion offset error must be divided by the applied gain factor (1, 2, 4, 8, or 16) to obtain the actual input referred offset
error.
5. Calibration of gain is possible when gain = 1. Offset Calibration should be done with respect to 0.5*VDD_HV_SDADC for
differential mode and single ended mode with negative input=0.5*VDD_HV_SDADC. Offset Calibration should be done
with respect to 0 for "single ended mode with negative input=0". Both offset and Gain Calibration is guaranteed for ±5%
variation of VDD_HV_SDADC, ±10% variation of VDD_HV_SDADC, and ± 50 °C temperature variation
6. Applicable for half sampling rate mode(Fs=20MHz).
7. Guaranteed only when input signal is between VREFP-0.15 and VREFN+0.15. Parameter observed should be normalized
to full scale.

13.3 Low Power Comparator (LPCMP)

Table 39. Low Power Comparator (LPCMP)

Symbol Description Min Typ Max Unit Condition Spec

Number

idda(IDHSS) vdda Supply — 240 — uA — —

Current, High Speed
Mode 1,2

idda(IDLSS) vdda Supply — 17 — uA — —

Current, Low Speed
Mode 1,2

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 74 / 120
NXP Semiconductors
Analog modules

Hysteresis, Low
Speed mode

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 75 / 120
NXP Semiconductors
Analog modules

Table 39. Low Power Comparator (LPCMP) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

VAHYST1 Analog Comparator — 8 60 mV HYSTCTR[1:0]= 2'b01 —

Hysteresis, Low
Speed mode

VAHYST2 Analog Comparator — 15 113 mV HYSTCTR[1:0]= 2'b10 —

Hysteresis, Low
Speed mode

VAHYST3 Analog Comparator — 23 165 mV HYSTCTR[1:0]= 2'b11 —

Hysteresis, Low
Speed mode

INL DAC integral -1 — 1 LSB vrefh_cmp = vdda, —

linearity 2,6,7 vrefl_cmp = vss

INL DAC integral -1.5 — 1.5 LSB vrefh_cmp < vdda —

linearity 2,6,7

DNL DAC differential -1 — 1 LSB vrefh_cmp = vdda, —

linearity 2,6 vrefl_cmp = vss

DNL DAC differential -1.5 — 1.5 LSB vrefh_cmp < vdda —

linearity 2,6

tDDAC DAC — — 30 us — —
Initialization time

VAIN Analog input voltage 0 — VDDA V — —

1. Difference at input > 200mV

2. vdda is comparator HV supply and internally shorted to VDD_HV_A pin. vss is comparator ground
3. Applied +/- (100 mV + VAHYST0/1/2/3 + max. of VAIO) around switch point
4. Applied +/- (30 mV + VAHYST0/1/2/3 + max. of VAIO) around switch point
5. Applied ± (100 mV + VAHYST0/1/2/3 ).
6. 1 LSB = (vrefh_cmp - vrefl_cmp) /256. vrefh_cmp and vrefl_cmp are comparator reference high and low
7. Calculation method used: Linear Regression Least Square Method

LPCMP0 channels must only be selected/enabled when VDD_HV_A >= VDD_HV_B. These channels must be disabled when
VDD_HV_A goes below VDD_HV_B.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 76 / 120
NXP Semiconductors
Analog modules

Hysteresis
(mV)
60

0
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 Vin level (V)
25 Junction Temp (°C)
3.3 VDD_HV_A (V)
HYSTCTR setting
00 01 10 11

Figure 18. Typical Hysteresis vs Vin level (VDD_HV_A = 3.3 V, High Speed Mode)

Hysteresis
(mV)

0
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 Vin level (V)
25 Junction Temp (°C)
3.3 VDD_HV_A (V)
HYSTCTR setting
00 01 10 11

Figure 19. Typical Hysteresis vs Vin level (VDD_HV_A = 3.3 V, Low Speed Mode)

Hysteresis
(mV)
60

0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Vin level (V)
25 Junction Temp (°C)
5 VDD_HV_A (V)
HYSTCTR setting
00 01 10 11

Figure 20. Typical Hysteresis vs Vin level (VDD_HV_A = 5 V, High Speed Mode).png

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 77 / 120
NXP Semiconductors
Analog modules

Hysteresis
(mV)

0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Vin level (V)
25 Junction Temp (°C)
5 VDD_HV_A (V)
HYSTCTR setting
00 01 10 11

Figure 21. Typical Hysteresis vs Vin level (VDD_HV_A = 5 V, Low Speed Mode).png

13.4 Sine wave generator

Table 40. Sine wave generator

Symbol Description Min Typ Max Unit Condition Spec

Number

INPUT_CLK Input clock 12 16 20 MHz — —

APP Sine wave 0.394 — 2.302 V — —

amplitude 1

MAXAPP Maximum amplitude 1.884 2.093 2.302 V — —

(pk-pk) 2

MINAPP Minimum amplitude 0.394 0.438 0.482 V — —

(pk-pk) 2

AV Amplitude -10 — 10 % — —
Variation 3

CV Common voltage 4 — 1.3 — V — —

CVV Common voltage -6 — 6 % — —

variation

SINAD Signal to noise ratio 30 45 — dB — —

plus distortion 5

FREQ Frequency range of 1 — 50 kHz — —

the sine wave

FRP Frequency precision -5 — 5 % — —

of the sine wave
(peak to peak
variation)

Cload Load capacitance 25 — 100 pF — —

Resd ESD Pad 149 213 277 ohm — —

Resistance 6

Iout Output current 0 — 100 uA — —

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 78 / 120
NXP Semiconductors
Analog modules

1. Peak to peak value is measured with no R or I load and its range is for room temperature
2. Peak-to-peak value is measured with no R or I load
3. Peak to peak excludes noise, SINAD must be considered.
4. Common mode value is measured with no R or I load
5. SINAD is measured at Max Peak-to-Peak voltage. SINAD may not be met with FIRC clock source.
6. Internal device routing resistance. ESD pad resistance is in series and must be considered for Max peak to peak voltages,
depending on application I load and/or R load

13.5 Supply Diagnosis

The table below gives the specification for the on die supply diagnosis.

Table 41. Supply Diagnosis

Symbol Description Min Typ Max Unit Condition Spec

Number

AN_ACC Offset to internally -5 0 5 % — —

monitored supply at
ADC input 1,2,3

AN_T_on Switching time from — 2.5 12 ns — —

closed (OFF) to
conducting (ON) 1

AN_TADCSA Required ADC 1.2 — — µs — —

sampling time 2

1. These specs will have degraded performance when used in extended supply voltage operation range, i.e. normal supply
voltage range specification is exceeded.
2. Required ADC sampling time specified by parameter AN_TADCSA needs to be used at the ADC conversion to guarantee
the specified accuracy. A smaller sampling time leads to a less accurate result.
3. If V15 > VDD_HV_A +100mV then the V15 measurement via anamux may be imprecise.

13.6 Temperature Sensor

The table below gives the specification for the MCU on-die temperature sensor.

Table 42. Temperature Sensor

Symbol Description Min Typ Max Unit Condition Spec

Number

TS_TJ Junction -40 — 150 °C — —

temperature
monitoring range

TS_IV25 ON state current — 400 — µA ETS_EN=1 —

consumption on V25

TS_ACC1 Temperature output -5 0 +5 °C 100 °C < Tj <= 150 °C —

error at circuit output
(Voltage) 1,2,3

TS_ACC2 Temperature output -10 0 +10 °C -40 °C <= Tj <=100 °C —

error at circuit output
(Voltage) 1,2,3

TS_TSTART Circuit start up time — 4 30 µs — —

TS_TADCSA Required ADC 1.2 — — µs — —

sampling time 1

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 79 / 120
NXP Semiconductors
Clocking modules

1. Required ADC sampling time specified by parameter TS_TADCSA needs to be used at the ADC conversion to guarantee
the specified accuracy. A smaller sampling time leads to a less accurate result.
2. Note: The temperature sensor measures the junction temperature Tj at the location where it is placed on die. The local Tj
is modulated by current and previous active state of the circuit elements on die.
3. The error caused by ADC conversion and provided temperature calculation formula is not included.

14 Clocking modules

14.1 Fast External Oscillator (FXOSC)

Table 43. Fast External Oscillator (FXOSC)

Symbol Description Min Typ Max Unit Condition Spec

Number

FREQ_BYPASS Input clock — — 50 MHz — —

frequency in bypass
mode 1

TRF_BYPASS Input clock rise/fall — — 5 ns — —

time in bypass
mode 1

CLKIN_DUTY_ Input clock duty 47.5 — 52.5 % — —

BYPASS cycle in bypass
mode 1

FXOSC_CLK output clock 8 — 40 MHz — —

frequency in crystal
mode

TFXOSC Fxosc start up — — 2 ms — —

time (ALC enabled) 2

IFXOSC Oscillator Analog — — 1 mA using 8, 16 or 40 MHz —

circuit supply crystal
current, V25 supply
(ALC enable)

IFXOSC Oscillator Analog — — 2.7 mA using 8, 16 or 40 MHz —

circuit supply crystal
current, V25 supply
(ALC disabled)

EXTAL_SWING_ Peak-to-peak 0.3 — 1.4 V — —

PP voltage swing on
EXTAL pin in crystal
oscillator mode (ALC
enabled)

EXTAL_SWING_ Peak-to-peak 1.2 — 2.75 V — —

PP voltage swing on
EXTAL pin in crystal
oscillator mode (ALC
disabled) 3

CLKIN_VIL_ Input clock low level 0 — vref-0.5 V vref=0.5*VDD_HV_A —

EXTAL_BYPASS in bypass mode

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S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 80 / 120
NXP Semiconductors
Clocking modules

Table 43. Fast External Oscillator (FXOSC) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

CLKIN_VIH_ Input clock high level vref+0.5 — VDD_HV V vref=0.5*VDD_HV_A —

EXTAL_BYPASS in bypass mode _A

VSB Self Bias Voltage 350 — 850 mV — —

GM Amplifier 9.7 — 18.5 mA/V GM_SEL[3:0] = —

Transconductance 4`b1111

1. For bypass mode applications, the EXTAL pin should be driven low when FXOSC is in off/disabled state.
2. The startup time specification is valid only when the recommended crystal and load capacitors are used. For higher load
capacitances, the actual startup time might be higher.
3. The recommended gm setting to ensure extal swing < 2.75V at 8MHz in ALC-disabled mode is gm=4'b0010.
Recommended gm settings in ALC-disabled mode for all other supported frequencies and crystals remain the same.

To ensure stable oscillations, FXOSC incorporates the feedback resistance internally.

Drive level is a crystal specification and if crystal load capacitance is increased beyond the recommended value, it may violate
the crystal drive level rating. In such cases, contact NXP sales representative for selecting the correct crystal.

Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as:
gm_crit = 4 * (ESR + RS) * (2πF)2 * (C0 + CL)2

where:
• gmXOSC is the transconductance of the internal oscillator circuit
• ESR is the equivalent series resistance of the external crystal
• RS is the series resistance connected between XTAL pin and external crystal for current limitation
• F is the external crystal oscillation frequency
• C0 is the shunt capacitance of the external crystal
• CL is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)]
• Cs is stray or parasitic capacitance on the pin due to any PCB traces
• C1, C2 external load capacitances on EXTAL and XTAL pins
See manufacture datasheet for external crystal component values

Figure 22. Oscillation build-up equation

NOTE
To improve the FXOSC & PLL jitter performance, following pins(PTG0,PTG2,PTG3,PTG6,PTF29, PMOS_CTRL
in BGA289 package) cannot be toggling edge-aligned.

NOTE
For 176LQFP, To improve FXOSC jitter with SMPS ON use VDD_DCDC=3.3 V.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 81 / 120
NXP Semiconductors
Clocking modules

Figure 23. Block diagram

14.2 FIRC
Table 44. FIRC

Symbol Description Min Typ Max Unit Condition Spec

Number

fFIRC FIRC nominal — 48 — MHz — —

Frequency

FACC FIRC Frequency -5 — 5 % — —

deviation across
process, voltage,
and temperature
after trimming

TSTART Startup Time 1 — 10 25 us — —

1. Startup time is for reference only.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 82 / 120
NXP Semiconductors
Clocking modules

14.3 SIRC
Table 45. SIRC

Symbol Description Min Typ Max Unit Condition Spec

Number

fSIRC SIRC nominal — 32 — KHz — —

Frequency

fSIRC_ACC SIRC Frequency -10 — 10 % — —

deviation across
process, voltage,
and temperature
after trimming

TSIRC_start SIRC Startup Time 1 — — 3 ms — —

TSIRC_DC SIRC duty cycle 30 — 70 % — —

1. Startup time is for information only.

14.4 PLL
Jitter values specified in this table are applicable for FXOSC reference clock input only.

Table 46. PLL

Symbol Description Min Typ Max Unit Condition Spec

Number

FPLL_in PLL input frequency 8 — 40 MHz This is the frequency —

after the Reference
Divider within the PLL

FPLL_out PLL output 48 — 480 MHz — —

frequency
(PLL_PHIn_CLK)

FPLL_vcoRange VCO Frequency 640 — 960 MHz — —

range

FPLL_DS Modulation Depth -0.5 — -3 % — —

(down spread)

FPLL_FM Modulation — — 32 KHz — —

frequency

TPLL_start PLL lock time — — 1 ms — —

JPLL_cyc PLL period jitter (pk- — — 208 ps FPLL_out = 320MHz, —

pk) 1,2,3 Integer Mode

JPLL_cyc PLL period jitter (pk- — — 395 ps FPLL_out = 320MHz, —

pk) 1,2,3 Fractional Mode

JPLL_acc PLL accumulated — — 840 ps FPLL_out = 320MHz, —

jitter (pk-pk) 1,2,3 Integer Mode

JPLL_acc PLL accumulated — — 1680 ps FPLL_out = 320MHz, —

jitter (pk-pk) 1,2,3 Fractional Mode

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 83 / 120
NXP Semiconductors
Communication interfaces

jitter (pk-pk) 1,2,3 Integer Mode

JPLL_acc PLL accumulated — — 1680 ps FPLL_out = 120MHz, —

jitter (pk-pk) 1,2,3 Fractional Mode

1. For SSCG, jitter due to systematic modulation needs to be added as per applied modulation. Accumulated jitter
specification is not valid with SSCG
2. Jitter numbers are valid only at IP boundary and does not include any degradation due to IO pad for clock measurement.
3. Jitter numbers calculated by extrapolating RMS jitter numbers to +/- 7 sigma .

15 Communication interfaces

15.1 LPSPI

15.1.1 LPSPI
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many
of the transfer attributes are programmable. The following table provides timing characteristics for classic LPSPI timing modes.
1.All timing is shown with respect to 50% VDD_HV_A/B thresholds.
2. All measurements are with maximum output load of 30pF, input transition of 1 ns and pad configured DSE = 1, SRC = 0

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 84 / 120
NXP Semiconductors
Communication interfaces

Table 47. LPSPI

Symbol Description Min Typ Max Unit Condition Spec

Number

fperiph Peripheral Frequenc — — 40 MHz Master —

y 1,2,3

fperiph Peripheral Frequenc — — 40 MHz Slave —

y 1,2,3

fperiph Peripheral Frequenc — — 80 MHz Master Loopback —

y 1,3,4

fop Operating frequency — — 15 MHz Slave 1

fop Operating frequency — — 15 MHz Master 1

fop Operating — — 10 MHz Slave_10Mbps 1

frequency 5

fop Operating — — 10 MHz Master_10Mbps 1

frequency 5

fop Operating — — 20 MHz Master Loopback 1

frequency 4,6

tSPSCK SPSCK period 66 — — ns Slave 2

tSPSCK SPSCK period 66 — — ns Master 2

tSPSCK SPSCK period 4 50 — — ns Master Loopback 2

tSPSCK SPSCK period 100 — — ns Master_10Mbps 2

tSPSCK SPSCK period 100 — — ns Slave_10Mbps 2

tLEAD Enable lead time tSPCK/2 — — ns Slave 3

(PCS to SPSCK
delay) 7

tLEAD Enable lead time 30 — — ns Master 3

(PCS to SPSCK
delay) 7

tLEAD Enable lead time 30 — — ns Master Loopback 3

(PCS to SPSCK
delay) 4,7

tLAG Enable lag time tSPCK/2 — — ns Slave 4

(After SPSCK
delay) 8

tLAG Enable lag time 30 — — ns Master 4

(After SPSCK
delay) 8

tLAG Enable lag time 30 — — ns Master Loopback 4

(After SPSCK
delay) 4,8

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 85 / 120
NXP Semiconductors
Communication interfaces

Table 47. LPSPI (continued)

tA Slave access time — — 50 ns Slave 8

tDIS Slave MISO (SOUT) — — 50 ns Slave 9

disable time

tV Data valid (after — — 26 ns Slave 10

SPSCK edge) 10

tV Data valid (after — — 14 ns Master 10

SPSCK edge) 10

tV Data valid (after — — 41 ns Slave_10Mbps 10

SPSCK edge) 10

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 86 / 120
NXP Semiconductors
Communication interfaces

input 11

tRI/FI Rise/Fall time — — 1 ns Master -

input 11

tRI/FI Rise/Fall time — — 1 ns Master Loopback -

input 4,11

1. tperiph = 1/fperiph
2. For LPSPI0 instance, max. peripheral frequency is equal to AIPS_PLAT_CLK.
3. fperiph = LPSPI peripheral clock
4. Master Loopback mode: In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting
LPSPI_CFGR1[SAMPLE] bit as 1.
5. These specifications apply to the SPI operation, as master or slave, at up to 10 Mbps for the combinations not indicated
in the table below. Unless otherwise noted, all other ‘master’ and ‘slave’ specifications are also applicable in the 10Mbps
configurations. See table "LPSPI 20 MHz and 15 MHz Combinations.
6. LPSPI0 support up to 20MHz on fast pin.
7. Minimum configuration value for CCR[PCSSCK] field is 3(0x00000011).
8. Minimum configuration value for CCR[SCKPCS] field is 3(0x00000011).
9. While selecting odd dividers, ensure Duty Cycle is meeting this parameter.
10. Output rise/fall time is determined by the output load and GPIO pad drive strength setting. See the GPIO specifications for
detail.
11. The input rise/fall time specification applies to both clock and data, and is required to guarantee related timing parameters.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 87 / 120
NXP Semiconductors
Communication interfaces

SS
(INPUT)
2 4
3
SPSCK
(CPOL = 0)
(INPUT)
5 5
SPSCK
(CPOL = 1)
(INPUT)
10 11 9
MISO
SLAVE MSB OUT BIT 6 ... 1 SLAVE LSB OUT
(OUTPUT)
8 6 7
MOSI
MSB IN BIT 6 ... 1 LSB IN
(INPUT)

Figure 24. LPSPI Slave Mode Timing (CPHA=1)

SS
(INPUT)
2 4
3
SPSCK
(CPOL = 0)
(INPUT)
5 5
SPSCK
(CPOL = 1) 8` 9
(INPUT)
8 10 11 11
MISO
SLAVE MSB BIT 6 ... 1 SLAVE LSB OUT
(OUTPUT)
6 7
MOSI
MSB IN BIT 6 ... 1 LSB IN
(INPUT)

Figure 25. LPSPI Slave Mode Timing (CPHA=0)

SS1
(OUTPUT)
2 4
3
SPSCK
(CPOL = 0)
(OUTPUT)
5 5
SPSCK
(CPOL = 1)
(OUTPUT)
6 7
MISO
MSB IN2 BIT 6 ... 1 LSB IN
(INPUT)
10 11
MOSI
MSB OUT2 BIT 6 ... 1 LSB OUT
(OUTPUT)

Figure 26. LPSPI Master Mode Timing (CPHA=0)

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 88 / 120
NXP Semiconductors
Communication interfaces

SS1
(OUTPUT)
2 4
3
SPSCK
(CPOL = 0)
(OUTPUT)
5 5
SPSCK
(CPOL = 1)
(OUTPUT)
6 7
MISO
MSB IN2 BIT 6 ... 1 LSB IN
(INPUT)
10 11
MOSI
PORT DATA MASTER MSB OUT BIT 6 ... 1 MASTER LSB OUT PORT DATA
(OUTPUT)

Figure 27. LPSPI Master Mode Timing (CPHA=1)

15.1.2 LPSPI0 20 MHz and 15 MHz Combinations

NOTE
All measurements are with maximum output load of 25pF

Table 48. LPSPI0 20 MHz and 15 MHz Combinations

PORT PAD TYPE SPI Signal 20Mbps (In loopback 15 Mbps

mode only)

PTB1 GPIO-Slow LPSPI0_SOUT LPSPI0_SOUT

PTB0 GPIO-Slow LPSPI0_PCS0 LPSPI0_PCS0

PTC9 GPIO-Slow LPSPI0_SIN LPSPI0_SIN

PTC8 GPIO-Slow LPSPI0_SCK LPSPI0_SCK

PTD6 GPIO-Medium LPSPI0_PCS0 LPSPI0_PCS0

PTD5 GPIO-Medium LPSPI0_PCS1 LPSPI0_PCS1

PTD12 GPIO-FAST LPSPI0_SOUT LPSPI0_SOUT

PTD11 GPIO-FAST LPSPI0_SCK LPSPI0_SCK

PTD10 GPIO-FAST LPSPI0_SIN LPSPI0_SIN

NOTE
Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode.

15.1.3 LPSPI Pad Type

Timing is not supported for below combination of Clock (FAST) and DATA(Super-Slow)

Table 49. LPSPI Pad Type

SPI Clock Fast PadPort SPI Data Superslow Pad Port

LPSPI0_SCK PTD11 LPSPI0_SIN PTE0

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NXP Semiconductors
Communication interfaces

Table 49. LPSPI Pad Type (continued)

SPI Clock Fast PadPort SPI Data Superslow Pad Port

PTD16

LPSPI0_PCS0 PTA26

PTE4

LPSPI0_PCS4 PTD23

LPSPI0_PCS5 PTD24

LPSPI0_PCS6 PTD20

LPSPI0_PCS7 PTD21

LPSPI2_SCK PTB29 LPSPI2_SIN PTE16

PTF1

LPSPI2_SOUT PTA8

PTF2

LPSPI2_PCS0 PTA9

PTE11

PTF3

LPSPI2_PCS1 PTE10

LPSPI2_PCS2 PTA21

LPSPI2_PCS3 PTF26

PTE26

LPSPI3_SCK PTC17 LPSPI3_SIN PTE10

PTD20

PTF12

LPSPI3_SOUT PTD0

PTA17

PTF15

LPSPI3_PCS0 PTD17

PTB17

PTA9

PTF16

LPSPI3_PCS1 PTF18

PTA6

LPSPI3_PCS2 PTB13

PTF19

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 90 / 120
NXP Semiconductors
Communication interfaces

Table 49. LPSPI Pad Type (continued)

SPI Clock Fast PadPort SPI Data Superslow Pad Port

LPSPI3_PCS3 PTB12

PTF23

15.2 MDIO timing specifications

The following table describes the MDIO electrical characteristics. Measurements are with maximum output load of 25 pF, input
transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1 and SRE = 1’b0). I/O operating voltage ranges from
2.97 V to 3.63 V. MDIO pin must have external Pull-up.

Table 50. MDIO timing specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

— MDC clock — — 2.5 MHz — —

frequency

MDC1 MDC pulse width 40 — 60 %MDC — MDC1

high period

MDC2 MDC pulse width low 40 — 60 %MDC — MDC2

period

MDC5 MDC falling edge — — 25 ns — MDC5

to MDIO output
valid(maximum
propagation delay)

MDC6 MDC falling edge -10 — — ns — MDC6

to MDIO output
invalid(minimum
propagation delay)

MDC3 MDIO (input) to 28 — — ns — MDC3

MDC rising edge
setup time

MDC4 MDIO (input) to 0 — — ns — MDC4

MDC rising edge
hold time

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NXP Semiconductors
Communication interfaces

MDC1 MDC2

MDC (output)

MDC6

MDIO (output)

MDC5

MDIO (input)

MDC3 MDC4

Figure 28. MII/RMII serial management channel timing

15.3 Ethernet MII (10/100 Mbps)

The following timing specs are defined at the device I/O pin and must be translated appropriately to arrive at timing specs/
constraints for the physical interface. Measurements are with maximum output load of 25pF, input transition of 1ns and pad
configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V.

NOTE
QuadSPI cannot be used along with Ethernet in 176LQFP-EP.

Table 51. Ethernet MII (10/100 Mbps)

Symbol Description Min Typ Max Unit Condition Spec

Number

— RXCLK frequency — 2.5/25 — MHz 10/100 Mbps —

MII1 RXCLK pulse width 35 — 65 %RXCLK — —

high period

MII2 RXCLK pulse width 35 — 65 %RXCLK — —

low period

MII3 RXD[3:0], RXDV, 5 — — ns 10/100 Mbps —

RXER to RXCLK
setup

MII4 RXCLK to RXD[3:0], 5 — — ns 10/100 Mbps —

RXDV, RXER hold

tCYC_TX TXCLK frequency — 2.5 / 25 — MHz 10/100 Mbps —

MII5 TXCLK pulse width 35 — 65 %TXCLK — —

high period

MII6 TXCLK pulse 35 — 65 %TXCLK — —

width low period

MII7 TXCLK to TXD[3:0], 2 — — ns — —

TXEN, TXER invalid

MII8 TXCLK to TXD[3:0], — — 25 ns — —

TXEN, TXER valid

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NXP Semiconductors
Communication interfaces

Figure 29. MII receive diagram

Figure 30. MII transmit diagram

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NXP Semiconductors
Communication interfaces

15.4 Ethernet MII (200 Mbps)

NOTE
QuadSPI cannot be used along with Ethernet in 176LQFP-EP

Table 52. Ethernet MII (200 Mbps)

Symbol Description Min Typ Max Unit Condition Spec

Number

— RXCLK frequency — — 50 MHz — —

MII1 RXCLK pulse width 35 — 65 % — —

high RXCLK
period

MII2 RXCLK pulse width 35 — 65 % — —

low RXCLK
period

MII3 RXD[3:0], RXDV, 4 — — ns — —

RXER to RXCLK
setup time

MII4 RXCLK to RXD[3:0], 2 — — ns — —

RXDV, RXER hold
time

— TXCLK frequency — — 50 MHz — —

MII5 TXCLK pulse width 35 — 65 % — —

high TXCLK
period

MII6 TXCLK pulse width 35 — 65 % — —

low TXCLK
period

MII7 TXCLK to TXD[3:0], 2 — — ns — —

TXDV, TXER invalid

MII8 TXCLK to TXD[3:0], — — 15 ns — —

TXDV, TXER valid

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

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NXP Semiconductors
Communication interfaces

Figure 31. MII receive diagram

Figure 32. MII transmit diagram

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 95 / 120
NXP Semiconductors
Communication interfaces

15.5 Ethernet RMII (10/100 Mbps)

NOTE
QuadSPI cannot be used along with Ethernet in 176LQFP-EP

Table 53. Ethernet RMII (10/100 Mbps)

Symbol Description Min Typ Max Unit Condition Spec

Number

— RMII input — — 50 MHz 10/100 Mbps —

clock frequency
(RMII_CLK)

RMII1,RMII5 RMII_CLK pulse 35 — 65 %RMII_C — —

width high LK period

RMII2,RMII6 RMII_CLK pulse 35 — 65 %RMII_C — —

width low LK period

RMII3 RXD[1:0], CRS_DV, 4 — — ns — —

RXER to RMII_CLK
setup

RMII4 RMII_CLK to 2 — — ns — —
RXD[1:0], CRS_DV,
RXER hold

RMII8 RMII_CLK to — — 15 ns — —
TXD[1:0], TXEN
data valid

RMII7 RMII_CLK to 2 — — ns — —
TXD[1:0], TXEN
data invalid

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

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NXP Semiconductors
Communication interfaces

Figure 33. RMII receive diagram

Figure 34. RMII transmit diagram

15.6 I2C
See I/O parameters for I2C specification.

15.7 FlexCAN characteristics

See I/O parameters for FlexCAN specification.

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NXP Semiconductors
Communication interfaces

15.8 LPUART characteristics

See I/O parameters for LPUART specification.

15.9 SPI
NOTE
This module corresponds with DSPI section in RM

DRE=1 & SRE=0 is the required drive setting to meet the timing.

Table 54. SPI

Symbol Description Min Typ Max Unit Condition Spec

Number

tSCK SPI cycle time 1,2 100 — 10000 ns Master, MTFE=0 —

tCSC PCS to SCK delay 3 20 — 10000 ns — 2

tASC After SCK delay 4 20 — 10000 ns — 3

tSDC SCK duty cycle 40 — 60 % — 4

tPCSC PCSx to PCSS time 13 — — ns — 7

tPASC PCSS to PCSx time 13 — — ns — 8

tSUI Input data setup 27 — — ns Master, MTFE=0 —

time 5,6

tHI Input data hold 0 — — ns Master, MTFE=0 10

time 5

tSUO Output data valid — — 5 ns — —

time (after SCK
edge) 7

tHO Output data hold -2 — — ns — —

time 7

1. SMPL_PTR should be set to 1. For SPI_CTARn[BR] - 'Baud Rate Scaler' configuration is >= 3
2. The maximum SPI baud rate that is achievable in a dedicated master-slave connection depends on several parameters
that are independent of the SPI module clocking capabilities (e.g. capacitive load of the signal lines, SPI slave clock-to-
data delay, pad slew rate, etc.). The maximum achievable SPI baud rate needs to be evaluated in a corresponding SPI
master-slave setup.
3. This value of 20 ns is with the configuration prescaler values: SPI_CTARn[PCSSCK] - "PCS to SCK Delay Prescaler"
configuration is "3" (01h) and SPI_CTARn[CSSCK] - "PCS to SCK Delay Scaler" configuration is "2" (0000h)
4. This value of 20 ns is with the configuration prescaler values: SPI_CTARn[PASC] - "After SCK Delay Prescaler"
configuration is "3" (01h) and SPI_CTARn[ASC] - "After SCK Delay Scaler" configuration is "2" (0000h)
5. Input timing assumes an input signal slew rate of 2ns (20%/80%).
6. For the case of both master and slave being NXP S32x devices, frequency of operation will be reduced to
[1000 /2* {tSUI_master + tSUO_slave + PCB delay}] in ns.
7. Output timing valid for maximum external load CL = 25 pF (includes PCB trace, package trace (around 1-2pF) and flash
input load).

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NXP Semiconductors
Communication interfaces

PCSx

SCK Output
(CPOL=0)

SCK Output
(CPOL=1)

9 10

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Figure 35. SPI Classic Timing - Master, CPHA = 1, MTFE=0

2 3

PCSx

4 1

SCK Output
(CPOL=0)
4

SCK Output
(CPOL=1)

9 10

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Figure 36. SPI Classic Timing - Master, CPHA = 0, MTFE=0

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 99 / 120
NXP Semiconductors
Communication interfaces

7 8

PCSS

PCSx

Figure 37. SPI PCS Strobe (PCSS) Timing

15.10 Microsecond channel (MSC)

These specs apply to both LVDS and GPIO.

NOTE
This module corresponds with DSPI in RM.

Table 55. Microsecond channel (MSC)

Symbol Description Min Typ Max Unit Condition Spec

Number

tSCK MSC-LVDS cycle 25 — — ns LVDS 1

time

tSCK MSC-GPIO cycle 40 — — ns GPIO 1

time 1

tCSV PCS valid after — — 26 ns GPIO —

SCK 2

tCSH PCS hold after -4 — — ns — —

SCK 2

tSUO Output data valid — — 5 ns — 11

time (after SCK
edge)

tHO Output data hold -2 — — ns — 12

time

Clock Jitter 10MHz, fRF_REF =
20MHz

fLFAST_CLK PLL Output Clock 320 — 480 MHz — —

Frequency Range

tLOCK PLL Lock Time — — 250 us fRF_REF = 20MHz —

PER_jitter PLL Period Jitter — — 40 ps fRF_REF = 20MHz —

(RMS)

RJ PLL Long Term — 50 — ps VCO clock measured —

Random Jitter over 100us acquisition
at ZipWire Tx LVDS
across 100ohm load.

DJ PLL Long Term — 80 500 ps VCO clock measured —

Deterministic Jitter 1 over 100us acquisition
at ZipWire Tx LVDS
across 100ohm load.

TOT_jitter Total Jitter — 1.09 1.31 ns BER = 10-9 —

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NXP Semiconductors
Memory interfaces

Table 56. LFAST PLL (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

IPLL_HV PLL HV — — 5 mA fPLL_VCO = 960MHz —

Supply Current
Consumption

IPLL_LV PLL LV — — 5 mA fPLL_VCO = 960MHz —

Supply Current
Consumption

1. DJ max jitter includes influence of edge aligned IO activity

16 Memory interfaces

16.1 QuadSPI Octal 3.3V DDR 120MHz

The following table describes the QuadSPI electrical characteristics. Measurements are with maximum output load of 25pF, input
transition of 1ns and pads configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97V to 3.63V. QuadSPI
trace length should be less than or equal to 2 inches. For Single and Dual IO modes of operation if external device doesn’t have
pull-up feature, then external pull-up must be added at board level for unused device pins. With external pull-up, performance
of the interface may degrade in Quad IO mode based on load associated with external pull-up. QuadSPI support delay chain
upto length 16, wherein delay length of low-frequency segment is 16 and length of high-frequency segment is 0. See the device
Reference Manual for register and bit descriptions.
Data transitions measured at 30%/70% supply for the write path. Data transitions measured at mid-supply for the read path. Clock
transitions measured at mid-supply

Table 57. QuadSPI Octal 3.3V DDR 120MHz

Symbol Description Min Typ Max Unit Condition Spec

Number

fSCK_DQS SCK / DQS — — 120 MHz DLL enabled —

frequency 1

fSCK_DQS SCK / DQS — — 120 MHz DLL mode enabled —

frequency 1

tSCK SCK clock period 1/ — — ns External DQS —

fSCK_D
QS

tSDC SCK / DQS duty 45 — 55 % External DQS —

cycle

tCL_SCK_DQS SCK / DQS low 3.75 — — ns — —

time 1

tCH_SCK_DQS SCK / DQS high 3.75 — — ns — —

time 1

tOD_DATA Data output delay 0.816 — 2.934 ns — —

(w.r.t. SCK)

tOD_CS CS output delay 3.016 — -0.766 ns — —

(w.r.t. SCK)

Table continues on the next page...

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NXP Semiconductors
Memory interfaces

Table 57. QuadSPI Octal 3.3V DDR 120MHz (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

tISU_DQS Input setup time -0.616 — — ns — —

(w.r.t. DQS) 1

tIH_DQS Input hold time (w.r.t. 3.134 — — ns — —

DQS) 1

1. Input timing assumes an input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the Flash.

16.2 QuadSPI Quad 3.3V SDR 120MHz

The following table describes the QuadSPI electrical characteristics. Measurements are with maximum output load of 25pF, input
transition of 1ns and pads configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97V to 3.63V. QuadSPI
trace length should be less than or equal to 2 inches. For Single and Dual IO modes of operation if external device doesn’t have
pull-up feature, then external pull-up must be added at board level for unused device pins. With external pull-up, performance
of the interface may degrade in Quad IO mode based on load associated with external pull-up. QuadSPI support delay chain
upto length 16, wherein delay length of low-frequency segment is 16 and length of high-frequency segment is 0. See the device
Reference Manual for register and bit descriptions.
Program register value QuadSPI_FLSHCR[TCSS] = 4`h3.
Program register value QuadSPI_FLSHCR[TCSH] = 4`h3.
Data transitions measured at 30%/70% supply for the write path. Data transitions measured at mid-supply for the read path. Clock
transitions measured at mid-supply.

Table 58. QuadSPI Quad 3.3V SDR 120MHz

Symbol Description Min Typ Max Unit Condition Spec

Number

fSCK SCK clock — — 120 MHz Pad Loopback —

frequency 1

tSCK SCK clock period 1/fSCK — — ns Pad Loopback —

tSDC SCK duty cycle 45 — 55 % Pad Loopback —

tIS Data input setup 2 — — ns Pad Loopback —

time

tIH Data input hold time 1 — — ns Pad Loopback —

tOV Data output valid — — 1.75 ns Pad Loopback —

time

tIV Data output invalid -1.5 — — ns Pad Loopback —

time

tCSSCK CS to SCK time 5 — — ns Pad Loopback —

tSCKCS SCK to CS time 3 — — ns Pad Loopback —

tDVW Input data valid 4.62 — — ns — —

window

1. This frequency specification is valid only if output valid time of external flash is ≤ 5.5ns, and if output valid time of
external flash is more than 5.5ns but ≤ 6.5ns, then maximum fSCK is 104MHz.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

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NXP Semiconductors
Memory interfaces

Figure 39. QuadSPI input timing (SDR mode)

Figure 40. QuadSPI output timing (SDR mode)

16.3 QuadSPI configurations

Table 59. QuadSPI configurations (120 DDR)

Parameter Value

Frequency 120 MHz

DDR/SDR DDR

External DQS alignment Edge-aligned

Flash type Octal Flash

FLSHCR[TDH] 1

FLSHCR[TCHS] 3

FLSHCR[TCSS] 3

MCR[DLPEN] 1

Table continues on the next page...

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NXP Semiconductors
Memory interfaces

Table 59. QuadSPI configurations (120 DDR) (continued)

Parameter Value

DLLCR[DLLEN] 1

DLLCR[FREQEN] 0

DLLCR[DLL_REFCNTR] 2

DLLCR[DLLRES] 8

DLLCR[SLV_FINE_OFFSET] 0

DLLCR[SLV_DLY_OFFSET] 0

DLLCR (SLV_DLY_COARSE] NA

DLLCR[SLV_DLY_FINE] NA

DLLCR[SLAVE_AUTO_UPDT] 1

DLLCR[SLV_EN] 1

DLLCR[SLV_DLL_BYPASS] 0

DLLCR[SLV_UPD]1

SMPR[DLLFSMPF*] 4

SMPR[FSDLY] 0

SMPR[FSPHS] NA

1. See Chapter "DLL and delay chain usage" for the DLLCR programming sequence

Table 60. QuadSPI configurations (120 SDR)

Parameter Value

Frequency 120 MHz

DDR/SDR SDR

External DQS alignment Internal DQS Dummy pad loopback

Flash type Quad

FLSHCR[TDH] NA

FLSHCR[TCHS] 3

FLSHCR[TCSS] 3

MCR[DLPEN] 0

DLLCR[DLLEN] 0

DLLCR[FREQEN] 0

DLLCR[DLL_REFCNTR] NA

DLLCR[DLLRES] NA

DLLCR[SLV_FINE_OFFSET] 0

DLLCR[SLV_DLY_OFFSET] 0

Table continues on the next page...

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NXP Semiconductors
Debug modules

Table 60. QuadSPI configurations (120 SDR) (continued)

Parameter Value

DLLCR (SLV_DLY_COARSE] 0

DLLCR[SLV_DLY_FINE] 0

DLLCR[SLAVE_AUTO_UPDT] 0

DLLCR[SLV_EN] 1

DLLCR[SLV_DLL_BYPASS] 1

DLLCR[SLV_UPD]1

SMPR[DLLFSMPF*] 0

SMPR[FSDLY] 0

SMPR[FSPHS] 1

17 Debug modules

17.1 Debug trace timing specifications

The following table describes the Debug trace electrical characteristics. Measurements are with maximum output load of 25pF,
input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0.

Table 61. Debug trace timing specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

fTRACE Trace clock — — 120 MHz — —

frequency (trace on
Fast pads)

fTRACE Trace clock — — 25 MHz — —

frequency (trace on
StandardPlus pads)

tDVW Data output valid 1.2 — — ns — —

window

tDIV Data output invalid 0.3 — — ns — —

TRACECLK
tDIV tDIV

TRACEDATA[n:0] Valid data Valid data

tDVW

Figure 41. Trace CLKOUT specifications

17.2 JTAG electrical specifications

The following table describes the JTAG electrical characteristics. These specifications apply to JTAG and boundary scan.
Measurements are with maximum output load of 30pF, input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

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NXP Semiconductors
Debug modules

Table 62. JTAG electrical specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

tJCYC TCK cycle time 1,2 30 — — ns — 1

tJDC TCK clock pulse 40 — 60 % — 2

width

tTCKRISE TCK rise/fall times — — 1 ns — 3

(40%-70%)

tTMSS, tTDIS TMS, TDI data setup 5 — — ns — 4

time

tTMSH, tTDIH TMS, TDI data hold 5 — — ns — 5

time

tTDOV TCK low to TDO — — 22 ns — 6

data valid 3

tTDOI TCK low to TDO 0 — — ns — 7

data invalid

tTDOHZ TCK low to TDO — — 22 ns — 8

high impedance

tBSDV TCK falling edge to — — 600 ns — 11

output valid 4

tBSDVZ TCK falling edge to — — 600 ns — 12

output valid out of
high impedance

tBSDHZ TCK falling edge — — 600 ns — 13

to output high
impedance

tBSDST Boundary scan input 15 — — ns — 14

valid to TCK rising
edge

tBSDHT TCK rising edge to 15 — — ns — 15

boundary scan input
invalid

1. Cycle time is 30ns assuming full cycle timing. Cycle time is 60ns assuming half cycle timing.
2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.
Refer to pad specification for allowed transition frequency
3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

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NXP Semiconductors
Debug modules

TCK
2

3 2

1 3

Figure 42. JTAG TCK Input Timing

TCK

TMS, TDI

7 8

TDO

Figure 43. JTAG Test Access Port Timing

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NXP Semiconductors
Debug modules

TCK

11 13

Output
signals

14
15

Input
signals

Figure 44. Boundary Scan Timing

17.3 SWD electrical specifications

The following table describes the SWD electrical characteristics. Measurements are with maximum output load of 30pF, input
transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0.

Table 63. SWD electrical specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

S1 SWD_CLK — — 33 MHz — S1
frequency

S2 SWD_CLK cycle 1 / S1 — — ns — S2
period

S3 SWD_CLK pulse 40 — 60 % — S3
width

S4 SWD_CLK rise and — — 1 ns — S4

fall times

S9 SWD_DIO input 5 — — ns — S9
data setup time to
SWD_CLK rise

S10 SWD_DIO input 5 — — ns — S10

data hold time
after SWD_CLK
rising edge

Table continues on the next page...

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NXP Semiconductors
Thermal Attributes

Table 63. SWD electrical specifications (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

S11 SWD_CLK high to — — 22 ns — S11

SWD_DIO output
data valid

S12 SWD_CLK high to — — 22 ns — S12

SWD_DIO output
data hi-Z

S13 SWD_CLK high to 0 — — ns — S13

SWD_DIO output
data invalid

S2
S3 S3

SWD_CLK (input)

S4 S4

Figure 45. SWD Input Clock Timing

SWD_CLK

S9 S10

SWD_DIO Input data valid

S11

S13

SWD_DIO Output data valid

S12

SWD_DIO

Figure 46. SWD Output Data Timing

18 Thermal Attributes

18.1 Description
The tables in the following sections describe the thermal characteristics of the device.

18.2 Thermal Characteristics

Thermal Design and Characteristics
• Junction temperature of the device does not solely depend on package thermal resistance but is also a function of chip
power dissipation, PCB attributes, environmental conditions (ambient temperature & air flow) and cumulative effects of
other heat generating ICs on the PCB.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 110 / 120
NXP Semiconductors
Dimensions

• The appropriate thermal design must be carried out on package so that it can safely dissipate the necessary amount of
power needed for it to function properly. This may involve adding a cooling solution on the package, creating thermal
enhancements on the PCB and improving environmental conditions.
• The customer is encouraged to use the package model to perform design and risk assessment through simulations.
Package models in FloTHERM or Icepak formats can be obtained under NDA from the sales team.

Thermal Ratings
• The table below is thermal ratings for both MAPBGA and LQFP-EP package variants of S32K396, S32K394, S32K376,
S32K374, S32K366 and S32K364. These numbers are derived through simulations based on standardized tests as
described in the footnotes.
• Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a
standardized specified environment. It is not meant to predict the performance of a package in an application-specific
environment :

Table 64. Thermal Characteristics

Rating Board Type1 Symbol Value by Package Type Unit

MAPBGA 289 LQFP-EP 176 I/O

I/O

Junction to Ambient 2s2p RθJA 22.5 19.4 °C/W

Thermal Resistances2

Junction-to-Top of Package 2s2p YJT 0.4 0.7 °C/W

Thermal Characterization
Parameter 2

Junction to Case Thermal N/A RθJCtop 7.2 N/A °C/W

Resistance (top)3

Junction to Case Thermal N/A RθJCbottom N/A 1.8 °C/W

Resistance (bottom)4

1. Thermal test board meets JEDEC specification for this package (JESD51-9 for MAPBGA and 51-7 for LQFP-EP). Test board
has 7x7 via array under the package.
2. Determined in accordance with JEDEC JESD51-2A natural convection environment.
3. Junction-to-Case (top) thermal resistance determined using an isothermal cold plate. Case temperature refers to the
MAPBGA’s mold surface temperature.
4. Junction-to-Case (bottom) thermal resistance determined using an isothermal cold plate. Case temperature refers to the
exposed pad surface temperature of LQFP-EP.

19 Dimensions

19.1 Obtaining package dimensions

Package dimensions are provided in the package drawings. To find a package drawing, go to nxp.com and perform a keyword
search for the drawing’s document number:

Package option Document Number

176-pin LQFP-EP 98ASA01825D

289-ball MAPBGA 98ASA01216D

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 111 / 120
NXP Semiconductors
Revision history

20 Revision history
The following table lists the changes in this document.

Rev 4, June 2024

• Added S32K366 and S32K364 part numbers and their corresponding information
• Updated block diagrams, feature comparison and feature summary

Rev 3, Mar 2024

• Updated the 6th character in Ordering Information

• Updated the footnote attached to HVD_V15 symbol in Supply monitoring section
• ADded L_SMPS and D_SMPS in V15 regulator (SMPS option) electrical specifications table
• Updated Supply Currents section
• Added ILKG_33_TWINANAMUX and ILKG_50_TWINANAMUX and removed ILKG_GPI, ILKG_50_I and ILKG_33_I from
3.3 V GPIO DC electrical specifications section and 5.0 V GPIO DC electrical specifications
• Added footnotes to 3.3 V GPIO AC electrical specifications and 5.0 V GPIO AC electrical specifications table
• Added Reference load diagram in 3.3 V GPIO AC electrical specifications section and 5.0 V GPIO AC electrical
specifications section
• ADded footnote that states "Value in the table represents .....external circuitry" to symbols of eTPU timing, eMIOS timing
and LCU timing
• Updated existing values and added parameters at 20 MHz frequency in Sigma Delta Analogto Digital Converter table
• Updated CMRR value from 55 dB to 34 dB
• Updated maximum frequency of FPLL_out and FPLL_vcoRange in PLL table
• In LPSPI section
— Updated the first point above table to "All timing is shown with respect to 50% VDD_HV_A/B thresholds"
— Updated second point above table to "All measurements are with maximum output load of 30pF, input transition of
1 ns and pad configured DSE = 1, SRC = 0"
— Updated min values of tLEAD/tLAG to ""tSPCK/2" for LPSPI Slave mode
— For "tWPSCK", removed "high or low" from description
— Removed Rise/Fall time output specs
— Added footnotes "Output rise/fall time is determined by the output load and GPIO pad drive strength setting..." and
"The input rise/fall time specification applies to both clock and data..."
— Updated LPSPI Master Mode Timing (CPHA=0) and LPSPI Master Mode Timing (CPHA=1) figure
• In LPSPI0 20 MHz and 15 MHz Combinations section, added note "LPSPI0 20 MHz and 15 MHz Combinations"
• IN LPSPI Pad type table, removed PTF25 and updated PTA16 to PTA6
• Added note "QuadSPI cannot be used along with ENET in 176LQFP" in Ethernet MII (10/100 Mbps) section, Ethernet
MII (200 Mbps) section and Ethernet RMII (10/100 Mbps) section
• Added t2 and t3 in Microsecond channel

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 112 / 120
NXP Semiconductors
Revision history

Rev 3, Mar 2024

• Updated 176 LQFP_EP package to "Yes" in Run Mode configuration

• Updated ILKG_50_M0 LSL from -1614.4nA to -1615nA in 5.0 V GPIO DC Electrical specifications section
• Updated the footnotes of LCU skew characteristics, eTPU skew charactteristics and eFlexPWM skew characteristics

Rev 2, Aug 2023

• Updated the title of datasheet to "S32K39 and S32K37 datasheet"

• Updated the S32K38 part to S32K37 part all over the datasheet
• Removed I3C feature all over the datasheet
• Updated the S32K396 product series section
• Updated mention of "GHzPWM configuration" to "eFlexPWM configuration" in Feature Comparison and Feature
Summary
• Added Clocks section in Feature Summary
• Updated Feature Summary table
• Updated "4x arm Cortex" to "3x arm Cortex" in both block diagrams and Feature Comparison section
• Updated "arm" to "Arm" in both block diagrams
• Updated 100 Mbps Ethernet to 10/100 Mbps Ethernet
• Added Supported voltage supply use-cases, LPSPI Pad Type, and eMIOS
• Added LCU skew characteristics, eTPU skew characteristics and eFlexPWM skew characteristics
• Updated the maximum value of V15, description of V11 and added footnote ""Voltage at VDD_DCDC cannot be higher
than VDD_HV_A" in Absolute maximum ratings to VDD_DCDC
• In Voltage and current operating requirements
— Added footnote to V15 as "Min and Max values are applicable only for non-SMPS mode where V15 is sourced
externally".
— Updated footnote from “VDDA_SWG must be shorted to VDD_HV_A at the PCB level” to “Must be shorted to
VDD_HV_A at the PCB level” and add it to VDD_SDADC
— Updated footnote from “SDADC can be only used when VDD_HV_A is 5V, otherwise SDADC cannot be used” to
"SDADC is intended to be used only when VDD_HV_A is supplied with 5V. In case of VDD_HV_A is supplied with
3.3V it is recommended to disable SDADC in MC_ME module" and added to VREH_SDADC_xx
— Added footnote "All the VREFH_xx except of VREFH_R2R must be shorted to single supply source at the PCB
level, either isolated voltage reference or shorted to VDD_HV_A. Isolated VREFH_R2R is required to avoid
SDADC performance degradation. If isolated supply cannot be used, then appropriate filtration is needed to isolate
the VREFH_R2R noise." and attached to VREFH_R2R, VREFH_SDADC_xx and VREFH_SAR_xx.
— Updated the footnote attached to VREFH specs to "VREFH should always be equal to or less than VDD_HV_A
+0.1.."
— Added IINJ_LVDS parameter specs with 100 µA as typical
— Added footnote "Voltage at VDD_DCDC cannot be higher than VDD_HV_A" to VDD_DCDC

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 113 / 120
NXP Semiconductors
Revision history

Rev 2, Aug 2023

• Added footnote to HVD_V15 in Supply Monitoring

• In Recommended Decoupling Capacitors
— Added "Only needed when internal SMPS is used to generate V15 and VDD_DCDC is supplied with isolated
source from VDD_HV_A or VDD_HV_B"
— Removed COUT_V15 parameter from Recommended Decoupling Capacitors and added in V15 regulator (SMPS
option) electrical specifications as COUT_V15_SMPS
— Added CBULK_SMPS with 22 µF as typical value
— Updated the figures
• Updated the title name of V15 regulator (SMPS option) electrical specifications and V11 regulator (NMOS ballast
transistor control) electrical specifications
• In V11 regulator (NMOS ballast transistor control) electrical specifications. split VTH_NMOS for 3.3 V supply and 5
Vsupply
• Updated the typical value of V15 Output from 1.51 to 1.5 in V15 regulator (SMPS option) electrical specifications
• Updated the description of V15 to "V15 Input" and typical value to 1.5 in V11 regulator (NMOS ballast transistor control)
electrical specifications
• Added V11 output with 1.14 typical value in V11 regulator (NMOS ballast transistor control) electrical specifications
• In Supply currents section
— Added column for VDD_HV_B in Example RUN mode configuration supply currents table
— Removed Clock Option E column from Low speed RUN mode supply currents table
— Removed "RUN mode supply currents (peripherals disabled)" table
• Updated eFLEXPWM to 12 channels and eMIOS to 6 channels in RUN mode configuration options table in Operating
mode
• Updated GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) and in GPIO DC electrical specifications, 5.0V
(4.5V - 5.5V)
• Updated 3.3V (2.97V - 3.63V) GPIO Output AC Specification and 5.0V (4.5V - 5.5V) GPIO Output AC Specification
• Added eTPU timing diagram in eTPU timing
• In LVDS 3.3V Transmitter Electrical Specifications and LVDS 5V Transmitter Electrical Specifications, updated the
symbol of Deterministic Jitter from Eye_Jitter to Dj
• In LVDS 5V Transmitter Electrical Specifications, updated min of Ipin_leakage to -5.6 and max to 5.6 and updated the
unit of Dmax from MHz to Mbps
• In SAR_ADC section, updated paragraph "All below specs are applicable...". and added footnote to TUE as "Spec valid
if potential difference between VDD_HV_A.." and figure updated to show VDD_HV_A instead of VREF
• In eFlexPWM, added "only for single instance" in Condition column of IVDD current consumption
• Updated the values of Sigma Delta Analog to Digital Converter
• In LPCMP section changed ACMP0 to LPCMP0 and updated the information after the table
• In Sine wave generator, updated the footnotes and updated the minimum value of APP to 0.394 to be similar to
minimum value of MINAPP

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 114 / 120
NXP Semiconductors
Revision history

Rev 2, Aug 2023

• In Fast External Oscillator (FXOSC)

— Updated IFOSXC, added EXTAL_SWING_PP, added CLKIN_VIL_EXTAL_BYPASS, CLKIN_VIH_EXTAL_BYPASS
specifications and VSB specs and related footnote
— Added two notes after the table
• Updated section and table name from "Ethernet MII (100 Mbps)" to "Ethernet MII (10/100 Mbps)" and "Ethernet RMII" to
"Ethernet RMII (10/100 Mbps)"
• In Ethernet MII (10/100 Mbps)
— Added 10/100 Mbps as Condition for RXCLK frequency, MII3, MII4 and TXCLK frequency
— Updated the typical value of RXCLK frequency and TXCLK frequency to 2.5/25
— Added 10/100 Mbps as Condition for RMII input clock frequency
• Updated SPIsection
— Added "DRE=1 and SRE=0....timing" before table
— Added Note "This modules corresponds with DSPI in RM"
— Removed tA and tDIS and updated load capacitance from 25 pF to 30 pF
• In Microsecond channel (MSC)
— ADded footnote to MSC_GPIO stating "if MSC functionality is not used it can be used as SPI interface"
— Added Note "This modules corresponds with DSPI in RM"
— Added t1 with min as -1 and max as 1 ns
— Updated the minimum values of tSCK (LVDS) to 25 and tSCK (GPIO) to 40
— Removed the parameter tCSC and tASC and added parameter tCSV and tCSH in
— Updated the maximum value of tSCV to 26 ns(GPIO) and minimum value tSCH to -4 ns
• Removed auto-learning mode from QuadSPI Octal 3.3V DDR 120MHz table
• In PLL, updated the footnote to "For SSCG, jitter due to systematic modulation needs to be added as per applied
modulation. Accumulated jitter specification is not valid with SSCG."
• Added sentence before the table in PLL
• Added accumulated and period jitter specifications in PLL table
• In LFAST PLL table, updated the typical value of Rj to 50 ps. Updated the typical value of Dj to 80 ps and maximum
value to 500 ps and added footnote "DJ max jitter includes influence of edge aligned IO activity"
• Added "Data transitions measured....mid-supply" in QuadSPI Octal 3.3V DDR 120MHz and QuadSPI Octal 3.3V DDR
120MHz

Rev 1.1, Aug 2022

• In section "Voltage and current operating requirements", added "contact NXP sales representative for Hardware design
guidelines document/package".
• Updated section "Sigma Delta Analog to Digital Converter" to remove TBDs and other updates.
• In section "SAR ADC", removed TBD from RS (max) specification.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 115 / 120
NXP Semiconductors
Revision history

Rev 1, Aug 2022

• Updated data sheet classification to "Advance Information".

• Updated sections S32K396 product series, feature comparison and feature summary.
• In section "Absolute maximum ratings":
— Updated V15 description as "Voltage sensing input".
— Added voltage range for VDD_LVDS.
• In section "Voltage and current operating requirements":
— Added a note as "DSPI/MSC interface is supported only at VDD_HV_A = 5V."
— Updated V15 description as "Voltage sensing input".
— Added footnote to VDDA_SWG as "VDDA_SWG must be shorted to VDD_HV_A at the PCB level."
— Added voltage range for VDD_LVDS and footnote "Ensure that VDD_HV_A ramps before VDD_LVD.".
— Added VDD_SDADC supply.
— ADC reference voltage symbol and description updated.
— Removed 3.3 V from SD ADC reference voltage typical, updated minimum and added a footnote as
"VREFH_SDADC_xx must be shorted to single supply source...".
— Added R2R high/low voltage reference specifications.
• Deleted LVD_V15 from "Supply monitoring""
• In section "Recommended Decoupling Capacitors":
— Updated description of CDEC and a related footnote updated to mention 10nF instead of 1 nF Optionally, 10 nF
capacitors can be added...".
— Decoupling capacitors pinout diagrams updated.
• In section "SMPS regulator electrical specifications":
— Added "External schottky diode average forward current".
— Added 2V as "External P-channel MOSFET threshold voltage".
• In section "NMOS Ballast Transistor Control Specification" added CNMOS (NMOS gate stability capacitor)
• Updated IDD tables in "Supply currents".
• In section "Operating mode" changed I3C to I2C.
• Added section "Cyclic wake-up current"
• In section "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)" deleted ILKG_33_S_PTE13.
• In section "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)" deleted ILKG_50_S_PTE13.
• In section "LVDS 3.3V Receiver Electrical Specifications", added sentence "These specifications are related to LVDS
pads dedicated to Zipwire."
• Added "LCU"and "eTPU timing".
• Changed "AE Nano Edge" to eFlexPWM.
• In section "SAR SDC"

Table continues on the next page...

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 116 / 120
NXP Semiconductors
Revision history

Rev 1, Aug 2022

— CP2 (all/standard channels) updated from 4.18 to 5 pF.

— CP2 (precision channels) updated from 1.42 to 2.2 pF.
— In footnote attached to TUE updated to mention 12-bit level resolution for both precision and standard channels.
• In section "FXOSC" removed crystal recommendations and updated a paragraph as "To ensure stable oscillations,
FXOSC...".
• In section "LPSPI", updated part of sentence as "All measurements are with maximum output load of 30 pF...." and
updated tV for Slave_10Mbps from 36 to 41 ns.
• In section "MDIO timing specifications" updated MDC3 from 25 to 28 ns.
• In section "I3C Push-Pull Timing Parameters for SDR Mode" added tDVO specs and updated tSU_PP from 3 to 5 ns.
• Added sections "SPI" and "Microsecond channel (MSC)".
• In section "QuadSPI Octal 3.3V DDR 120MHz":
— Updated part of sentence as "QuadSPI trace length should be less than or equal to 2 inches.".
— Updated tOD_DATA, tOD_CS, IH_DQS and deleted tDVW.
• In section "QuadSPI Quad 3.3V SDR 120MHz":
— Updated part of sentence as "QuadSPI trace length should be less than or equal to 2 inches.".
— deleted specs related to internal loopback, updated tIS and tDVW
• Added QuadSPI configurations.

S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 117 / 120
NXP Semiconductors
Legal information

Legal information

Data sheet status

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product
development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices.
The latest product status information is available on the Internet at URL https://www.nxp.com.

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under internal review and subject to formal approval, which may result to be accurate and reliable. However, NXP Semiconductors does not give
in modifications or additions. NXP Semiconductors does not give any any representations or warranties, expressed or implied, as to the accuracy
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S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 118 / 120
NXP Semiconductors
Legal information

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S32K39, S32K37 and S32K36 Data Sheet, Rev. 4, 06/2024

Data Sheet: Technical Data 119 / 120
Please be aware that important notices concerning this document and the product(s) described
herein, have been included in section 'Legal information'.

For more information, please visit: https://www.nxp.com

Date of release: 06/2024

Document identifier: S32K396

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