Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block

Design of an AMBA-Advanced High

performance Bus (AHB) Protocol IP
Block
Design and Verification of a Bus Bridge from OCP to AHB
1
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
Abstract
he AHB (Advanced High-performance Bus) is a high-performance !us in
AMBA (Advanced Microcontroller Bus Architecture) famil"# his AHB can !e used in
high clock fre$uenc" s"stem modules# he AHB acts as the high-performance s"stem
!ack!one !us# AHB supports the efficient connection of processors% on-chip memories
and off-chip e&ternal memor" interfaces 'ith lo'-po'er peripheral macro cell functions#
AHB is a technolog"-independent and ensure that highl" reusa!le peripheral and
s"stem macro cells can !e migrated across a diverse range of I( processes and !e
appropriate for full-custom% standard cell and gate arra" technologies# )enerall"% an
AMBA-!ased microcontroller t"picall" consists of a high-performance s"stem !ack!one
!us (AMBA AHB)% a!le to sustain the e&ternal memor" !and'idth% on 'hich the (P*%
on-chip memor" and other Direct Memor" Access (DMA) devices reside#
In this 'ork% the design of the Advanced High-Performance Bus Protocol is
developed 'hich has the !asic !locks such as Master and +lave# he ar!itration
mechanism is used to ensure that onl" one master has access to the !us at an" one time
and the AHB decoder is used to decode the address of each transfer and provide a select
signal for the slave that is involved in the transfer# his AMBA-AHB protocol can !e
adopted in all the application provided the design should !e an AHB compliant#
Design and Verification of a Bus Bridge from OCP to AHB
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
Chapter 1Introduction
1.1 Aim
he main aim of this 'ork is to design an AMBA (Advanced Microcontroller Bus
Architecture) - AHB (Advanced High-Performance Bus) protocol and verif"ing it
functional !ehavior 'ith the help of its simulation results#
1.2 Basic Idea
Basic idea is to perform the proper and lossless communication !et'een the IP
cores 'hich using same protocols on the +"stem on (hip (+.() s"stem# Basicall"% an
+.( is a s"stem 'hich is considered as a set of components and interconnects among
them# he dataflo' 'ill happen in the s"stem in order to achieve a successful process and
hence for 'hich the various interfaces is re$uired# If these interfaces have issues% then the
process to !e achieved 'ill fail 'hich leads to fail of 'hole application#
)enerall"% in an +.( s"stem% the protocols can !e used as interfaces 'hich 'ill
!e !ased on the application and also the designer# he interface has its o'n properties
'hich suits for the corresponding application#
1.3 Need for Project
his pro/ect is chosen !ecause currentl" the issues are increased in the industries
due to the lack of proper data transferring !et'een the IP cores on the +"stem on (hip
(+.() s"stem#
In recent da"s% the development of +.( chips and the reusa!le IP cores are given
higher priorit" !ecause of its less cost and reduction in the period of ime-to-Market# +o
this ena!les the ma/or and ver" sensitive issue such as interfacing of these IP cores# hese
interfaces pla" a vital role in +.( and should !e taken care !ecause of the
communication !et'een the IP cores propert"# he communication !et'een the different
IP cores should have a lossless data flo' and should !e fle&i!le to the designer too#
Design and Verification of a Bus Bridge from OCP to AHB
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
Hence to resolve this issue% the standard protocol !uses are used in or order to
interface the t'o IP cores# Here the loss of data depends on the standards of protocols
used# Most of the IP cores from A1M uses the AMBA (Advanced Microcontroller Bus
Architecture) 'hich has AHB (Advanced High-Performance Bus)# his !us has its o'n
advantages and fle&i!ilities# A full AHB interface is used for the follo'ing#
Bus masters
.n-chip memor" !locks
2&ternal memor" interfaces
High-!and'idth peripherals 'ith 3I3. interfaces
DMA slave peripherals
1.4 Objecties of the A!BA "pecification
he AMBA specification has !een derived to satisf" four ke" re$uirements4
o facilitate the right-first-time development of em!edded microcontroller
products 'ith one or more (P*s or signal processors#
o !e technolog"-independent and ensure that highl" reusa!le peripheral and
s"stem macro cells can !e migrated across a diverse range of I( processes and !e
appropriate for full-custom% standard cell and gate arra" technologies#
o encourage modular s"stem design to improve processor independence%
providing a development road-map for advanced cached (P* cores and the
development of peripheral li!raries#
o minimi5e the silicon infrastructure re$uired to support efficient on-chip and
off-chip communication for !oth operation and manufacturing test#
1.# $%pica& A!BA'based !icrocontro&&er
An AMBA-!ased microcontroller t"picall" consists of a high-performance s"stem
!ack!one !us (AMBA AHB or AMBA A+B)% a!le to sustain the e&ternal memor"
!and'idth% on 'hich the (P*% on-chip memor" and other Direct Memor" Access (DMA)
devices reside# his !us provides a high-!and'idth interface !et'een the elements that
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
are involved in the ma/orit" of transfers# Also located on the high-performance !us is a
!ridge to the lo'er !and'idth APB% 'here most of the peripheral devices in the s"stem
are located#
(i)ure 1.1 $%pica& A!BA "%stems
he ke" advantages of a t"pical AMBA +"stem are listed as follo's#
High performance
Pipelined operation
Multiple !us masters
Burst transfers
+plit transactions
AMBA APB provides the !asic peripheral macro cell communications
infrastructure as a secondar" !us from the higher !and'idth pipelined main s"stem !us
such peripherals t"picall"#
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
8 Have interfaces 'hich are memor"-mapped registers
8 Have no high-!and'idth interfaces
8 Are accessed under programmed control
he e&ternal memor" interface is application-specific and ma" onl" have a narro'
data path% !ut ma" also support a test access mode 'hich allo's the internal AMBA
AHB% A+B and APB modules to !e tested in isolation 'ith s"stem-independent test sets#
Here the importance of pro/ect comes into picture i#e# AMBA-AHB plays a vital
role by doing its transaction between two different IP cores, which will make the
application fail when it doesnt work properly!#
1.* $ermino&o)%
he follo'ing terms are used throughout this specification
1.*.1 Bus C%c&e
A !us c"cle is a !asic unit of one !us clock period and for the purpose of AMBA
AHB or APB protocol descriptions is defined from rising-edge to rising-edge transitions#
An A+B !us c"cle is defined from falling-edge to falling-edge transitions# Bus signal
timing is referenced to the !us c"cle clock#
1.*.2 Bus $ransfer
An AMBA AHB !us transfer is a read or 'rite operation of a data o!/ect% 'hich
ma" take one or more !us c"cles# he !us transfer is terminated !" a completion response
from the addressed slave# he transfer si5es supported !" AMBA AHB include !"te (9-
!it)% half 'ord (1:-!it) and 'ord (0,-!it)#
1.*.3 Burst Operation
A !urst operation is defined as one or more data transactions% initiated !" a !us
master% 'hich have a consistent 'idth of transaction to an incremental region of address
space# he increment step per transaction is determined !" the 'idth of transfer (!"te%
half 'ord and 'ord)#
1.+ APP,ICA$ION"
Design and Verification of a Bus Bridge from OCP to AHB
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
AMBA-AHB can !e used in the different application and also it is technolog"
independent#
A1M (ontrollers are designed according to the specifications of AMBA#
In the present technolog"% high performance and speed are re$uired 'hich are
convincingl" met !" AMBA-AHB
(ompared to the other architectures AMBA-AHB is far more advanced and
efficient#
o minimi5e the silicon infrastructure to support on-chip and off-chip
communications
An" em!edded pro/ect 'hich involve in A1M processors or microcontroller must
al'a"s make use of this AMBA-AHB as the common !us through out the pro/ect#
Design and Verification of a Bus Bridge from OCP to AHB
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
Chapter 2 A!BA'A-B Protoco&
2.1 Introduction
he AHB (Advanced High-performance Bus) is a high-performance !us in
AMBA (Advanced Microcontroller Bus Architecture) famil"# his AHB can !e used in
high clock fre$uenc" s"stem modules# he AHB acts as the high-performance s"stem
!ack!one !us# AHB supports the efficient connection of processors% on-chip memories
and off-chip e&ternal memor" interfaces 'ith lo'-po'er peripheral macro cell functions#
AHB is also specified to ensure ease of use in an efficient design flo' using automated
test techni$ues# his AHB is a technolog"-independent and ensure that highl" reusa!le
peripheral and s"stem macro cells can !e migrated across a diverse range of I( processes
and !e appropriate for full-custom% standard cell and gate arra" technologies#
2.2 (eatures
AMBA Advanced High-performance Bus (AHB) supports the follo'ing features#
High performance
Burst transfers
+plit transactions
+ingle edge clock operation
+2<% =.=+2<% B*+>% and ID?2 ransfer "pes
Programma!le num!er of idle c"cles
?arge Data !us-'idths - 0,% :6% 1,9 and ,7: !its 'ide
Address Decoding 'ith (onfigura!le Memor" Map
2.3 !erits
+ince AHB is a most commonl" used !us protocol% it must have man" advantages
from designer@s point of vie' and are mentioned !elo'#
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
AHB offers a fairl" lo' cost (in area)% lo' po'er (!ased on IA.) !us 'ith a
moderate amount of comple&it" and it can achieve higher fre$uencies 'hen
compared to others !ecause this protocol separates the address and data phases#
AHB can use the higher fre$uenc" along 'ith separate data !uses that can !e
defined to 1,9-!it and a!ove to achieve the !and'idth re$uired for high-
performance !us applications#
AHB can access other protocols through the proper !ridging converter# Hence it
supports the !ridge configuration for data transfer#
AHB allo's slaves 'ith significant latenc" to respond to read 'ith an H12+P of
B+P?IC# he slave 'ill then re$uest the !us on !ehalf of the master 'hen the
read data is availa!le# his ena!les !etter !us utili5ation#
AHB offers !urst capa!ilit" !" defining incrementing !ursts of specified length
and it supports !oth incrementing and 'rapping# Although AHB re$uires that an
address phase !e provided for each !eat of data% the slave can still use the !urst
information to make the proper re$uest on the other side# his helps to mask the
latenc" of the slave#
AHB is defined 'ith a choice of several !us 'idths% from 9-!it to 1D,6-!it# he
most common implementation has !een 0,-!it% !ut higher !and'idth re$uirements
ma" !e satisfied !" using :6 or 1,9-!it !uses#
AHB used the H12+P signals driven !" the slaves to indicate 'hen an error has
occurred#
AHB also offers a large selection of verification IP from several different
suppliers# he solutions offered support several different languages and run in a
choice of environments#
Access to the target device is controlled through a M*E% there!" admitting !us-
access to one !us-master at a time#
AHB Masters% +laves and Ar!iters support 2arl" Burst ermination# Bursts can !e
earl" terminated either as a result of the Ar!iter removing the H)1A= to a
master part 'a" through a !urst or after a slave returns a non-.FA> response to
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
an" !eat of a !urst# Ho'ever that a master cannot decide to terminate a defined
length !urst unless prompted to do so !" the Ar!iter or +lave responses#
An" slave 'hich does not use +P?I responses can !e connected directl" to an
AHB master# If the slave does use +P?I responses then a simplified version of
the ar!iter is also re$uired#
hus the strengths of the AHB protocol is listed a!ove 'hich clearl" resem!les
the reason for the 'ide use of this protocol#
2.4 .emerits
2ven though AHB protocol is commonl" used !us in the design% it has some
afforda!le demerits 'hich are listed !elo'#
AHB cannot achieve full data !us utili5ation and !and'idth if some slaves have a
relativel" high latenc"#
AHB defines transfer si5es of 1% ,% 6% 9% and 1: !"tes# Because !"te ena!les are
not defined% there are cases 'here multiple transfers must !e made inside a single
$uad'ord#
AHB defines timing parameters for man" of the relationships !et'een signals on
the !us# Ho'ever% these are not associated 'ith re$uirements relative to a clock
c"cle# herefore% +o( developers must integrate AHB cores and run chip level
static timing anal"sis to /udge ho' compati!le AHB masters and slaves are 'ith
one another#
Po'er-!ased +o(s cover a 'ide range of applications% and there is a
corresponding 'ide range of address map re$uirements# Having the address
decodes for all AHB slaves reside 'ithin the interconnect means having to support
the most comple& split address ranges% even for the simplest of slaves#
hus the 'eakness of AHB protocol is mentioned a!ove 'hich can !e tolerated
'ith respect to its useful advantages#
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
2.# B&oc/ .ia)ram
he !lock diagram of the Advanced High-Performance Bus Protocol is sho'n in
the 3igure ,#1#
(i)ure 2.1 A!BA A-B b&oc/ dia)ram
otall" this !lock diagram comprises of four components#
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
Ar!iter
Master
+lave
Decoder
Arbiter
he ar!itration mechanism is used to ensure that onl" one master has access to the
!us at an" one time# he ar!iter performs this function !" o!serving a num!er of different
re$uests to use the !us and deciding 'hich is currentl" the highest priorit" master
re$uesting the !us#
Master
A !us master is a!le to initiate read and 'rite information !" providing address
and control information# .nl" one !us master can use the !us at the same time An AHB
!us master has the most comple& !us interface in an AMBA s"stem# "picall" an AMBA
s"stem designer 'ould use predesigned !us masters and therefore 'ould not need to !e
concerned 'ith the detail of the !us master interface# =o provision is made 'ithin the
AHB specification for a !us master to cancel a transfer once it has commenced#
Slave
After a master has started a transfer% the slave then determines ho' the transfer
should progress# Hhenever a slave is accessed it must provide a response 'hich indicates
the status of the transfer# he H12AD> signal is used to e&tend the transfer and this
'orks in com!ination 'ith the response signal H12+P 'hich provide the status of the
transfer#
he slave can complete the transfer in a num!er of 'a"s# It can4
(omplete the transfer immediatel"
+ignal an error to indicate that the transfer has failed
Dela" the completion of the transfer% !ut allo' the master and slave to !ack off
the !us% leaving it availa!le for other transfers#
Decoder
Design and Verification of a Bus Bridge from OCP to AHB
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
he AHB decoder is used to decode the address of each transfer and provide a
select signal for the slave that is involved in the transfer# A central address decoder is
used to provide a select signal IH+2?&@ for each slave on the !us# he select signal is a
com!inatorial decode of the high-order address signals# A slave must onl" sample the
address and control signals and H+2?& is asserted 'hen H12AD> is HI)H% indicating
that the current transfer is completing#
"orking
he AMBA AHB !us protocol is designed 'ith a central multiple&or
interconnection scheme#
*sing this scheme all !us masters drive out the address and control signals indicating the
transfer% the" 'ish to perform and the ar!iter determines 'hich master has its address and
control signals routed to all of the slaves# Before 'hich initiall" the master 'ho needs to
perform the operation should give the re$uest signal to the ar!iter and the ar!iter 'ill give
the grant signal to the master for further proceedings# +imilarl"% a decoder is used to
select the slave 'hich has to !e active during the operation !ased on the address given !"
the master# A central decoder is also re$uired to control the read data and response signal
multiple&or% 'hich selects the appropriate signals from the slave that is involved in the
transfer# hese make the read and 'rite operation smoothl"#
hus the 'orking of AMBA AHB protocol is e&plained 'ith the help of its !lock
diagram sho'n in 3igure ,#1#
2.* "pecification
he follo'ing points should !e considered 'hen reading the AMBA specification
echnolog" independence
2lectrical characteristics
iming specification
2.*.1 $echno&o)% Independence
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
AMBA is a technolog"-independent on-chip protocol# he specification onl"
details the !us protocol at the clock c"cle level#
2.*.2 0&ectrica& Characteristics
=o information regarding the electrical characteristics is supplied 'ithin the
AMBA specification as this 'ill !e entirel" dependent on the manufacturing process
technolog" that is selected for the design#
2.*.3 $imin) "pecification
he AMBA protocol defines the !ehavior of various signals at the c"cle level# he
e&act timing re$uirements 'ill depend on the process technolog" used and the fre$uenc"
of operation# Because the e&act timing re$uirements are not defined !" the AMBA
protocol% the s"stem integrator is given ma&imum fle&i!ilit" in allocating the signal
timing !udget amongst the various modules on the !us#
2.+ A!BA "i)na&s
All AMBA signals are named such that the first letter of the name indicates 'hich
!us the signal is associated 'ith# A lo'er case n in the signal name indicates that the
signal is active ?.H% other'ise signal names are al'a"s all upper case#
est signals have a prefi& regardless of the !us t"pe#
2.+.1 A-B "i)na& Prefi1es
IH@ indicates an AHB signal#
3or e&ample% H12AD> is the signal used to indicate that the data portion of an
AHB transfer can complete# It is active HI)H#
2.+.2 A!BA A-B "i)na& ,ist2
All signals are prefi&ed 'ith the letter H% ensuring that the AHB signals are
differentiated from other similarl" named signals in a s"stem design# he signals involved
in designing the AMBA AHB are listed in the a!le ,#1 'hich also gives the
specification of each signal#
$ab&e 2.1 A!BA A-B si)na& specification
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
".No. NA!0 3I.$- .4I504 (6NC$ION
1 H(?F 1 (lock +ource
his clock times all !us transfers at the
rising edge of H(?F
, HADD1 0, Master he s"stem address !us of 'idth 0,-!it
0 H1A=+ , Master
Indicates the t"pe of the current
transfer happening
6 HH1I2 1 Master
Hhen HI)H this signal indicates a
'rite transfer and 'hen ?.H a read
transfer
7 H+IJ2 0 Master Indicates the si5e of the transfer
: HB*1+ 0 Master
Indicates if the transfer forms part of a
!urst#
; HHDAA 9 Master
he 'rite data !us is used to transfer
data from the master to the !us slaves
during 'rite operations#
9 H+2?& 1 Decoder
2ach AHB slave has its o'n slave
select signal and this signal indicates
that the current transfer is intended for
the selected slave#
G H1DAA 9 +lave
he read data !us is used to transfer
data from !us slaves to the !us master
during read operations#
1D H12AD> 1 +lave
Hhen HI)H the H12AD> signal
indicates that a transfer has finished on
the !us# his signal ma" !e driven
?.H to e&tend a transfer#
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
11 H12+P , +lave
he transfer response provides
additional information on the status of
a transfer
he ta!le also includes the function of each signal and the source from 'hich the
each signal is driven# he operation is performed in a s"nchroni5ed clock fre$uenc" and
hence the signals should !e changed 'ith respect to the rising edge of the clock#
2.7 Oerie8 of A!BA A-B Operation
Before an AMBA AHB transfer can commence the !us master must !e granted
access to the !us# his process is started !" the master asserting a re$uest signal to the
ar!iter# hen the ar!iter indicates 'hen the master 'ill !e granted use of the !us#
A granted !us master starts an AMBA AHB transfer !" driving the address and
control signals# hese signals provide information on the address% direction and 'idth of
the transfer% as 'ell as an indication if the transfer forms part of a !urst# 'o different
forms of !urst transfers are allo'ed#
8 Incrementing !ursts% 'hich do not 'rap at address !oundaries
8 Hrapping !ursts% 'hich 'rap at particular address !oundaries
A 'rite data !us is used to move data from the master to a slave% 'hile a read data
!us is used to move data from a slave to the master#
2ver" transfer consists of4
8 An address and control c"cle
8 .ne or more c"cles for the data#
he address cannot !e e&tended and therefore all slaves must sample the address
during this time# he data% ho'ever% can !e e&tended using the H12AD> signal# Hhen
?.H this signal causes 'ait states to !e inserted into the transfer and allo's e&tra time
for the slave to provide or sample data#
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
During a transfer the slave sho's the status using the response signals% H12+P
O9A:. he .FA> response is used to indicate that the transfer is progressing normall"
and 'hen H12AD> goes HI)H this sho's the transfer has completed successfull"#
2.7.1 Address .ecodin)
A central address decoder is used to provide a select signal% H+2?&% for each slave
on the !us# he select signal is a com!inatorial decode of the high-order address signals%
and simple address decoding schemes are encouraged to avoid comple& decode logic and
to ensure high-speed operation#
(i)ure 2.2 .ecoder and "&ae se&ect si)na&s
A slave must onl" sample the address and control signals and H+2?& 'hen
H12AD> is HI)H% indicating that the current transfer is completing# *nder certain
circumstances it is possi!le that H+2?& 'ill !e asserted 'hen H12AD> is ?.H% !ut the
selected slave 'ill have changed !" the time the current transfer completes#
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
In the case 'here a s"stem design does not contain a completel" filled memor"
map an additional default slave should !e implemented to provide a response 'hen an" of
the none&istent address locations are accessed# "picall" the default slave functionalit"
'ill !e implemented as part of the central address decoder#
2.7.2 "&ae $ransfer 4esponses
After a master has started a transfer% the slave then determines ho' the transfer
should progress# =o provision is made 'ithin the AHB specification for a !us master to
cancel a transfer once it has commenced#
Hhenever a slave is accessed it must provide a response 'hich indicates the status
of the transfer# he H12AD> signal is used to e&tend the transfer and this 'orks in
com!ination 'ith the response signals% H12+P K14DL% 'hich provide the status of the
transfer# he slave can complete the transfer !" doing its transfer immediatel"#
2.7.3 A-B .ecoder2
he decoder in an AMBA s"stem is used to perform a centrali5ed address
decoding function% 'hich improves the porta!ilit" of peripherals% !" making them
independent of the s"stem memor" map#
(i)ure 2.3 A-B .ecoder Interface .ia)ram
2.7.4 Arbitration
he ar!itration mechanism is used to ensure that onl" one master has access to the
!us at an" one time# he ar!iter performs this function !" o!serving a num!er of different
re$uests to use the !us and deciding 'hich is currentl" the highest priorit" master
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
re$uesting the !us# he ar!iter also receives re$uests from slaves that 'ish to complete
+P?I transfers#
An" slaves 'hich are not capa!le of performing +P?I transfers do not need to !e
a'are of the ar!itration process% e&cept that the" need to o!serve the fact that a !urst of
transfers ma" not complete if the o'nership of the !us is changed#
Interface .ia)ram
(i)ure 2.4 A-B Arbiter Interface .ia)ram
he role of the ar!iter in an AMBA s"stem is to control 'hich master has access
to the !us# 2ver" !us master has a 12<*2+A)1A= interface to the ar!iter and the
ar!iter uses a prioriti5ation scheme to decide 'hich !us master is currentl" the highest
priorit" master re$uesting the !us#
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Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
he detail of the priorit" scheme is not specified and is defined for each
application# It is accepta!le for the ar!iter to use other signals% either AMBA or non-
AMBA% to influence the priorit" scheme that is in use#
"i)na& .escription
A !rief description of each of the ar!itration signals is given !elo'#
H#$%&
he !us re$uest signal is used !" a !us master to re$uest access to the !us# 2ach
!us master has its o'n HB*+12<& signal to the ar!iter and there can !e up to 1:
separate !us masters in an" s"stem#
H'#A()&
he grant signal is generated !" the ar!iter and indicates that the appropriate
master is currentl" the highest priorit" master re$uesting the !us% taking into account
locked transfers and +P?I transfers#
A master gains o'nership of the address !us 'hen H)1A=& is HI)H and
H12AD> is HI)H at the rising edge of H(?F#
HMA*)$#
he ar!iter indicates 'hich master is currentl" granted the !us using the
HMA+21K04DL signals and this can !e used to control the central address and control
multiple&er#
2.7.# 4e;uestin) Bus Access
A !us master uses the H12<& signal to re$uest access to the !us and ma" re$uest
the !us during an" c"cle# he ar!iter 'ill sample the re$uest on the rising of the clock and
then use an internal priorit" algorithm to decide 'hich master 'ill !e the ne&t to gain
access to the !us#
=ormall" the ar!iter 'ill onl" grant a different !us master 'hen a !urst is
completing# Ho'ever% if re$uired% the ar!iter can terminate a !urst earl" to allo' a higher
priorit" master access to the !us#
Hhen a master is granted the !us and is performing a fi&ed length !urst it is not
necessar" to continue to re$uest the !us in order to complete the !urst# he ar!iter
Design and Verification of a Bus Bridge from OCP to AHB
,D
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
o!serves the progress of the !urst and uses the HB*1+K,4DL signals to determine ho'
man" transfers are re$uired !" the master# If the master 'ishes to perform a second !urst
after the one that is currentl" in progress then it should re-assert the re$uest signal during
the !urst# If a master loses access to the !us in the middle of a !urst then it must re-assert
the H12<& re$uest line to regain access to the !us#
3or undefined length !ursts the master should continue to assert the re$uest until it
has started the last transfer# he ar!iter cannot predict 'hen to change the ar!itration at
the end of an undefined length !urst# It is possi!le that a master can !e granted the !us
'hen it is not re$uesting it# his ma" occur 'hen no masters are re$uesting the !us and
the ar!iter grants access to a default master# herefore% it is important that if a master does
not re$uire access to the !us it drives the transfer t"pe H1A=+ to indicate an ID?2
transfer#
2.7.* <rantin) Bus Access
he ar!iter indicates 'hich !us master currentl" the highest priorit" is re$uesting
the !us !" asserting the appropriate H)1A=& signal# Hhen the current transfer
completes% as indicated !" H12AD> HI)H% then the master 'ill !ecome granted and the
ar!iter 'ill change the HMA+21 K04DL signals to indicate the !us master num!er#
he ar!iter changes the H)1A=& signals 'hen the penultimate (one !efore last)
address has !een sampled# he ne' H)1A=& information 'ill then !e sampled at the
same point as the last address of the !urst is sampled#
Design and Verification of a Bus Bridge from OCP to AHB
,1
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
(i)ure 2.# Bus !aster <rant "i)na&s
Because a central multiple&er is used% each master can drive out the address of the
transfer it 'ishes to perform immediatel" and it does not need to 'ait until it is granted
the !us# he H)1A=& signal is onl" used !" the master to determine 'hen it o'ns the
!us and hence 'hen it should consider that the address has !een sampled !" the
appropriate slave# A dela"ed version of the HMA+21 !us is used to control the 'rite
data multiple&er#
2.7.+ .efau&t Bus !aster
2ver" s"stem must include a default !us master 'hich is granted the !us if all
other masters are una!le to use the !us# Hhen granted% the default !us master must onl"
perform ID?2 transfers# If no masters are re$uesting the !us then the ar!iter ma" either
Design and Verification of a Bus Bridge from OCP to AHB
,,
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
grant the default master or alternativel" it ma" grant the master that 'ould !enefit the
most from having lo' access latenc" to the !us#
)ranting the default master access to the !us also provides a useful mechanism for
ensuring that no ne' transfers are started on the !us and is a useful step to perform prior
to entering a lo'-po'er mode of operation#
2.7.7 A-B .ata Bus 3idth2
.ne 'a" to improve !us !and'idth 'ithout increasing the fre$uenc" of operation
is to make the data path of the on-chip !us 'ider# Both the increased la"ers of metal and
the use of large on-chip memor" !locks (such as 2m!edded D1AM) are driving factors
'hich encourage the use of 'ider on-chip !uses#
+pecif"ing a fi&ed 'idth of !us 'ill mean that in man" cases the 'idth of the !us
is not optimal for the application# herefore an approach has !een adopted 'hich allo's
fle&i!ilit" of the 'idth of !us% !ut still ensures that modules are highl" porta!le !et'een
designs#
he protocol allo's for the AHB data !us to !e 9% 1:% 0,% :6% 1,9% ,7:% 71, or
1D,6-!its 'ide# Ho'ever% it is recommended that a minimum !us 'idth of 0, !its is used
and it is e&pected that a ma&imum of ,7: !its 'ill !e ade$uate for almost all applications#
3or !oth read and 'rite transfers the receiving module must select the data from the
correct !"te lane on the !us# 1eplication of data across all !"te lanes is not re$uired#
2.7.= A-B Bus !aster
An AHB !us master has the most comple& !us interface in an AMBA s"stem#
"picall" an AMBA s"stem designer 'ould use pre designed !us masters and therefore
'ould not need to !e concerned 'ith the detail of the !us master interface#
Here the Ar!iter signals and the transfer signals 'ere mentioned in the !elo' data
flo' AHB !us master interface diagram#
Design and Verification of a Bus Bridge from OCP to AHB
,0
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
(i)ure 2.* A-B Bus !aster Interface .ia)ram
2.7.1> A-B Bus "&ae
An AHB !us slave responds to transfers initiated !" !us masters 'ithin the
s"stem# he slave uses a H+2?& select signal from the decoder to determine 'hen it
should respond to a !us transfer# All other signals re$uired for the transfer% such as the
address and control information% 'ill !e generated !" the !us master#
Design and Verification of a Bus Bridge from OCP to AHB
,6
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
(i)ure 2.+ A-B Bus "&ae Interface
Hence all the signals involved in the slave and decoder 'ere mentioned in the
a!ove AHB !us slave interface diagram#
Design and Verification of a Bus Bridge from OCP to AHB
,7
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
2.= "ummar%
he literature surve" is carried out 'ith merits and demerits of AHB and the
signal flo' diagram is identified#
he specification for the signals sho'n in the signal flo' diagram is identified
and its 'orking is e&plained 'ith the help of its !lock diagram#
he discussion on the overvie' of the AMBA-AHB operation 'as made 'hich
includes all the components involved in the AHB
#
Chapter 3 .esi)n of A!BA'A-B
Design and Verification of a Bus Bridge from OCP to AHB
,:
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
3.1 Introduction
he literature surve" on the AHB is made and the !asic signal flo' !lock diagram
is identified# In the mentioned dataflo' signal diagram% the !asic signals are identified
and are used in the simple read and 'rite and !urst operation in AHB Master and +lave#
Initiall" the 3inite +tate Machine (3+M) is developed and the modeling of the developed
3+M is done using the MHD?#
In this chapter% the design of AHB protocol is discussed and their simulations are
verified 'ith the !asic operation#
3.2 .esi)n of A!BA ' A-B
he AHB takes on man" characteristics of a standard plug-in !us# It@s a multi-
master 'ith ar!itration% putting the address on the !us% follo'ed !" the data# It has a data-
valid signal (H12AD>)#
his !us differs in that it has separate read (H1DAA) and 'rite (HHDAA) !uses
'hose connections are multiple&ed% rather than making use of a tri-state multiple
connection# AHB supports !ursts 'ith 6% 9% and 1: !eat !ursts and single transfers#
he notations used 'hile designing the AHB for the s"stem (ontrol signals are
mentioned in the a!le 0#1 and for others are listed in the a!le 0#1 and a!le 0#, 'hich
are as follo's#
)ransfer type +H)rans,
$ab&e 3.1 $ransfer t%pe ?-$rans@
-$rans Notations 6sed .escription
DD ID2 =o Data ransfer
1D =.=N+2<
he address and control signals
are unrelated to the previous transfer
11 +2<
he address is related to the
previous transfer
Design and Verification of a Bus Bridge from OCP to AHB
,;
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
HB-rst val-es
$ab&e 3.2 -Burst a&ues
-Burst .escription
DDD 1epresents Burst +i5e of 6
DD1 1epresents Burst +i5e of 9
D1D 1epresents Burst +i5e of 1:
3.2.1 "imp&e 3rite and 4ead Operation
he simple 'rite and read operation in AHB has the mandator" signals 'hose
specification is mentioned in the a!le ,#1#
.*M for AHB master
(i)ure 3.1 ("! for A-B master ' simp&e 8rite and read
he 3inite +tate Machine (3+M) for the AHB master simple 'rite and read
operation is developed and is sho'n in the 3igure 0#1#
Design and Verification of a Bus Bridge from OCP to AHB
IDL
!AD "!I#
$ontrol % "r!e&
' H(rant)%*
H!ead+%,
$ontrol % !d!e&
' H(rant)%*
H!ead+%*
H!ead+ %*
H!ead+%,
HAddr, HWData
& HWrite !
HAddr, Data"out
H#Data &
HWrite $
,9
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
AHB Master 'ill !e in ID?2 +tate at the initial stage and 'ill give the re$uest
signal to the ar!iter 'hich in turn provides the grant signal# Hence !ased on the control
and the grant signal% AHB Master either goes to H1I2 or 12AD state#
If control from the s"stem is a 'rite re$uest ((ontrol O BDD1C)% then the AHB
Master go H1I2 state and 'ill issue the address (HAddr) and input data (HHData) to
the slave and also makes the HHrite signal to high# .nce these signals are issued% it 'ill
'ait for the H1ead" signal 'hich 'ill come from the slave after finishing the operation#
.nce the H1ead" signal occurred% then the AHB Master 'ill go to the ID?2 state again#
+imilarl"% 'hen s"stem gives read re$uest ((ontrol O BD1DC)% master goes to the
12AD state and 'ill give address (HAddr) and make HHrite signal to ?o'# he data in
the given address 'ill !e read out !" the dataNout signal# Master go ID?2 state 'hen the
H1ead" signal is made high 'hich represents the operation got over#
.*M for AHB slave
(i)ure 3.2 ("! for A-B s&ae ' simp&e 8rite and read
Initiall"% all four AHB slave 'ill !e inactive and it 'ill get activated !" the +elect
(H+el&) signal from the decoder 'hich in turn !ased on the given address (HAddr)# .nce
Design and Verification of a Bus Bridge from OCP to AHB
I.,0
34I$
0
40A
.
-"e&1 A 1 B
-3rite A 1
H#ead% ! &
Hres& O'A(
H#ead% ! &
Hres& O'A(
H#ead% $
-"e&1 A 1 B
-3rite A >
"toreC!em A
-3.ata
-4.ata A
"toreC!em
,G
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
the slave is activated% !ased on HHrite status% slave ma" go either H1I2 or 12AD
state# he developed 3+M for the AHB slave is sho'n in the 3igure 0#,#
(ote
+lave go H1I2 state 'hen the HHrite signal is made High#
+lave go 12AD state 'hen the HHrite signal is made ?o'#
AHB +lave goes H1I2 state 'hen !oth H+el& and HHrite signals are made
high# In H1I2 state% slave 'ill 'rite the data to its internal memor" address location
given !" the master# .nec the data is 'ritten% then it 'ill issue the H1ead" signal and
response (H1esp) signal to I.FA>@ 'hich is an e&tra status sho'ing signal# In the same
'a"% 'hen HHrite O D% the AHB +lave 'ill go to the 12AD state from ID?2# In read
operation% slave 'ill fetch the data from its internal memor" for the given address
location and is given out through H1Data signal to the dataNout signal in master#
*im-lation res-lt for simple write and read
otall" there are four masters and slave are present in the design in 'hich one can
!e selected at a time !" Ar!iter and Decoder respectivel"# he simulation result for AHB
Master and +lave - +imple Hrite and 1ead is sho'n in the 3igure 0#0#
Here in the 'aveform% master is ena!led 'hich sends the re$uest to the ar!iter
'hich in turn provides the grant signal# hen the master gives the HAddr% HHData and
HHrite O 1 or HHrite O D !ased on the current operation# his information@s are given to
slave through IAddress and Hrite Data Mu&@ 'hose select line 'ill !e given !" the
HMaster signal that represents 'hich master is currentl" selected# he slave 'ill !e
activated 'ith respect to the given address !" the decoder# he slave activation can !e
indicated !" the H+el& signal and 'hich slave is activated can !e represented !" the
decodeNsel signal 'hich 'ill act as a select signal for the I1ead Data Mu&@#
(i)ure 3.3 3aeforms for A-B master and s&ae ' simp&e 8rite and read
Design and Verification of a Bus Bridge from OCP to AHB
0D
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
=o' !oth the master and slave 'ill !e in either 'rite or read state 'hich can !e
finished onl" 'hen the data is 'ritten to the memor" or the data is read out from the
memor"# his can !e indicated !" making the H1ead" signal high and the H1esp signal
to I.FA>@#
3.2.2 Burst Operation
he Burst operation in AHB has the mandator" signals such as H+i5e and HBurst%
'hose specification is mentioned in the a!le ,#1#
Basicall"% AHB !urst operation is that a se$uence of operation happens 'ith
respect to the H+i5e given and it supports onl" three !urst si5es 'hich are mentioned in
a!le 0#,# he si5e is acting as one of the inputs to the master during the !urst operation
and after each !urst operation% the master or slave 'ill go to the ID?2 state#
.*M for AHB master
(i)ure 3.4 ("! for A-B master burst operation
3+M developed for the AHB Master - Burst operation is sho'n in the 3igure 0#6
'hich has the clear vie' on the operation in a se$uence manner# Hhen 'rite re$uest
((ontrol O BD11C) is given and the ar!iter provides the grant signal in response to re$uest
signal% AHB Master goes to H1I2 state# Here the count signal is added 'hich 'ill !e
incremented onl" 'hen the H1ead" signal made high i#e# count increments after each
Design and Verification of a Bus Bridge from OCP to AHB
IDL
!AD
"!I#
Hread+ % ,
H!ead+ % * '
($ount%si-e)
H!ead+ % * '
($ount%si-e)
$ontrol % "r!e&
' H(rant)%*
$ontrol % !d!e&
' H(rant)%*
Hread+ % ,
H!ead+ % * '
($ount .% si-e)
HAddr, HSi)e,
HWData &
HWrite !
HAddr, HSi)e,
Data"out
H#Data &
HWrite $
H!ead+ % * '
($ount .% si-e)
01
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
operation and 'ill remain in the same state# Hhen !urst si5e is e$ual to the count% then
the master go ID?2 state that represents !urst operation is over#
In 1ead operation% read re$uest ((ontrol O B1DDC) is given 'hich leads to the
master to 12AD state in 'hich the stored data in the memor" is read out 'ith respect to
the given address to the slave# his output data is sent out through dataNout signal and
'hen count is e$ual to the !urst si5e% the master goes to ID?2 state#
.*M for AHB slave
he 3+M for the AHB +lave - Burst .peration is developed !ased on its
operation and is sho'n in the 3igure 0#7#
(i)ure 3.# ("! for A-B s&ae burst operation
In ID?2 state H1ead" 'ill !e made lo' and 'hen HHrite O 1 slave 'ill go
H1I2 state and check for the count# he 'ill get increment onl" 'hen the data is stored
in the memor" and if count is e$ual to the !urst si5e% then the slave 'ill go to the ID?2
state or it 'ill sta" in the H1I2 state itself# In the same 'a"% 'hen HHrite O D% slave
Design and Verification of a Bus Bridge from OCP to AHB
I.,0
34I$
0
40A
.
H#ead% $
"toreC!em A
-3.ata B
?Count A -Burst@
-"e&1 A 1 B
-3rite A 1
-"e&1 A 1 B
-3rite A >
H#ead% ! &
Hres& O'A(
-4.ata A
"toreC!em B
?CountA-Burst@
Count DA
-Burst
H#ead% ! &
Hres& O'A(
Count DA
-Burst@
0,
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
'ill go 12AD state and the data is fetched from memor"# .nce the fetching process over%
H1ead" is made high% H1esp is set to I.FA>@ and count 'ill check foe !urst si5e#
.nce the !urst operation is over i#e# count is e$ual to !urst si5e% then the count value
resets to 5ero#
*im-lation res-lts for b-rst operation
he !asic 'orking of AHB master and salve is discussed !ased on their 3+Ms and
in the design totall" four AHB master and slave are present# AHB supports !urst si5e of
onl" 6% 9 and 1:#
/, B-rst operation of si0e12
he simulation result for the AHB master and slave of !urst si5e 6 is sho'n in the
3igure 0#:#
he si5e is given as BDDDC 'hich represents the !urst si5e 6 and hence four
continuous 'rite or read operation happens# Here the count is introduced in order to
generate the address 'ith respect the given initial address and the count increment# he
operation remains the same as simple read and 'rite !ut the onl" change is that after each
operation% count 'ill check for the !urst si5e# Hhen the count is not e$ual to the !urst si5e
given% the count 'ill get incremented and the ne&t address is get generated !ased on
'hich the read or 'rite operation that currentl" performed is carried out# Hhen the count
is e$ual to !urst length% that represents the !urst operation over and count resets to 5ero#
Hence master and slave go ID?2 state#
HHrite signal 'ill !e maintained as High or ?o' throughout the !urst 'rite or
!urst read operation and is made don@t care after the !urst operation over# +imilarl"% the
H1ead" signal is also made high for each operation in the !urst 'hich is clearl" sho'n in
the 'aveform#
(i)ure 3.* 3aeform for A-B master and s&ae burst operation of siEeC4
3, B-rst operation of si0e14
Design and Verification of a Bus Bridge from OCP to AHB
00
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
Here the si5e is given as BDD1C 'hich represents the !urst si5e of 9 and this
contains the eight continuous operation of 'rite or read operation# he simulation result
for the 'rite operation is sho'n in the 3igure 0#;#
(i)ure 3.+ 3aeform for A-B master and s&ae burst 8rite operation of siEeC7
+imilarl" the Burst read operation of si5e 9 is sho'n in the 3igure 0#9 'hich
clearl" sho's the generation of 9 addresses and corresponding data is read out#
he slave 'ill go ID?2 state 'hen the memor" locations are full i#e# 'hen the
address value e&ceeds the num!er of memor" locations in a slave% then that slave 'ill go
to ID?2 and ne&t slave 'ill get activated#
(i)ure 3.7 3aeform for A-B master and s&ae burst read operation of siEeC7
5, B-rst operation of si0e1/6
he simulated 'aveforms for the !urst 'rite operation of si5e 1: is sho'n in the
3igure 0#G# Burst si5e O BD1DC is declared 'hich represents the !urst operation of si5e 1:
and hence the slave 'ill changes for ever" four count#
+ince the decoder is designed in such a 'a" that for ever" four addresses% the
decoder should select another slave and the current active slave should go to the ID?2%
provided the address generation should !e in the incrementing order# Also that each slave
'ill !e activated onl" !" the H+el& signal from the decoder and hence the 'rite operation
occurs in each slave memor" locations !ased on the given addresses#
(i)ure 3.= 3aeform for A-B master and s&ae burst 8rite operation of siEeC1*
he simulation 'aveform for the AHB Master and +lave Burst 1ead .peration of
si5eN1: is sho'n in the 3igure 0#1D# his clearl" represents the !urst read operation in
se$uence and as per the developed 3+M#
Design and Verification of a Bus Bridge from OCP to AHB
06
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
(i)ure 3.1> 3aeform for A-B master and s&ae burst read operation of siEeC1*
hus all the simulation results of AHB protocol are present and are discussed as
per the developed 3+Ms#
3.3 "ummar%
Based on the literature revie'% the 'orking of AHB masters and slaves is made
clear and on identified specifications the design is made#
Initiall" the 3+Ms are developed for !oth master and slave of AHB separatel"
'hich includes simple 'rite and read operation and !urst operation#
he modelling of the developed 3+Ms of AHB are made using MHD?#
3inall" the AHB is designed in such a 'a" that the transaction !et'een master
and slave is carried out 'ith proper dela" and timings#
he screen shots of the simulated 'aveform results are displa"ed and are
e&plained 'ith respect to the design !ehaviour#
Design and Verification of a Bus Bridge from OCP to AHB
07
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
Chapter 4 ' Conc&usions and 4ecommendations for (uture
3or/
his pro/ect 'ork presents the AMBA- Advanced High Performance Bus (AHB)
protocol design 'hich acts as an interface !et'een t'o different IP cores# In this 'ork%
initiall" the investigation on the AHB is carried out and the !asic commands and its
'orking are identified !ased on 'hich the signal flo' diagram and the specifications are
developed for designing the AMBA-AHB using MHD?# his AMBA-AHB 'ill include
t'o t"pes of operation such as +imple Hrite and 1ead and Burst .peration#
4.1 Conc&usion
he AMBA advanced microcontroller !us architecture specification defines an
.n-(hip (ommunications standard for designing high performance em!edded
microcontrollers# In this pro/ect 'e could design the intellectual properties of the
master and slave depending upon the specifications% data transfer and various
transfer modes that are supported !" AMBA !us architecture# Depending upon the
real time application these intellectual properties can !e used and design num!er
of masters and slaves that can !e used in the pro/ect#
he !asic aim of our pro/ect is to model the master and slave of AHB and 'e have
successfull" modeled !oth MA+21 and +?AM2 along 'ith internal memor"
design using MHD?#
he simulation result sho's that the communication !et'een different IP cores
using AHB is proper#
All of the commands and data are successfull" transferred from one IP core to the
other IP core using AMBA-AHB protocol# here is no loss of data or control
information#
Design and Verification of a Bus Bridge from OCP to AHB
0:
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
he AMBA-AHB !us supports the simple 'rite and read operation and the !urst
e&tension#
Based on the result o!tained% the !urst e&tension is seen to automate the address
generation# he initial address alone is provided to the protocol#
he Marious +cenarios for each component in the AMBA-AHB !us design are
verified effectivel" during the simulation 'it respect to its !ehavior#
Design and Verification of a Bus Bridge from OCP to AHB
0;