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Axi Protocol Basics

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Purna satya srinivas Vempala
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68 views

Axi Protocol Basics

Uploaded by

Purna satya srinivas Vempala
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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You are on page 1/ 6

BASICS OF AXI4 PROTOCOL

AXI 4:
• The Advanced eXtensible Interface (AXI) protocol, part of the AMBA
(Advanced Microcontroller Bus Architecture) specification from ARM, plays a
critical role in high-performance System-on-Chip (SoC) design.
• AXI is renowned for its flexibility, efficiency, and ability to support high-
speed and high-frequency data transactions, making it a fundamental component
in modern SoC architectures.
• It builds on the earlier AXI3 protocol by enhancing performance, flexibility,
scalability, and capability, particularly suited for high-bandwidth applications.
• AXI also includes a number of new features including out-of-order transactions,
unaligned data transfers, cache support signals, and a low-power interface.

KEY ENHANCEMENTS IN AXI4:


1. Consolidated Interfaces: AXI4 simplified the number of interfaces compared to
AXI3, offering different versions like AXI4, AXI4-Lite, and AXI4-Stream for
different use cases.
• AXI4: For high-performance memory-mapped interfaces.
• AXI4-Lite: A simpler version for low-bandwidth control register accesses.
• AXI4-Stream: For high-speed streaming data with minimal control overhead.

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2. Wider Data Buses: AXI4 increased support for wider data buses, from 32-bit up
to 1024-bit data paths, which is crucial for handling larger data sets in high-
performance computing.
3. Better Burst Support: AXI4 has better support for burst transactions (up to
256 data transfers per burst) and allows wrapping bursts, improving the
efficiency of bulk data transfers.
4. Memory-Mapped Interfaces: The primary focus of AXI4 is memory-mapped
communication, making it ideal for connecting processors, memory controllers,
and high-speed peripherals.

AXI CHANNELS :
There are five independent channels between an AXI master and slave. They are the:
1. Read address channel
2. Read data channel
3. Write address channel
4. Write data channel
5. Write response channel

AXI channels
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• The address channels are used to send address and control information while
performing a basic handshake between master and slave. The data channels are
where the information to be exchanged is placed.
• A master reads data from and writes data to a slave. Read response information
is placed on the read data channel, while write response information has a dedicated
channel. This way the master can verify a write transaction has been completed.
Figure shows an AXI master and slave connected via the five AXI channels.
• Every exchange of data is called a transaction. A transaction includes the address
and control information, the data sent, as well as any response information. The
actual data is sent in bursts which contain multiple transfers.

AXI TRANSACTIONS :
An AXI data transfer is called a transaction. Transactions can take the form of
reads or writes and include address/control information, data, and a response. The
data is sent in the form of bursts, which include multiple data items called beats. To
synchronise the sending and receiving of data, an AXI master and slave perform a
handshake at the beginning of a transaction using the READY and VALID signals.

HANDSHAKING MECHANISM :
In AXI4, the handshaking mechanism is crucial for ensuring that data is transferred
accurately between the master and slave devices. The protocol uses a valid/ready
handshake on all its channels (read/write address, data, and response).

Valid/Ready Handshake in AXI4 :


The handshaking mechanism revolves around two signals on each channel:
• VALID: Indicates that the sender (master or slave) has valid data or an address to
send.
• READY: Indicates that the receiver (slave or master) is ready to accept data or
the address.

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• The data transfer happens only when both the VALID and READY signals are
asserted (set to high).

Key Points:
• The master asserts the VALID signal when it has data or an address ready to
send.
• The slave asserts the READY signal when it is ready to receive that data or
address.
• A transaction is completed when both VALID and READY are asserted at the
same time.

HANDSHAKE PROCESS STEPS :


The handshake process follows a straightforward sequence:
1. The master asserts the VALID signal to indicate the availability of valid data.
2. The slave monitors the VALID signal and, if it is asserted and it is ready to
receive data, asserts its READY signal.

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3. When both the VALID and READY signals are high during the same clock cycle,
data transfer occurs.
4. After data transfer, the master can de-assert the VALID signal, indicating that the
data is sent, and the slave can also de-assert the READY signal if it no longer
wishes to accept data.

HANDSHAKING ON DIFFERENT CHANNELS :


AXI4 has five independent channels, and each channel uses the VALID/READY
handshake for communication.

a. Write Address Channel


• Master sends the write address on the address bus when AWVALID is high.
• Slave acknowledges the address when AWREADY is high, completing the address
handshake.

b. Write Data Channel


• Master sends data on the data bus when WVALID is high.
• Slave asserts WREADY when it's ready to accept the data, completing the data
transfer handshake.

c. Write Response Channel


• Slave sends a response after completing the write transaction using the BVALID
signal.
• Master acknowledges the response with BREADY, completing the handshake for
write response.

d. Read Address Channel


• Master sends the read address using ARVALID.
• Slave acknowledges the read address by asserting ARREADY, completing the
address transfer handshake.

e. Read Data Channel


• Slave sends the requested data using RVALID when data is ready.
• Master asserts RREADY when it is ready to accept the data, completing the
handshake for the read data.
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DIFFERENCE BETWEEN AXI3 AND AXI4?
- AXI3: Added features like separate read/write channels, pipelining, and burst
transfers for high-performance systems, AXI3 supports up to 16 beats.
- AXI4: Enhanced AXI3 with consolidated interfaces (AXI4, AXI4-Lite, AXI4-
Stream), wider data paths, and better burst transaction support, leading to
widespread adoption in modern SoCs, AXI4 supports Quality of Service (QoS),
AXI4 supports burst lengths of up to 256 beats.

ADVANTAGES OF AXI4 PROTOCOL


• High Performance: AXI4 supports high throughput, thanks to separate read and
write channels, allowing concurrent operations.
• Burst Transactions: Efficient data transfer is possible with support for burst
transfers, reducing latency and increasing bandwidth utilization.
• Low Latency: The protocol allows for low-latency transactions, which is essential
in real-time applications.
• Scalability: AXI4 is scalable and can be easily adapted for different bus widths,
data types, and system requirements.
• Flexibility: With support for out-of-order transactions and multiple masters/slaves,
AXI4 offers flexibility in complex SoC designs.

DISADVANTAGES OF AXI4 PROTOCOL


• Complex Implementation: While flexible, AXI4's protocol complexity can make
the design, implementation, and verification process more challenging, especially
for smaller, simpler designs.
• Higher Power Consumption: The additional features like burst transfers and
separate channels can result in higher power consumption compared to simpler bus
protocols.
• Not Ideal for Low-Performance Systems: For systems where simplicity, low
power, and minimal data bandwidth are more important, AXI4 may be over-
engineered.
• Requires Advanced Verification: Testing and verifying AXI4-compliant systems
require sophisticated tools and expertise due to its complexity and multiple
transaction types.

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