ddr3 Advantages1
ddr3 Advantages1
Products are warranted only to meet Microns production data sheet specifications.
Information, products and/or specifications are subject to change without notice. All information is provided on an AS IS basis without
warranties of any kind. Dates are estimates only. Drawings not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
DDR3 Advantages
4/8/2009 2
2009 Micron Technology, Inc. All rights reserved.
DDR3 Advantages
Lower power
Higher speed
Master reset
More performance
Larger densities
Modules for all applications
4/8/2009 3
2009 Micron Technology, Inc. All rights reserved.
Lower Power
Supply voltage reduced from 1.8V to1.5V
~30% reduction in power due to supply voltage alone
Lower I/O buffer power
34 ohm driver vs. 18 ohm driver
E
s
t
i
m
a
t
e
d
P
o
w
e
r
R
e
l
a
t
i
v
e
t
o
D
D
R
2
DDR2
800
DDR2
800
DDR3
1067
DDR3
1067
DDR2
667
DDR2
667
DDR3
800
DDR3
800
DDR3
1333
DDR3
1333
DDR2
533
DDR2
533
Source: Micron
DDR3
1600
DDR3
1600
4/8/2009 4
2009 Micron Technology, Inc. All rights reserved.
Designed for HighSpeed
Signaling
Improved pinout
Flyby architecture
READ and WRITE leveling
Data calibration through ZQ resistor
Dynamic ODT for improved WRITE signaling
2 DIMMs/channel at DDR3 frequencies
4/8/2009 5
2009 Micron Technology, Inc. All rights reserved.
Improved Pinout
Improved power delivery
More power and ground balls
Improved signal quality
Improved signal integrity
Improved power and ground
distribution
Improved signal referencing
Fully populated ball grid
Improved mechanical reliability
Improved D/Q array
Less D/Q skew
Tighter D/Q timing
DDR2 DDR3
4/8/2009 6
2009 Micron Technology, Inc. All rights reserved.
Improved Module Layout
Flyby architecture for C/A, control, clocks
Improved signal integrity for high speeds
Onmodule termination
Used on UDIMM, SODIMM, RDIMM
Not used on DDR2
not needed at lower frequencies
4/8/2009 7
2009 Micron Technology, Inc. All rights reserved.
READ/WRITE Leveling
Allows for controller to determine the time delta for data
command to data output of each DRAM (byte lane)
Enables controller to capture data for each byte lane
Enables controller to adjust receiver timing per byte lane
4/8/2009 8
2009 Micron Technology, Inc. All rights reserved.
Master Reset
Improved system stability
Eliminates unknown startup
states
Known initialization and
recovery state
Cold boot reset
Warm boot reset
Removes controller burden to
ensure no illegal commands
4/8/2009 9
2009 Micron Technology, Inc. All rights reserved.
Increased Peak Performance
2X the bandwidth of DDR2
Component per pin
800 MT/s to 1600 MT/s
Bus bandwidth
6400 MT/s to 12,800 MT/s
8 banks vs. 4 banks
More open banks for
backtoback access
Hide turnaround time
Hide
t
RP
0
1
2
3
4
5
6
7
8
3
2
0
0
4
2
0
0
5
3
0
0
6
4
0
0
8
5
0
0
1
0
6
0
0
1
2
8
0
0
DDR2 DDR3
4/8/2009 10
2009 Micron Technology, Inc. All rights reserved.
DDR3 Market
DDR3 market dynamics
512Mb/1Gb crossover
1Gb/2Gb crossover
DDR3 life from 2007 through 2014
Source: Micron Marketing
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
2005 2006 2007 2008 2009 2010 2011 2012
4 Gb
2 Gb
1 Gb
512 Mb
256 Mb
128 Mb
64 Mb
16 Mb
512Mb to 1Gb price parity
2H08
1Gb to 2Gb price parity 2H11
4/8/2009 11
2009 Micron Technology, Inc. All rights reserved.
DDR3 Ramp
2007 2008 2009 2010
DDR 14% 3% 2% 1%
DDR2 83% 78% 64% 33%
DDR3 3% 19% 34% 60%
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
2007 2008 2009 2010 2011 2012
0%
50%
100%
150%
200%
250%
DDR4
DDR3
DDR2
DDR
Premium
Source: Micron Marketing
DDR2 to DDR3 Crossover
4/8/2009 12
2009 Micron Technology, Inc. All rights reserved.
Maximum* Module Density
Component
Density
Module
Density
256Mb 512Mb 1Gb 2Gb 4Gb 8Gb
DDR2 UDIMM (18)
SODIMM(16)
RDIMM(36)
FBDIMM(36)
512MB
512MB
1GB
1 GB
1GB
1GB
2 GB
2GB
2 GB
2 GB
4GB
4 GB
4 GB
4 GB
8 GB
8GB
n/a** n/a
DDR3 UDIMM (18)
SODIMM(16)
RDIMM(36)
FBDIMM(36)
n/a 1GB
1GB
2 GB
2 GB
2 GB
2 GB
4 GB
4 GB
4 GB
4 GB
8 GB
8GB
8 GB
8 GB
16GB
16GB
16 GB
16 GB
32GB
32GB
*Maximum density requires stacked and/or high component count
planar versions of modules
** 4Gb is a JEDEC standard; Micron has no plans to support it
4/8/2009 13
2009 Micron Technology, Inc. All rights reserved.
DDR3 Modules for All Applications
1H07 2H07 1H08 2H08 1H09 2H09
Desktop
Notebook
Server
Networking
Small Outline DIMM
Unbuffered
DIMM
Registered DIMM
Very Low Profile DIMM
U
n
b
u
f
f
e
r
e
d
D
I
M
M
Fully Buffered DIMM
4/8/2009 14
2009 Micron Technology, Inc. All rights reserved.
Summary
DDR3 provides more bandwidth at lower power
Package, pinout, and signaling improvements for
higherspeed
operation
Master reset for improved system stability
Larger densities
Modules for all applications