149

Name _______________________________________ Class ______________ Date

Objectives Upon completion of this laboratory exercise, you should be able to:
Write a VHDL file to implement a 5-bit EVEN parity generator.
Write a set of simulation criteria to verify the correctness of the parity generator
design.
Create a Quartus II simulation based on your simulation criteria.
Modify the 5-bit parity generator to implement a 5-bit parity checker.
Create a test circuit in the Quartus II Block Editor to test the parity generator and
checker.
Lab
17
Parity Generators and Checkers
Reference
Equipment
Required
Dueck, Robert K., Digital Design with CPLD Applications and VHDL, 2/e
Chapter 6: Combinational Logic Functions
6.6 Parity Generators and Checkers
CPLD Trainer:
Altera UP-2 circuit board with ByteBlaster Download cable, or
DeVry eSOC board with Straight-Through Parallel Port cable, or
RSR PLDT-2 circuit board with Straight-Through Parallel Port cable, or
equivalent CPLD trainer board with Altera EPM7128S CPLD
Quartus II Web Edition software
AC adapter, minimum output: 7 VDC, 250 mA DC
Anti-static wrist strap
#22 solid-core wire
Wire strippers
Experimental Notes

Parity Generator
A parity generator can be implemented in VHDL using a GENERATE statement to instantiate a
series of XOR functions. For example, a 5-bit EVEN parity generator can be implemented with a
design entity having the structure shown in Figure 17.1. In general, each portion of the parity
circuit is described by the equation p(i) = d(i) p(i 1).
Parity Checker
A parity checker compares a parity bit from a parity generator with a parity bit created from the
original data applied to the generator. A parity generator can be modified to create a parity
checker. Figure 17.2 shows the circuit. In addition to the Exclusive OR equation given for the
parity generator, one more equation is required: p(0) = d(0) p
in
.
Procedure

Design Entry and Simulation (Parity Generator)

1. Write a VHDL file that describes the circuit of the 5-bit parity generator shown in
Figure 17.1. Use a GENERATE statement and the predefined attribute ('RIGHT) to define
the ranges of the ports and signals in the file. (Refer to Example 6.25 in main text.)
2. Save the VHDL file as drive:\qdesigns\labs\lab17\parity_gen5\parity_gen5.vhd. Use the
file to create a new project.
3. Write a set of simulation criteria that test the correctness of the design. Use these criteria to
create a simulation in Quartus II. Show the simulation to your instructor.
Simulation Criteria
Instructors Initials _________
150 Lab 17
p
in
d(0)
d(1)
d(2)
d(3)
p(0)
p(1)
p(2)
p(3)
d(4)
p(4) = pe
Figure 17.2 5-Bit Parity Checker
d(0)
d(1)
d(2)
d(3)
d(4)
p(1)
p(2)
p(3)
p(4) = pe
Figure 17.1 5-Bit Parity Generator
Parity Test Circuit
Figure 17.3 shows a normal setup for a 5-bit parity EVEN generator and checker. The same data
bits are applied to both the parity generator and checker. The generator determines the EVEN
parity bit and applies it to the parity checker, which compares it to a new parity bit determined
from the original input data. Separate outputs in the circuit monitor the original parity bit,
PE_GEN, and the output of the parity checker, P
E
.
Parity Generators and Checkers 151
D
0
D
1
D
2
D
3
D
4
P
E
Parity Generator
D
0
D
1
D
2
D
3
D
4
P
E
Parity Checker
P
IN
P
E
D
0
D
1
D
2
D
3
D
4
PE_GEN
Figure 17.3 Normal Set up for Parity Generation and Checking
This circuit is not suitable for testing how the parity checker reacts to parity errors. The
problem is that if the parity checker and parity generator are both working, the P
E
light never
comes on. We need a way to artificially introduce errors into the system so that we can properly
test the response of the parity checker.
Figure 17.4 shows one possibility. Two multiplexers are inserted in the lines connecting D
0
and D
1
to the parity checker. The multiplexers can send normal data or error data to the parity
checker. When Error Select 0 = 0, parity bit D
0
is the same at both the generator and the checker.
When Error Select 0 = 1, the parity checker bit D
0
is determined by the status of the logic switch
at Error 0. This may or may not be the same as the data at parity generator bit D
0
. If they are
different, an error should be detected by the parity checker. The same arrangement also applies
for the multiplexer for D
1
.
1. Create a folder called drive:\qdesigns\labs\lab17\parity5_test\. Use the Quartus II New
Project Wizard (File menu) to create a new project in the folder.
2. Copy the VHDL file parity5_gen.vhd to the new folder and use it to create a symbol. Add
the file to the active project.
3. Modify the 5-bit parity generator to make a 5-bit parity checker. Save the file as
parity_chk5.vhd. (Make sure to add the file to the project.) Create a symbol for the file.
4. Create a circuit for a 2-to-1 multiplexer and save it in the project folder, making sure to add
the file to the project. (The example in this laboratory exercise uses a multiplexer created
from a Block Diagram File called 2to1mux.bdf.) Create a symbol for the multiplexer.
152 Lab 17
D
0
D
1
D
2
D
3
D
4
P
E
Parity Generator
D
0
D
1
D
2
D
3
D
4
P
E
Parity Checker
P
IN
P
E
D
0
D
1
D
2
D
3
D
4
PE_GEN
Error Select 1
Error 1
Error Select 0
Error 0
Y
D
0
D
1
S
Y
D
0
D
1
S
1
0
1
0
Logic
Switches
Two MUXs introduce deliberate
errors to check circuit
Figure 17.4 Test Circuit for Parity Generation and Checking
5. Create a Block Diagram File, as in Figure 17.5 (Altera UP-2 or DeVry eSOC) or Figure 17.6
(RSR PLDT-2). Save the file as:
drive:\qdesigns\labs\lab17\parity 5_test\parity5_test.bdf.
The pe output in the parity checker in Figure 17.5 is inverted. (This can be done by
highlighting the block, then right-clicking and selecting Properties. In the Ports tab,
select pe, and click All in the Inversion box.) This and the other NOT gates are required
for the Altera UP-2 and DeVry eSOC boards to make the board LEDs active-HIGH.
Both Figure 17.5 and Figure 17.6 make use of an LCELL buffer. This component, shown
in detail in Figure 17.7, allows us to direct three of the five elements of the input bus
d[0..4] to the parity checker and the other two elements to the multiplexers. The
component can be inserted in the Block Diagram File by typing LCELL in the Symbol
dialog box.
6. Compile the parity generator/checker test file. Add pin numbers, as listed in Tables 17.1
through 17.3 at the end of this laboratory exercise. Compile the file again and download it to
the CPLD test board.
7. Set err_sel0 and err_sel1 both to 0 so that the input data is the same for both the parity
generator and parity checker. Test some combinations of data input. For each combination,
note whether the number of 1s at the data inputs is ODD or EVEN. Which condition causes
the pe_gen light to come on? The pe light should not come on for any combination. Why?
Show your instructor the operation of the circuit and explain the behavior of pe and pe_gen.
Instructors Initials _________
Note
Note
Parity Generators and Checkers 153
Figure 17.5 Parity Test Circuit (Altera UP-2 and DeVry eSOC)
Figure 17.6 Parity Test Circuit (RSR PLDT-2)
8. Set err_sel0 and err_sel1 both to 1 so that d[0] and d[1] for the parity checker are now set
by the inputs error0 and error1. Test some combinations of data that include the following
cases:
Error on d[0]: d[0] (generator) is different from d[0] (checker), but d[1] (generator) is
the same as d[1] (checker)
Error on d[1]: d[1] (generator) is different from d[1] (checker), but d[0] (generator) is
the same as d[0] (checker)
Errors on d[0] and d[1]: d[0] (generator) is different from d[0] (checker) and d[1]
(generator) is different from d[1] (checker)
How is an error on one bit shown on the pe output? How are errors on two bits shown on the
pe output? What does this say about the ability of a parity checker to detect an ODD or EVEN
number of errors? Demonstrate the operation of the circuit to your instructor and explain the
behavior of the pe output of the parity checker.
Instructors Initials _________
154 Lab 17
Figure 17.7 LCELL buffer
Table 17.1 EPM7128LC84-7 Pin Assignments
Altera UP-2 Board
DIP Switches
Function Pin Function Pin
d[0] 34 err_sel0 28
d[1] 33 error0 29
d[2] 36 30
d[3] 35 31
d[4] 37 57
40 55
39 err_sel1 56
41 error1 54
LED Outputs
Function Pin Function Pin
d_out[0] 44 nd_chk[0] 80
d_out[1] 45 nd_chk[1] 81
d_out[2] 46 nd_chk[2] 4
d_out[3] 48 nd_chk[3] 5
d_out[4] 49 nd_chk[4] 6
unused[1] 50 unused[3] 8
unused[2] 51 unused[4] 9
pe_gen 52 pe 10
Parity Generators and Checkers 155
Table 17.2 EPM7128LC84-7 Pin Assignments
RSR PLDT-2 Board
DIP Switches
Function Pin Function Pin
d[0] 34 err_sel0 28
d[1] 33 error0 29
d[2] 36 30
d[3] 35 31
d[4] 37 57
40 55
39 err_sel1 56
41 error1 54
LED Outputs
Function Pin Function Pin
d_out[0] 44 d_chk[0] 80
d_out[1] 45 d_chk[1] 81
d_out[2] 46 d_chk[2] 4
d_out[3] 48 d_chk[3] 5
d_out[4] 49 d_chk[4] 6
unused[1] 50 unused[3] 8
unused[2] 51 unused[4] 9
pe_gen 52 pe 10
Table 17.3 EPM7128LC84-7 Pin Assignments
DeVry eSOC Board
DIP Switches
Function Pin Function Pin
d[0] 50 err_sel0 60
d[1] 51 error0 61
d[2] 52 63
d[3] 54 64
d[4] 55 65
56 67
57 err_sel1 68
58 error1 69
LED Outputs
Function Pin Function Pin
d_out[0] 4 nd_chk[0] 16
d_out[1] 5 nd_chk[1] 17
d_out[2] 8 nd_chk[2] 18
d_out[3] 9 nd_chk[3] 20
d_out[4] 10 nd_chk[4] 21
unused[1] 11 unused[3] 22
unused[2] 12 unused[4] 24
pe_gen 15 pe 25