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Lab 7 DLD

This document describes a lab experiment on implementing parity generators and checkers. The objectives are to introduce parity generators, explain the uses of parity checkers and generators, and implement a parity checker and generator. The lab components include a breadboard, leads, digital trainer and LS7486 IC. The procedures generate even and odd parity, check for errors in even and odd parity, and verify the circuits. Circuits are shown for even and odd parity generators and checkers. The conclusions are that parity generators and checkers were learned about and implemented in the lab.

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Noman Khan
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167 views6 pages

Lab 7 DLD

This document describes a lab experiment on implementing parity generators and checkers. The objectives are to introduce parity generators, explain the uses of parity checkers and generators, and implement a parity checker and generator. The lab components include a breadboard, leads, digital trainer and LS7486 IC. The procedures generate even and odd parity, check for errors in even and odd parity, and verify the circuits. Circuits are shown for even and odd parity generators and checkers. The conclusions are that parity generators and checkers were learned about and implemented in the lab.

Uploaded by

Noman Khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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LAB NUMBER 7

 TITLE
 Implementation/Design of Parity Generator & Checker.
 OBJECTIVES
 Introduction to parity generators.
 Learn the uses of parity checkers & generators.
 Implementation of parity checker & Generator.
 COMPONENTS
 Bread Board
 Leads
 Digital Trainer
 LS 7486
 INTRODUCTION
Even Parity Generator
A 3-bit message is to be transmitted with an even parity bit. Let the three inputs A, B and C are
applied to the circuits and output bit is the parity bit P. The total number of 1s must be even, to
generate the even parity bit P.
Odd Parity Generator
A 3-bit data is to be transmitted with an odd parity bit. The three inputs are A, B and C and P is
the output parity bit. The total number of bits must be odd in order to generate the odd parity
bit.
Even Parity Checker
A three input message along with even parity bit is generated at the transmitting end. These 4
bits are applied as input to the parity checker circuit which checks the possibility of error on the
data. Since the data is transmitted with even parity, four bits received at circuit must have an
even number of 1s.If any error occurs, the received message consists of odd number of 1s. The
output of the parity checker is denoted by PEC (parity error check)
Odd Parity Checker
A three bit message along with odd parity bit is transmitted at the transmitting end. Odd parity
checker circuit receives these 4 bits and checks whether any error are present in the data.If the
total number of 1s in the data is odd, then it indicates no error, whereas if the total number of
1s is even then it indicates the error since the data is transmitted with odd parity at transmitting
end.
 PROCEDURE
 First take ic’s, wire and design the circuit on the breadboard according to the Requirement.
 First generate even and odd parity.
 Then check the error of even and odd parity.
 Then turn on and off the switches for the verification of gates.
 RESULTS
Even Parity Generator

Odd Parity Generator

P = A ⊕ B Ex-NOR C
Even Parity Checker
Odd Parity Checker

PEC = (A Ex-NOR B) Ex-NOR (C Ex-NOR D)


 CIRCUIT
Even Parity Generator

Odd Parity Generator

Even Parity Checker

Odd Parity Checker


 CONCLUSIONS
In this lab we have learned about parity generators. Learned the uses of parity checkers &
generators. And Implemented parity checker & Generator in the lab.
 REFRENCE
 www.googleimages.com
 Www.Wikipedia.com
 https://www.electronicshub.org/parity-generator-and-parity-check/

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