RT8841

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DS8841-01 April 2011 www.richtek.com
4/3/2/1-Phase PWM Controller for High-Density Power Supply
General Descri pti on
The RT8841 is a 4/3/2/1-phase synchronous buck
controller with 2 integrated MOSFET drivers for VR11 CPU
power application. RT8841 uses differential inductor DCR
current sense to achieve phase current balance and active
voltage positioning. Other features include adjustable
operating frequency, adjustable soft start, power good
indication, external error-amp compensation, over voltage
protection, over current protection and enable/shutdown
for various applications. RT8841 comes to a small footprint
with WQFN-40L 6x6 package
Features
12V Power Supply Voltage
4/3/2/1-Phase Power Conversion
2 Embedded MOSFET Drivers
Internal Regulated 5V Output
VID Tables for Intel VRD11/VRD10.x and AMD K8,
K8_M2 CPUs
Continuous Differential Inductor DCR Current Sense
Adjustable Soft Start
Adjustable Frequency
Power Good Indication
Adjustable Over Current Protection
Over Voltage Protection
Small 40-Lead WQFN Package
RoHS Compliant and 100% Lead(Pb)-Free
Appl i cati ons
Desktop CPU Core Power
Low Voltage, High Current DC/ DC Converter
Orderi ng Informati on
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/J EDEC J -STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Pin Configurations
WQFN-40L 6x6
(TOP VIEW)
BOOT1
UGATE1
PHASE1
LGATE1
VCC12
LGATE2
PHASE2
UGATE2
BOOT2
PWM3
FBRTN
SS/EN
ADJ
FB
OFS
RT
IMAX
GND
I
S
P
4
I
S
N
4
I
S
P
3
I
S
P
2
I
S
N
2
I
S
N
1
I
S
P
1
V
C
C
5
P
W
M
4
V
I
D
0
V
I
D
2
V
I
D
3
V
I
D
5
V
I
D
6
V
I
D
7
E
N
/
V
T
T
P
W
R
G
D
V
I
D
1
I
S
N
3
30
29
28
27
26
25
24
23
22
21
31 32 33 34 35 36 37 38 39 40
1
2
3
4
5
6
7
8
9
10
20 19 18 17 16 15 14 13 12 11
GND
COMP
V
I
D
4
VIDSEL
41
Package Type
QW : WQFN-40L 6x6 (W-Type)
RT8841
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
RT8841
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Typical Application Circuit
1
9
2
9
2
8
2
7
9 7 8
1
7
2
2
2
3
2
4
1
3
2
1
2
5
1
5
A
D
J
V
C
C
5
R
T
U
G
A
T
E
1
U
G
A
T
E
2
I
S
N
1
R
T
8
8
4
1
O
F
S
I
M
A
X
B
O
O
T
2
L
G
A
T
E
1
I
S
P
2
S
S
/
E
N
P
H
A
S
E
2
I
S
N
2
C
O
M
P
4
3
0
F
B
R
T
N
B
O
O
T
1
P
W
M
3
3 1
6
5 2 2
6
P
H
A
S
E
1
L
G
A
T
E
2
I
S
N
3
V
C
C
1
2
I
S
P
1
1
8
L
3
1
2
V
I
S
P
3
1
4
P
W
M
4
2
0
V
C
O
R
E
L
4
1
2
V
N
T
C
V
C
C
P
W
M
B
O
O
T
U
G
A
T
E
P
H
A
S
E
L
G
A
T
E
L
1
1
2
V
1
2
V
G
N
D
V
C
C
P
W
M
B
O
O
T
U
G
A
T
E
P
H
A
S
E
L
G
A
T
E
L
2
1
2
V
1
2
V
G
N
D
L
O
A
D
F
B
6
I
S
N
4
I
S
P
4
1
1
1
2
G
N
D
1
2
V
3
3

t
o

4
0
V
I
D
[
7
:
0
]
3
2
E
N
/
V
T
T
1
V
I
D
S
E
L
3
1
P
W
R
G
D
R
T
9
6
1
9
R
T
9
6
1
9
1
0
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Table 1. Output Voltage Program (VRD10.x + VID6)
To be continued
Pin Name
VID4 VID3 VID2 VID1 VID0 VID5 VID6
Nominal Output Voltage DACOUT
0 1 0 1 0 1 1 1.60000V
0 1 0 1 0 1 0 1.59375V
0 1 0 1 1 0 1 1.58750V
0 1 0 1 1 0 0 1.58125V
0 1 0 1 1 1 1 1.57500V
0 1 0 1 1 1 0 1.56875V
0 1 1 0 0 0 1 1.56250V
0 1 1 0 0 0 0 1.55625V
0 1 1 0 0 1 1 1.55000V
0 1 1 0 0 1 0 1.54375V
0 1 1 0 1 0 1 1.53750V
0 1 1 0 1 0 0 1.53125V
0 1 1 0 1 1 1 1.52500V
0 1 1 0 1 1 0 1.51875V
0 1 1 1 0 0 1 1.51250V
0 1 1 1 0 0 0 1.50625V
0 1 1 1 0 1 1 1.50000V
0 1 1 1 0 1 0 1.49375V
0 1 1 1 1 0 1 1.48750V
0 1 1 1 1 0 0 1.48125V
0 1 1 1 1 1 1 1.47500V
0 1 1 1 1 1 0 1.46875V
1 0 0 0 0 0 1 1.46250V
1 0 0 0 0 0 0 1.45625V
1 0 0 0 0 1 1 1.45000V
1 0 0 0 0 1 0 1.44375V
1 0 0 0 1 0 1 1.43750V
1 0 0 0 1 0 0 1.43125V
1 0 0 0 1 1 1 1.42500V
1 0 0 0 1 1 0 1.41875V
1 0 0 1 0 0 1 1.41250V
1 0 0 1 0 0 0 1.40625V
1 0 0 1 0 1 1 1.40000V
1 0 0 1 0 1 0 1.39375V
1 0 0 1 1 0 1 1.38750V
1 0 0 1 1 0 0 1.38125V
1 0 0 1 1 1 1 1.37500V
1 0 0 1 1 1 0 1.36875V
1 0 1 0 0 0 1 1.36250V

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Pin Name
VID4 VID3 VID2 VID1 VID0 VID5 VID6
Nominal Output Voltage DACOUT
1 0 1 0 0 0 0 1.35625V
1 0 1 0 0 1 1 1.35000V
1 0 1 0 0 1 0 1.34375V
1 0 1 0 1 0 1 1.33750V
1 0 1 0 1 0 0 1.33125V
1 0 1 0 1 1 1 1.32500V
1 0 1 0 1 1 0 1.31875V
1 0 1 1 0 0 1 1.31250V
1 0 1 1 0 0 0 1.30625V
1 0 1 1 0 1 1 1.30000V
1 0 1 1 0 1 0 1.29375V
1 0 1 1 1 0 1 1.28750V
1 0 1 1 1 0 0 1.28125V
1 0 1 1 1 1 1 1.27500V
1 0 1 1 1 1 0 1.26875V
1 1 0 0 0 0 1 1.26250V
1 1 0 0 0 0 0 1.25625V
1 1 0 0 0 1 1 1.25000V
1 1 0 0 0 1 0 1.24375V
1 1 0 0 1 0 1 1.23750V
1 1 0 0 1 0 0 1.23125V
1 1 0 0 1 1 1 1.22500V
1 1 0 0 1 1 0 1.21875V
1 1 0 1 0 0 1 1.21250V
1 1 0 1 0 0 0 1.20625V
1 1 0 1 0 1 1 1.20000V
1 1 0 1 0 1 0 1.19375V
1 1 0 1 1 0 1 1.18750V
1 1 0 1 1 0 0 1.18125V
1 1 0 1 1 1 1 1.17500V
1 1 0 1 1 1 0 1.16875V
1 1 1 0 0 0 1 1.16250V
1 1 1 0 0 0 0 1,15625V
1 1 1 0 0 1 1 1.15000V
1 1 1 0 0 1 0 1.14375V
1 1 1 0 1 0 1 1.13750V
1 1 1 0 1 0 0 1.13125V
1 1 1 0 1 1 1 1.12500V
1 1 1 0 1 1 0 1.11875V
Table 1. Output Voltage Program (VRD10.x + VID6)
To be continued
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Pin Name
VID4 VID3 VID2 VID1 VID0 VID5 VID6
Nominal Output Voltage DACOUT
1 1 1 1 0 0 1 1.11250V
1 1 1 1 0 0 0 1.10625V
1 1 1 1 0 1 1 1.10000V
1 1 1 1 0 1 0 1.09375V
1 1 1 1 1 0 1 OFF
1 1 1 1 1 0 0 OFF
1 1 1 1 1 1 1 OFF
1 1 1 1 1 1 0 OFF
0 0 0 0 0 0 1 1.08750V
0 0 0 0 0 0 0 1.08125V
0 0 0 0 0 1 1 1.07500V
0 0 0 0 0 1 0 1.06875V
0 0 0 0 1 0 1 1.06250V
0 0 0 0 1 0 0 1.05625V
0 0 0 0 1 1 1 1.05000V
0 0 0 0 1 1 0 1.04375V
0 0 0 1 0 0 1 1.03750V
0 0 0 1 0 0 0 1.03125V
0 0 0 1 0 1 1 1.02500V
0 0 0 1 0 1 0 1.01875V
0 0 0 1 1 0 1 1.01250V
0 0 0 1 1 0 0 1.00625V
0 0 0 1 1 1 1 1.00000V
0 0 0 1 1 1 0 0.99375V
0 0 1 0 0 0 1 0.98750V
0 0 1 0 0 0 0 0.98125V
0 0 1 0 0 1 1 0.97500V
0 0 1 0 0 1 0 0.96875V
0 0 1 0 1 0 1 0.96250V
0 0 1 0 1 0 0 0.95625V
0 0 1 0 1 1 1 0.95000V
0 0 1 0 1 1 0 0.94375V
0 0 1 1 0 0 1 0.93750V
0 0 1 1 0 0 0 0.93125V
0 0 1 1 0 1 1 0.92500V
0 0 1 1 0 1 0 0.91875V
0 0 1 1 1 0 1 0.91250V
0 0 1 1 1 0 0 0.90625V
0 0 1 1 1 1 1 0.90000V

To be continued
Table 1. Output Voltage Program (VRD10.x + VID6)
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Pin Name
VID4 VID3 VID2 VID1 VID0 VID5 VID6
Nominal Output Voltage DACOUT
0 0 1 1 1 1 0 0.89375V
0 1 0 0 0 0 1 0.88750V
0 1 0 0 0 0 0 0.88125V
0 1 0 0 0 1 1 0.87500V
0 1 0 0 0 1 0 0.86875V
0 1 0 0 1 0 1 0.86250V
0 1 0 0 1 0 0 0.85625V
0 1 0 0 1 1 1 0.85000V
0 1 0 0 1 1 0 0.84375V
0 1 0 1 0 0 1 0.83750V
0 1 0 1 0 0 0 0.83125V

Table 1. Output Voltage Program (VRD10.x + VID6)
Note: (1) 0 : Connected to GND
(2) 1 : Open
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To be continued
Table 2. Output Voltage Program (VRD11)
Pi n Name Nominal Out put Voltage
DACOUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
0 0 0 0 0 0 0 0 OFF
0 0 0 0 0 0 0 1 OFF
0 0 0 0 0 0 1 0 1.60000V
0 0 0 0 0 0 1 1 1.59375V
0 0 0 0 0 1 0 0 1.58750V
0 0 0 0 0 1 0 1 1.58125V
0 0 0 0 0 1 1 0 1.57500V
0 0 0 0 0 1 1 1 1.56875V
0 0 0 0 1 0 0 0 1.56250V
0 0 0 0 1 0 0 1 1.55625V
0 0 0 0 1 0 1 0 1.55000V
0 0 0 0 1 0 1 1 1.54375V
0 0 0 0 1 1 0 0 1.53750V
0 0 0 0 1 1 0 1 1.53125V
0 0 0 0 1 1 1 0 1.52500V
0 0 0 0 1 1 1 1 1.51875V
0 0 0 1 0 0 0 0 1.51250V
0 0 0 1 0 0 0 1 1.50625V
0 0 0 1 0 0 1 0 1.50000V
0 0 0 1 0 0 1 1 1.49375V
0 0 0 1 0 1 0 0 1.48750V
0 0 0 1 0 1 0 1 1.48125V
0 0 0 1 0 1 1 0 1.47500V
0 0 0 1 0 1 1 1 1.46875V
0 0 0 1 1 0 0 0 1.46250V
0 0 0 1 1 0 0 1 1.45625V
0 0 0 1 1 0 1 0 1.45000V
0 0 0 1 1 0 1 1 1.44375V
0 0 0 1 1 1 0 0 1.43750V
0 0 0 1 1 1 0 1 1.43125V
0 0 0 1 1 1 1 0 1.42500V
0 0 0 1 1 1 1 1 1.41875V
0 0 1 0 0 0 0 0 1.41250V
0 0 1 0 0 0 0 1 1.40625V
0 0 1 0 0 0 1 0 1.40000V
0 0 1 0 0 0 1 1 1.39375V
0 0 1 0 0 1 0 0 1.38750V
0 0 1 0 0 1 0 1 1.38125V
0 0 1 0 0 1 1 0 1.37500V
0 0 1 0 0 1 1 1 1.36875V

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To be continued
Pin Name Nominal Output Voltage
DACOUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
0 0 1 0 1 0 0 0 1.36250V
0 0 1 0 1 0 0 1 1.35625V
0 0 1 0 1 0 1 0 1.35000V
0 0 1 0 1 0 1 1 1.34375V
0 0 1 0 1 1 0 0 1.33750V
0 0 1 0 1 1 0 1 1.33125V
0 0 1 0 1 1 1 0 1.32500V
0 0 1 0 1 1 1 1 1.31875V
0 0 1 1 0 0 0 0 1.31250V
0 0 1 1 0 0 0 1 1.30625V
0 0 1 1 0 0 1 0 1.30000V
0 0 1 1 0 0 1 1 1.29375V
0 0 1 1 0 1 0 0 1.28750V
0 0 1 1 0 1 0 1 1.28125V
0 0 1 1 0 1 1 0 1.27500V
0 0 1 1 0 1 1 1 1.26875V
0 0 1 1 1 0 0 0 1.26250V
0 0 1 1 1 0 0 1 1.25625V
0 0 1 1 1 0 1 0 1.25000V
0 0 1 1 1 0 1 1 1.24375V
0 0 1 1 1 1 0 0 1.23750V
0 0 1 1 1 1 0 1 1.23125V
0 0 1 1 1 1 1 0 1.22500V
0 0 1 1 1 1 1 1 1.21875V
0 1 0 0 0 0 0 0 1.21250V
0 1 0 0 0 0 0 1 1.20625V
0 1 0 0 0 0 1 0 1.20000V
0 1 0 0 0 0 1 1 1.19375V
0 1 0 0 0 1 0 0 1.18750V
0 1 0 0 0 1 0 1 1.18125V
0 1 0 0 0 1 1 0 1.17500V
0 1 0 0 0 1 1 1 1.16875V
0 1 0 0 1 0 0 0 1.16250V
0 1 0 0 1 0 0 1 1.15625V
0 1 0 0 1 0 1 0 1.15000V
0 1 0 0 1 0 1 1 1.14375V
0 1 0 0 1 1 0 0 1.13750V
0 1 0 0 1 1 0 1 1.13125V
0 1 0 0 1 1 1 0 1.12500V
0 1 0 0 1 1 1 1 1.11875V
Table 2. Output Voltage Program (VRD11)
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To be continued
Pin Name Nominal Out put Voltage
DACOUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
0 1 0 1 0 0 0 0 1.11250V
0 1 0 1 0 0 0 1 1.10625V
0 1 0 1 0 0 1 0 1.10000V
0 1 0 1 0 0 1 1 1.09375V
0 1 0 1 0 1 0 0 1.08750V
0 1 0 1 0 1 0 1 1.08125V
0 1 0 1 0 1 1 0 1.07500V
0 1 0 1 0 1 1 1 1.06875V
0 1 0 1 1 0 0 0 1.06250V
0 1 0 1 1 0 0 1 1.05625V
0 1 0 1 1 0 1 0 1.05000V
0 1 0 1 1 0 1 1 1.04375V
0 1 0 1 1 1 0 0 1.03750V
0 1 0 1 1 1 0 1 1.03125V
0 1 0 1 1 1 1 0 1.02500V
0 1 0 1 1 1 1 1 1.01875V
0 1 1 0 0 0 0 0 1.01250V
0 1 1 0 0 0 0 1 1.00625V
0 1 1 0 0 0 1 0 1.00000V
0 1 1 0 0 0 1 1 0.99375V
0 1 1 0 0 1 0 0 0.98750V
0 1 1 0 0 1 0 1 0.98125V
0 1 1 0 0 1 1 0 0.97500V
0 1 1 0 0 1 1 1 0.96875V
0 1 1 0 1 0 0 0 0.96250V
0 1 1 0 1 0 0 1 0.95625V
0 1 1 0 1 0 1 0 0.95000V
0 1 1 0 1 0 1 1 0.94375V
0 1 1 0 1 1 0 0 0.93750V
0 1 1 0 1 1 0 1 0.93125V
0 1 1 0 1 1 1 0 0.92500V
0 1 1 0 1 1 1 1 0.91875V
0 1 1 1 0 0 0 0 0.91250V
0 1 1 1 0 0 0 1 0.90625V
0 1 1 1 0 0 1 0 0.90000V
0 1 1 1 0 0 1 1 0.89375V
0 1 1 1 0 1 0 0 0.88750V
0 1 1 1 0 1 0 1 0.88125V
0 1 1 1 0 1 1 0 0.87500V
0 1 1 1 0 1 1 1 0.86875V
Table 2. Output Voltage Program (VRD11)
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Table 2. Output Voltage Program (VRD11)
To be continued
Pin Name Nominal Out put Volt age
DACOUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
0 1 1 1 1 0 0 0 0.86250V
0 1 1 1 1 0 0 1 0.85625V
0 1 1 1 1 0 1 0 0.85000V
0 1 1 1 1 0 1 1 0.84375V
0 1 1 1 1 1 0 0 0.83750V
0 1 1 1 1 1 0 1 0.83125V
0 1 1 1 1 1 1 0 0.82500V
0 1 1 1 1 1 1 1 0.81875V
1 0 0 0 0 0 0 0 0.81250V
1 0 0 0 0 0 0 1 0.80625V
1 0 0 0 0 0 1 0 0.80000V
1 0 0 0 0 0 1 1 0.79375V
1 0 0 0 0 1 0 0 0.78750V
1 0 0 0 0 1 0 1 0.78125V
1 0 0 0 0 1 1 0 0.77500V
1 0 0 0 0 1 1 1 0.76875V
1 0 0 0 1 0 0 0 0.76250V
1 0 0 0 1 0 0 1 0.75625V
1 0 0 0 1 0 1 0 0.75000V
1 0 0 0 1 0 1 1 0.74375V
1 0 0 0 1 1 0 0 0.73750V
1 0 0 0 1 1 0 1 0.73125V
1 0 0 0 1 1 1 0 0.72500V
1 0 0 0 1 1 1 1 0.71875V
1 0 0 1 0 0 0 0 0.71250V
1 0 0 1 0 0 0 1 0.70625V
1 0 0 1 0 0 1 0 0.70000V
1 0 0 1 0 0 1 1 0.69375V
1 0 0 1 0 1 0 0 0.68750V
1 0 0 1 0 1 0 1 0.68125V
1 0 0 1 0 1 1 0 0.67500V
1 0 0 1 0 1 1 1 0.66875V
1 0 0 1 1 0 0 0 0.66250V
1 0 0 1 1 0 0 1 0.65625V
1 0 0 1 1 0 1 0 0.65000V
1 0 0 1 1 0 1 1 0.64375V
1 0 0 1 1 1 0 0 0.63750V
1 0 0 1 1 1 0 1 0.63125V
1 0 0 1 1 1 1 0 0.62500V
1 0 0 1 1 1 1 1 0.61875V
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To be continued
Table 2. Output Voltage Program (VRD11)
To be continued
Pin Name Nominal Output Volt age
DACOUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
1 0 1 0 0 0 0 0 0.61250V
1 0 1 0 0 0 0 1 0.60625V
1 0 1 0 0 0 1 0 0.60000V
1 0 1 0 0 0 1 1 0.59375V
1 0 1 0 0 1 0 0 0.58750V
1 0 1 0 0 1 0 1 0.58125V
1 0 1 0 0 1 1 0 0.57500V
1 0 1 0 0 1 1 1 0.56875V
1 0 1 0 1 0 0 0 0.56250V
1 0 1 0 1 0 0 1 0.55625V
1 0 1 0 1 0 1 0 0.55000V
1 0 1 0 1 0 1 1 0.54375V
1 0 1 0 1 1 0 0 0.53750V
1 0 1 0 1 1 0 1 0.53125V
1 0 1 0 1 1 1 0 0.52500V
1 0 1 0 1 1 1 1 0.51875V
1 0 1 1 0 0 0 0 0.51250V
1 0 1 1 0 0 0 1 0.50625V
1 0 1 1 0 0 1 0 0.50000V
1 0 1 1 0 0 1 1 X
1 0 1 1 0 1 0 0 X
1 0 1 1 0 1 0 1 X
1 0 1 1 0 1 1 0 X
1 0 1 1 0 1 1 1 X
1 0 1 1 1 0 0 0 X
1 0 1 1 1 0 0 1 X
1 0 1 1 1 0 1 0 X
1 0 1 1 1 0 1 1 X
1 0 1 1 1 1 0 0 X
1 0 1 1 1 1 0 1 X
1 0 1 1 1 1 1 0 X
1 0 1 1 1 1 1 1 X
1 1 0 0 0 0 0 0 X
1 1 0 0 0 0 0 1 X
1 1 0 0 0 0 1 0 X
1 1 0 0 0 0 1 1 X
1 1 0 0 0 1 0 0 X
1 1 0 0 0 1 0 1 X
1 1 0 0 0 1 1 0 X
1 1 0 0 0 1 1 1 X
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Table 2. Output Voltage Program (VRD11)
To be continued
Pin Name Nominal Out put Voltage
DACOUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
1 1 0 0 1 0 0 0 X
1 1 0 0 1 0 0 1 X
1 1 0 0 1 0 1 0 X
1 1 0 0 1 0 1 1 X
1 1 0 0 1 1 0 0 X
1 1 0 0 1 1 0 1 X
1 1 0 0 1 1 1 0 X
1 1 0 0 1 1 1 1 X
1 1 0 1 0 0 0 0 X
1 1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 0 X
1 1 0 1 0 0 1 1 X
1 1 0 1 0 1 0 0 X
1 1 0 1 0 1 0 1 X
1 1 0 1 0 1 1 0 X
1 1 0 1 0 1 1 1 X
1 1 0 1 1 0 0 0 X
1 1 0 1 1 0 0 1 X
1 1 0 1 1 0 1 0 X
1 1 0 1 1 0 1 1 X
1 1 0 1 1 1 0 0 X
1 1 0 1 1 1 0 1 X
1 1 0 1 1 1 1 0 X
1 1 0 1 1 1 1 1 X
1 1 1 0 0 0 0 0 X
1 1 1 0 0 0 0 1 X
1 1 1 0 0 0 1 0 X
1 1 1 0 0 0 1 1 X
1 1 1 0 0 1 0 0 X
1 1 1 0 0 1 0 1 X
1 1 1 0 0 1 1 0 X
1 1 1 0 0 1 1 1 X
1 1 1 0 1 0 0 0 X
1 1 1 0 1 0 0 1 X
1 1 1 0 1 0 1 0 X
1 1 1 0 1 0 1 1 X
1 1 1 0 1 1 0 0 X
1 1 1 0 1 1 0 1 X
1 1 1 0 1 1 1 0 X
1 1 1 0 1 1 1 1 X
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Table 2. Output Voltage Program (VRD11)
Pin Name Nominal Output Voltage
DACOUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
1 1 1 1 0 0 0 0 X
1 1 1 1 0 0 0 1 X
1 1 1 1 0 0 1 0 X
1 1 1 1 0 0 1 1 X
1 1 1 1 0 1 0 0 X
1 1 1 1 0 1 0 1 X
1 1 1 1 0 1 1 0 X
1 1 1 1 0 1 1 1 X
1 1 1 1 1 0 0 0 X
1 1 1 1 1 0 0 1 X
1 1 1 1 1 0 1 0 X
1 1 1 1 1 0 1 1 X
1 1 1 1 1 1 0 0 X
1 1 1 1 1 1 0 1 X
1 1 1 1 1 1 1 0 OFF
1 1 1 1 1 1 1 1 OFF
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) X : Don't Care
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Table 3. Output Voltage Program (K8)
VID4 VID3 VID2 VID1 VID0 Nominal Output Voltage DACOUT
0 0 0 0 0 1.550
0 0 0 0 1 1.525
0 0 0 1 0 1.500
0 0 0 1 1 1.475
0 0 1 0 0 1.450
0 0 1 0 1 1.425
0 0 1 1 0 1.400
0 0 1 1 1 1.375
0 1 0 0 0 1.350
0 1 0 0 1 1.325
0 1 0 1 0 1.200
0 1 0 1 1 1.275
0 1 1 0 0 1.250
0 1 1 0 1 1.225
0 1 1 1 0 1.200
0 1 1 1 1 1.175
1 0 0 0 0 1.150
1 0 0 0 1 1.125
1 0 0 1 0 1.100
1 0 0 1 1 1.075
1 0 1 0 0 1.050
1 0 1 0 1 1.025
1 0 1 1 0 1.000
1 0 1 1 1 0.975
1 1 0 0 0 0.950
1 1 0 0 1 0.925
1 1 0 1 0 0.900
1 1 0 1 1 0.875
1 1 1 0 0 0.850
1 1 1 0 1 0.825
1 1 1 1 0 0.800
1 1 1 1 1 Shutdown
Note: (1) 0 : Connected to GND
(2) 1 : Open
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Table 4. Output Voltage Program (K8_M2)
To be continued
Pin Name
VID5 VID4 VID3 VID2 VID1 VID0
Nominal Output Voltage DACOUT
0 0 0 0 0 0 1.5500
0 0 0 0 0 1 1.5250
0 0 0 0 1 0 1.5000
0 0 0 0 1 1 1.4750
0 0 0 1 0 0 1.4500
0 0 0 1 0 1 1.4250
0 0 0 1 1 0 1.4000
0 0 0 1 1 1 1.3750
0 0 1 0 0 0 1.3500
0 0 1 0 0 1 1.3250
0 0 1 0 1 0 1.3000
0 0 1 0 1 1 1.2750
0 0 1 1 0 0 1.2500
0 0 1 1 0 1 1.2250
0 0 1 1 1 0 1.2000
0 0 1 1 1 1 1.1750
0 1 0 0 0 0 1.1500
0 1 0 0 0 1 1.1250
0 1 0 0 1 0 1.1000
0 1 0 0 1 1 1.0750
0 1 0 1 0 0 1.0500
0 1 0 1 0 1 1.0250
0 1 0 1 1 0 1.0000
0 1 0 1 1 1 0.9750
0 1 1 0 0 0 0.9500
0 1 1 0 0 1 0.9250
0 1 1 0 1 0 0.9000
0 1 1 0 1 1 0.8750
0 1 1 1 0 0 0.8500
0 1 1 1 0 1 0.8250
0 1 1 1 1 0 0.8000
0 1 1 1 1 1 0.7750
1 0 0 0 0 0 0.7625
1 0 0 0 0 1 0.7500
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Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) The voltage above are load independent for desktop and server platforms. For mobile platforms the voltage above
correspond to zero load current.
Table 4. Output Voltage Program (K8_M2)
Pin Name
VID5 VID4 VID3 VID2 VID1 VID0
Nominal Output Voltage DACOUT
1 0 0 0 1 0 0.7375
1 0 0 0 1 1 0.7250
1 0 0 1 0 0 0.7125
1 0 0 1 0 1 0.7000
1 0 0 1 1 0 0.6875
1 0 0 1 1 1 0.6750
1 0 1 0 0 0 0.6625
1 0 1 0 0 1 0.6500
1 0 1 0 1 0 0.6375
1 0 1 0 1 1 0.6250
1 0 1 1 0 0 0.6125
1 0 1 1 0 1 0.6000
1 0 1 1 1 0 0.5875
1 0 1 1 1 1 0.5750
1 1 0 0 0 0 0.5625
1 1 0 0 0 1 0.5500
1 1 0 0 1 0 0.5375
1 1 0 0 1 1 0.5250
1 1 0 1 0 0 0.5125
1 1 0 1 0 1 0.5000
1 1 0 1 1 0 0.4875
1 1 0 1 1 1 0.4750
1 1 1 0 0 0 0.4625
1 1 1 0 0 1 0.4500
1 1 1 0 1 0 0.4375
1 1 1 0 1 1 0.4250
1 1 1 1 0 0 0.4125
1 1 1 1 0 1 0.4000
1 1 1 1 1 0 0.3875
1 1 1 1 1 1 0.3750
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Functional Pin Description
Pi n No. Pi n Name Pi n Functi on
1 VIDSEL VID DAC Selection Pin.
2 FBRTN Negative remote sense pin of output voltage.
3 SS/EN
Connect this pin to GND by a capacitor to adjust soft start time.
Pull this pin to GND to disable controller.
4 ADJ Connect this pin to GND by a resistor to set loadline.
5 COMP Output of error-amp and input of PWM comparator.
6 FB Inverting input of error-amp.
7 OFS Connect this pin to GND by a resistor to set no-load offset voltage.
8 RT Connect this pin to GND by a resistor to adjust frequency.
9 IMAX
Negative input of OCP comparator. (Positive input of OCP
comparator is ADJ ).
10 GND Ground Pin.
11,14,15,18 ISP4, ISP3, ISP2, ISP1 Positive current sense pin of channel 1, 2, 3 and 4.
12,13,16,17 ISN4, ISN3, ISN2, ISN1 Negative current sense pin of channel 1, 2, 3 and 4.
19 VCC5 5V LDO output for system power supply pin.
20,21 PWM4, PWM3 PWM output for channel 4 and channel 3.
22,30 BOOT2, BOOT1 Bootstrap supply for channel 2 and channel 1.
23,29 UGATE2, UGATE1 Upper gate driver for channel 2 and channel 1.
24,28 PHASE2, PHASE1 Switching node of channel 2 and channel 1.
25,27 LGATE2, LGATE1 Lower gate driver for channel 2 and channel 1.
26 VCC12 IC power supply. Connect to 12V.
31 PWRGD Power good indicator.
32 EN/VTT VTT voltage detector input.
33 to 40 VID7 to VID0 Voltage identification input for DAC.
41 (Exposed pad) GND
Exposed pad should be soldered to PCB board and connected to
GND.
VIDSEL VID [7] Tabl e
VTT X VR11
GND X VR10.x
VCC5 VTT K8
VCC5 GND K8_M2
VID Table Selection
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Function Block Diagram
VCC12
VCC5
BOOT1
UGATE1
PHASE1
LGATE1
BOOT2
UGATE2
PHASE2
LGATE2
PWM3
PWM4
ISP1
ISN1
ISP2
ISN2
ISP3
ISN3
ISP4
ISN4
ADJ
FBRTN
VID7 to VID0
I_SEN1
I_SEN2
I_SEN3
I_SEN4
IMAX
OC
POR
POR
VIDOFF
SS/EN
FB
150mV
OV
COMP
OC
OV
RT
850mV
EN/VTT
OFS
Power-On
Reset
5V
Regulator
MOSFET
Driver
MOSFET
Driver
CH3_EN
Detector
CH4_EN
Detector
CH1
Current
SENSE
CH2
Current
SENSE
CH3
Current
SENSE
CH4
Current
SENSE
AVG
VID
Table
Generator
Soft Start
and
Fault
Logic
Transient
Response
Enhancement
Offset
Modulator
Waveform
Generator
+
-
+
-
+
-
+
-
+
-
+
-
+
+
-
+
+
-
EA
+
-
+
-
+
-
+
-
+
-
VIDSEL
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El ectri cal Characteri sti cs
Paramet er Symbol Test Condit i ons Min Typ Max Uni t
VCC12 Supply Input
VCC12 Supply Voltage V
VCC12
10.8 12 13.2 V
VCC12 Supply Current I
CC
No switching -- 6 -- mA
VCC5 power
VCC5 Supply Voltage V
VCC5
I
LOAD
=10mA 4.75 5.0 5.25 V
VCC5 Output Sourcing I
VCC5
10 -- -- mA
Power -On Reset
VCC12 Rising Threshold V
VCC12TH
VCC12 Rising 9.2 9.6 10.0 V
VCC12 Hysteresis V
VCC12HY
VCC12 Falling -- 0.9 -- V
EN/VTT
EN/VTT Rising Threshold V
ENVTT
EN/VTT Rising 0.80 0.85 0.90 V
Enable Hysteresis V
ENVTTHY
EN/VTT Falling -- 100 -- mV
Reference Vol t age accuracy
0.8V to 1.6V 5 -- +5
DAC Accuracy
0.5V to 0.8V 8 -- +8
mV
To be continued
Recommended Operating Conditions (Note 4)
Supply Voltage, VCC12 -------------------------------------------------------------------------------------------------- 12V 10%
J unction Temperature Range -------------------------------------------------------------------------------------------- 40C to 125C
Ambient Temperature Range --------------------------------------------------------------------------------------------

0C to 70C
Absolute Maximum Ratings (Note 1)
Supply Input Voltage ------------------------------------------------------------------------------------------------------- 0.3V to 15V
BOOTx to PHASEx -------------------------------------------------------------------------------------------------------- 0.3V to 15V
BOOTx to GND
DC--------------------------------------------------------------------------------------------------------------------------- 0.3V to 30V
<200ns --------------------------------------------------------------------------------------------------------------------- 0.3V to 42V
PHASEx to GND
DC--------------------------------------------------------------------------------------------------------------------------- 2V to 15V
<200ns --------------------------------------------------------------------------------------------------------------------- 5V to 30V
Input/Output Voltage ------------------------------------------------------------------------------------------------------- 0.3V to 7V
Power Dissipation, P
D
@ T
A

=25C
WQFN40L 6x6 ------------------------------------------------------------------------------------------------------------- 2.778W
Package Thermal Resistance (Note 2)
WQFN-40L 6x6,
J A
-------------------------------------------------------------------------------------------------------- 36C/W
J unction Temperature ------------------------------------------------------------------------------------------------------ 150C
Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------- 260C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------------ 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------------- 200V
(VCC12 =12V, VGND

=0V, TA =25C, unless otherwise specified)
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Parameter Symbol Test Condi ti ons Mi n Typ Max Uni t
Error Ampli fi er
DC Gain A
DC
No Load -- 80 -- dB
Gain-Bandwidth GBW C
LOAD
=10pF -- 10 -- MHz
Slew Rate SR C
LOAD
=10pF 10 -- -- V/us
Output voltage range V
COMP
0.5 3.6 V
Max Current I
EA_SLEW
Slew 300 -- -- uA
Power Sequence
PWRGD Low Voltage V
PGOOD
I
PWRGD
=4mA -- -- 0.4 V
Soft-Start Delay T
D1
-- 2 -- ms
V
BOOT
Duration T
D3
-- 0.8 -- ms
PWRGD Delay T
D5

Measured the time form V
BOOT
change
to PWRGD =1
-- 1.6 -- ms
Current Sense Ampli fi er
Max Current I
GMMAX

V
CSP
= 1.3V
Sink Current from CSN
100 -- -- uA
Input Offset Voltage V
OSCS
1.5 0 1.5 mV
Running Frequency f
OSC
R
RT
=40k 270 300 330 kHz
RT Pin Voltage V
RT
R
RT
=40k 1.52 1.60 1.68 V
Ramp Amplitude V
RAMP
R
RT
=40k -- 1.60 -- V
Soft St ar t
Soft Start Current I
SS1
Slew 13 16 19 uA
VID change Current I
SS2
Slew 130 160 190 uA
Gate Driver
UGATE Drive Source R
UGATEsr

BOOT PHASE =8V
250mA Source Current
-- 1 --
UGATE Drive Sink R
UGATEsk

BOOT PHASE =8V
250mA Sink Current
-- 1 --
LGATE Drive Source R
LGATEsr
V
LGATE
= 8V -- 1 --
LGATE Drive Sink R
LGATEsk
250mA Sink Current -- 0.8 --
Protect ion
Over-Voltage Threshold V
OVP
Sweep FB Voltage, V
FB,EAP
125 150 175 mV
Over-Current Threshold V
OCP
Sweep IMAX Voltage, V
IMAX,ADJ
13 0 +13 mV
Dynamic Characteri sti c
UGATE Rise Time t
rUGATE
-- 15 -- ns
UGATE Fall Time t
fUGATE
-- 10 -- ns
LGATE Rise Time t
rLGATE
-- 15 -- ns
LGATE Fall Time t
fLGATE

Ciss =3000p
-- 10 -- ns
Input Threshol d
VID7 to VID0,
VIDSEL Rising Threshold
V
ID7 to 0
,
V
IDSEL

VID7 to VID0 Rising,
VIDSEL Rising
--
1/2V
TT
+
12.5mV
-- V
VID7 to VID0,
VIDSEL Hysteresis
V
ID7 to
0_Hy
,
V
IDSEL_Hy

VID7 to VID0 Falling,
VIDSEL Falling
-- 25 -- mV

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Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. J A is measured in the natural convection at TA =25C on a effective single layer thermal conductivity test board of
J EDEC thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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Typi cal Operati ng Characteri sti cs
Output Voltage vs. Temperature
1.314
1.315
1.316
1.317
1.318
1.319
1.320
1.321
1.322
1.323
1.324
-40 -20 0 20 40 60 80 100 120 140
Temperature
O
u
t
p
u
t

V
o
l
t
a
g
e

(
V
)
VIN =12V, IOUT =0A
Frequency vs. Temperature
345
350
355
360
365
370
375
380
-40 -20 0 20 40 60 80 100 120 140
Temperature
F
r
e
q
u
e
n
c
y

(
k
H
z
)
RRT =30.1k
(C)
Power Off from VTT/EN
Time (40us/Div)
SS
(2V/Div)
VOUT
(1V/Div)
PHASE
(10V/Div)
VIN =12V, VOUT =1.4V, IOUT =0A
VTT/EN
(1V/Div)
Power On from VIN
Time (4ms/Div)
PGOOD
(2V/Div)
VOUT
(1V/Div)
PHASE
(10V/Div)
VIN =12V, VOUT =1.4V, IOUT =0A
VIN
(10V/Div)
Power On from VTT/EN
Time (2ms/Div)
PGOOD
(1V/Div)
VOUT
(1V/Div)
PHASE
(10V/Div)
VIN =12V, VOUT =1.4V, IOUT =0A
VTT/EN
(1V/Div)
Frequency vs. R
RT
0
200
400
600
800
1000
1200
0 40 80 120 160 200 240 280
R
RT
(k ohm)
F
r
e
q
u
e
n
c
y

(
k
H
z
)
(k)
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VOUT
(500mV/Div)
Power Off from VIN
Time (4ms/Div)
SS
(2V/Div)
VOUT
(1V/Div)
PHASE
(10V/Div)
VIN =12V, VOUT =1.4V, IOUT =0A
VIN
(10V/Div)
Dynamic VID
Time (40us/Div)
VOUT
(500mV/Div)
VID
(1V/Div)
Rising
Output Short then Power On
Time (1ms/Div)
SS
(2V/Div)
VOUT
(1V/Div)
PHASE
(10V/Div)
VIN =12V, VOUT =1.4V
PGOOD
(1V/Div)
Dynamic VID
Time (40us/Div)
VID
(1V/Div)
Falling
ACLL Overshoot
Time (20us/Div)
VOUT
(20mV/Div)
IOUT =67.5 to 35A
35
IOUT
(A)
67.5
ACLL Drop
Time (20us/Div)
VOUT
(20mV/Div)
IOUT =35 to 67.5A
35
IOUT
(A)
67.5
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Power On then Output Short
Time (1ms/Div)
SS
(2V/Div)
VOUT
(1V/Div)
PHASE
(10V/Div)
VIN =12V, VOUT =1.4V
PGOOD
(1V/Div)
OVP
Time (40us/Div)
SS
(2V/Div)
FB
(500mV/Div)
PHASE
(10V/Div)
PGOOD
(1V/Div)
FB
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Application Information
RT8841 is a 4/3/2/1-phase synchronous buck DC/DC
converter with 2 embedded MOSFET drivers. The internal
VID DAC is designed to interface with the Intel 8-bit VR11
compatible CPUs.
Power Ready Detection
During start-up, RT8841 will detect V
CC
12, V
CC
5 and V
TT
.
When V
CC
12 >9.6V, V
CC
5 >4.6V and V
TT
>0.85V POR
will go high. POR (Power On Reset) is the internal signal
to indicate all voltage powers are ready to let RT8841 and
the companioned MOSFET drivers to work properly. When
POR =L, RT8841 will try to turn off both high side and low
side MOSFETs.
Phase Detection
The number of operational phases is determined by the
internal circuitry that monitors the ISNx voltages during
start up. Normally, the RT8841 operates as a 4-phase
PWM controller. Pull ISN4 and ISP4 to V
CC
5 programs
3-phase operation, pull ISN3 and ISP3 to V
CC
5 programs
2-phase operation, and pull ISN2 and ISP2 to V
CC
5
programs 1-phase operation. RT8841 detects the voltage
of ISN4, ISN3 and ISN2 at POR rising edge. At the rising
edge, RT8841 detects whether the voltage of ISN4, ISN3
and ISN2 are higher than V
CC
5 1V respectively to
decide how many phases should be active. Phase
detection is only active during start up. When POR =H,
the number of operational phases is determined and
latched. The unused PWM pin can be connected to 5V,
GND or left open.
Figure 1. Circuit for Power Ready Detection
Figure 2. R
RT
vs Phase Switching Frequency
POR
V
CC
12
V
TT
+
-
CMP
+
-
CMP
+
-
CMP
POR : Power On Reset
9.6V
4.6V
0.85V
V
CC
5
Phase Switching Frequency
The phase switching frequency of the RT8841 is set by
an external resistor connected from the RT pin to GND.
The frequency follows the graph in Figure 2.
Frequency vs. R
RT
0
200
400
600
800
1000
1200
0 40 80 120 160 200 240 280
R
RT
(k ohm)
F
r
e
q
u
e
n
c
y

(
k
H
z
)
(k)
The V
OUT
start-up time is set by a capacitor from the SS
pin to GND. In power_on_reset state (POR =L), the SS
pin is held at GND. After power_on_reset stae (POR =H)
and an extra delay 1600us, V
SS
and V
SSQ
begin to rise till
V
SSQ
=V
BOOT
. When V
SSQ
=V
BOOT
, RT8841 stays in this
state for 800us waiting for valid VID code sent by CPU.
After receiving valid VID code, V
OUT
continues ramping up
or down to the voltage specified by VID code. Before
PWRGD =H, output current of OPSS (I
SS
) is limited to
8uA (I
SS
1). When PWRGD =H, I
SS
is limited to 80uA (I
SS
2).
The soft start waveform is shown in Figure 5.
V
OUT
will trace V
EAP
which is equal to V
SSQ
V
ADJ
.
V
ADJ
is a small voltage signal which is proportional to
I
OUT
. This voltage is used to generate loadline and will be
described later. T1 is the delay time from power_on_reset
state to the beginning of V
OUT
rising.
T1 =1600s +0.6V x C
SS
/I
SS
1 (1)
T2 is the soft start time from V
OUT
=0 to V
OUT
=V
BOOT
.
Soft Start
Figure 4. Circuit for Soft Start and Dynamic VID
+
-
OPSS
V
DAC
SS
+
-
ADJ
C
SS R
ADJ
NTC
EAP
(ErrorAmp positive input)
Output current of OPSS (I
SS
) is limited and variant
SSQ
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T2 =V
BOOT
x C
SS
/I
SS
1 (2)
T3 is the dwelling time for V
OUT
=V
BOOT
. T3 =800s.
T4 is the soft start time from V
OUT
=V
BOOT

to V
OUT
=
V
DAC
.
T4 ~=|V
DAC
V
BOOT
| x C
SS
/I
SS
1 (3)
T5 is the power good delay time, T5 ~=1600s.
Dynamic VID
The RT8841 can accept VID input changing while the
controller is running. This allows the output voltage (V
OUT
)
to change while the DC/DC converter is running and
supplying current to the load. This is commonly referred
to as VID on-the-fly (OTF). A VID OTF can occur under
either light or heavy load conditions. The CPU changes
the VID inputs in multiple steps from the start code to the
finish code. This change can be positive or negative.
Theoretically, V
OUT
should follow V
DAC
which is a staircase
waveform. In RT8841, as mentioned in soft start session,
V
DAC
slew rate is limited by I
SS
2/C
SS
when PWRGD =H.
This slew rate limiter works as a low pass filter of V
DAC
and makes the bandwidth of V
DAC
waveform finite. By
smoothening V
DAC
staircase waveform, V
OUT
will no longer
overshoot or undershoot. On the other hand, C
SS
will
increase the settling time of V
OUT
during VID OTF. In most
cases, 1nF to 30nF ceramic capacitor is suitable for C
SS
.
Output Voltage Differential Sensing
The RT8841 uses differential sensing by a high gain low
offset ErrorAmp. The CPU voltage is sensed between the
FB and FBRTN pins. A resistor (R
FB
) connects FB pin and
the positive remote sense pin of the CPU (V
CCP
). FBRTN
No-Load Offset
In Figure 6, I
OFSN
or I
OFSP
are used to generate no-load
offset. Either I
OFSN
or I
OFSP
is active during normal operation.
It should be noted that users can only enable one polarity
of no-load offset. Do not connect OFS pin to GND and to
V
CC5
at the same time. Connect a resistor from OFS pin
to GND to activate I
OFSN
. I
OFSN
flows through R
ADJ
from
ADJ pin to GND. In this case, negative no-load offset voltage
(V
OFSN
) is generated.
V
OFSN
=I
OFSN
x R
ADJ
=0.8 x R
ADJ
/R
OFS
(4)
Connect a resistor from OFS pin to V
CC
5 to activate I
OFSP
.
I
OFSP
flows through R
FB
from the V
CCP
to FB pin. In this
case, positive no-load offset voltage (V
OFSP
) is generated.
When positive no-load offset is selected, the RT8841 will
generate another internal 8uA current source to eliminate
dead zone problem of droop function. This 8uA current
will be injected into ADJ resistors, producing a small initial
negative no-load offset. Therefore, when OFS pin is
connected to VCC5 through a resistor, the positive no-
load offset can be calculated as :
Figure 5. Soft Start Waveforms
VCC12 9.6V
V
DAC
SS
SSQ
PWRGD T1 T2 T3
V
TT 0.85V
V
BOOT
T4 T5
SS
SSQ
VCC5 4.6V
pin connects to the negative remote sense pin of CPU
(V
CCN
) directly. The ErrorAmp compares EAP (=V
DAC

V
ADJ
) with the V
FB
to regulate the output voltage.
OFSP OFSP FB ADJ
FB
ADJ
OFS
V I R 8uA R
R
6.4 8uA R
R
=
=
Figure 6. Circuit for V
OUT
Differential Sensing and No
Load Offset
+
-
EA
+
-
V
DAC
+
-
I
OFSN
EAP
COMP
FB
FBRTN
ADJ
C1
C2
R1
C
FB
R
FB
V
CCP
(Positive remote
sense pin of CPU)
V
CCN
(Negative remote
sense pin of CPU)
R
ADJ
I
OFSP
(5)
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Load Transient Quick Response
Figure 7. Load Transient Quick Response
In steady state, the voltage of V
FB
is controlled to be very
close to V
EAP
. While a load step transient from light load
to heavy load could cause V
FB
lower than V
EAP
by several
tens of mV. In prior design, owing to limited control
bandwidth, controller is hard to prevent V
OUT
undershoot
during quick load transient from light load to heavy load.
RT8841 detects load transient by comparing V
FB
and V
EAP
.
If V
FB
suddenly drops below V
EAP
V
QR
, V
QR
is a
predetermined voltage. The quick response indicator QR
rises up. When QR =H, RT8841 turns on all high side
MOSFETs and turn off all low side MOSFETs. The
sensitivity of quick response can be adjusted by the values
of C
FB
and R
FB
. Smaller R
FB
and/or larger C
FB
will make
QR easier to be triggered. Figure 7 is the circuit and typical
waveforms.
+
-
235nA
235nA
V
OFS_CSA
+
-
ISN
ISP
R
CSP
R
CSN
R
S
DCR
CS
L
I
X
CSA: Current Sense Amplifier
Figure 8. Circuit for Channel Current Sensing
+
-
+
-
FB COMP
QR
EAP - V
QR
EAP =V
QR
- V
ADJ
C1
C2
R1 R
FB
C
FB
V
OUT
I
OUT
V
OUT
FB
=V
EAP
=V
EAP
- V
QR
FB
QR
Loadl i ne
Output current of CSA is summed and averaged in
RT8841. Then 0.5(I
X
[n]) is sent to ADJ pin. Because
I
X
[n] is a PTC (Positive Temperature Coefficient) current,
an NTC (Negative Temperature Coefficient) resistor is
needed to connect ADJ pin to GND. If the NTC resistor is
properly selected to compensate the temperature
coefficient of I
X
[n], the voltage on ADJ pin will be
proportional to I
OUT
without temperature effect. In RT8841,
the positive input of ErrorAmp is V
DAC

V
ADJ
. V
OUT
will
follow V
DAC

V
ADJ
, too. Thus, the output voltage
decreasing linearly with I
OUT
is obtained. The loadline is
defined as
LL(loadline) =V
OUT
/I
OUT

=V
ADJ
/I
OUT
=0.5 x DCR x R
ADJ
/R
CSN
Briefly, the resistance of R
ADJ
sets the resistance of
loadline. The temperature coefficient of R
ADJ
compensates
the temperature effect of loadline.
Output Current Sensing
The RT8841 provides low input offset current-sense
amplifier (CSA) to monitor the output current of every
channel. Output current of CSA (I
X
[n]) is used for channel
current balance and active voltage position. In this inductor
current sensing topology, R
S
and C
S
must be set according
to the equation below :
L/DCR =R
S
x C
S
Then the output current of CSA will follow the equation
below :
I
X
=[I
L
x DCR V
OFS-CSA
+235n x (R
CSP
R
CSN
)]/R
CSN
235nA is typical value of CSA input offset current.
V
OFS-CSA
is the input offset voltage of CSA. V
OFS-CSA
of
RT8841 is smaller than +/- 1mV. Usually, V
OFS-CSA
+
235n x (R
CSP
R
CSN
) is negligible except at very light
load and the equation can be simplified as the equation
below :
I
X
=I
L
x DCR/R
CSN
RT8841 provides wide range no-load positive offset for over-
clocking applications. The I
OFSP
capability can supply from
30uA to 640uA, which means in Equation (5), R
OFS
can
range from 240k to 10k. Other resistances of R
OFS
exceeding this range can also provide no-load positive
offset but cannot be guaranteed by Equation (5).
RT8841
28
DS8841-01 April 2011 www.richtek.com
If the initial current distribution is constant ratio type,
according to Equation(8), reduce R
CSN
[1] can reduce I
L
[1]
and improve current balance. If the initial current distribution
is constant difference type, according to Equation(7),
increase R
CSP
[1] can reduce I
L
[1] and improve current
balance.
+
-
CMP
ADJ
IMAX
V
CC
5
R1
R2
OCP
Figure 11. Over Current Protection
In Figure 11, V
IMAX
is equal to 5V x R2/(R1 +R2). In
RT8841, V
ADJ
is proportional to I
OUT
and is thermally
compensated. Once V
ADJ
is larger than V
IMAX
, OCP is
triggered and latched. RT8841 will turn off both high side
MOSFET and low side MOSFET of all channels. A 20uS
delay is used in OCP detection circuit to prevent false
trigger.
Over Voltage Protectiom (OVP)
The over voltage protection monitors the output voltage
via the FB pin. Once V
FB
exceeds V
EAP
+150mV, OVP
is triggered and latched. RT8841 will try to turn on low
side MOSFET and turn off high side MOSFET to protect
CPU. A 20s delay is used in OVP detection circuit to
prevent false trigger.
+
-
+
-
+
-
+
-
COMP
I
ERR
[1] x R
CB
I
ERR
[n] x R
CB
Interleaved
RAMP[1]
RAMP[n]
CMP
CMP
BUF
BUF
PWM[1]
PWM[n]
Figure 9. Circuit for Channel Current Balance
In Figure 8, I
X
[n] is the current signal which is proportional
to current flowing through channel n. In Figure 9, the
current error signals I
ERR
[n] (=I
X
[n] AVG(I
X
[n])) are used
to raise or lower the internal sawtooth waveforms
(RAMP[1] to RAMP[n]) which are compared with ErrorAmp
output (COMP) to generate PWM signal. The raised
sawtooth waveform will decrease the PWM duty of the
corresponding channel while the lowered will increase.
Eventually, current flowing through each channel will be
balanced.
Channel Current Adjust
If channel current is not balanced due to asymmetric PCB
layout of power stage, external resistors can be adjusted
to correct current imbalance. Figure 10 shows two types
of current imbalance, constant ratio type and constant
difference type.
Constant ratio
I
OUT
, total
I1
I2
Constant difference
I
OUT
, total
I1
I2
Figure 10. Channel Current vs. Total Current
Current Balance
Over Current Protection (OCP)
Loop Compensation
The RT8841 is a synchronous Buck converter with two
control loops : voltage loop and current balance loop. Since
the function of the current balance loop is to maintain the
current balance between each active channel, its influence
to converter stability will be negligible compared with the
voltage feedback loop. Therefore, to compensate the
voltage loop will be the main task to maintain converter
stability.
The converter duty-to-output transfer function G
d
is :
2
2
OUT
d
V
D
G
S S
1
L
1 R
C
LC
=
+ +



RT8841
29
DS8841-01 April 2011 www.richtek.com
and the modulator gain of the converter is :
m
P
1
F
V
=
Where V
OUT
is the output voltage of the converter, R is
the loading resistance, L and C are the output inductance
and capacitance, and V
P
is the peak-to-peak voltage of
ramp applied at modulator input. The overall loop gain after
compensation can be described as :
Loop Gain =T =G
d
x F
m
x A
Where A denotes as compensation gain. To compensate
a typical voltage mode buck converter, there are two
ordinary compensation schemes, well known as type-II
compensator and type-III compensator. The choice of using
type-II or type-III compensator will be up to platform
designers, and the main concern will be the position of
the capacitor ESR zero and mid-frequency to high-
frequency gain boost. Typically, the ESR zero of output
capacitor will tend to stabilize the effect of output LC double
poles, hence the positon of the output capacitor ESR zero
in frequency domain may influence the design of voltage
loop compensation. If F
ZERO,ESR
is <1/2F
CO

where F
CO
denotes cross-over frequency, type-II compensation will
be sufficient for voltage stability. If F
ZERO,ESR

is >1/2F
CO
(or higher gain and phase margin is required at mid-
frequency to high-frequency), then type-III compensation
may be a better solution for voltage loop compensation.
A typical type-II compensation network is shown in
Figure 13.
R1 can be determined independently from DC
considerations. Normally choose R1 that the current
passing by will be around 1mA. Therefore,
REF
V
R1
1mA
=
Then determine R2 by the boosted gain of loop gain at
crossover :
2
ZERO, ESR
CO P
IN(MAX) LC ZERO, ESR
F F V
R2 R1
V F F

=


Where V
IN(MAX)
is the max input voltage of power stage,
V
P
is the peak-to-peak voltage of ramp applied at modulator
input, F
ZERO,ESR

is the frequency of output capacitor ESR
zero, and F
LC

is the frequency of output LC :
ZERO, ESR
ESR
LC
1
F
2 R C
1
F
2 LC

=

=

After determining the phase margin at crossover

=

=

F
Z

can be determined by the following Equation :
-1 -1
-1
CO Z
Z CO
CO
ZERO, ESR
F F
tan tan 90
F F
F
P.M. tan
F





+

By properly choosing F
Z

to fit equation (22), C1 can then
be determined by :
Z
1
C1
2 R2 F
=

and C2 can be determined by :
2
CO
Z
1
C2
F 1
2 R2
F C1

=

A typical type-III compensation contains two zeros and
two poles where the extra one zero and one pole compared
with type-II compensation are added for stabilizing the
system when ESR zero is relatively far from LC double
poles in frequency domain. Figure15. and Figure.16 shows
the typical circuit and bode plot of the type-III compensation.
RT8841
30
DS8841-01 April 2011 www.richtek.com
After determining desired phase margin, according to the
following Equation :
-1 -1
2
CO Z
Z CO
CO
P
Z
F F P.M.
tan tan 45
F F 2
and
F
F =
F

+



F
Z

and F
P

can be determined by choosing proper F
CO
to
F
Z

ratio to meet Equation (25). Again, R1 can be determined
by the Equation (16).
R2 can be determined by the following Equation :
2
CO P Z
IN(MAX) LC CO
F V F
R2 R1
V F F

=


Other component values of the Type-III compensation can
then be calculated as :
Z
P
Z
P
1
C1
2 R2 F
1
C2
1
2 R2 F
C1
1
C3
2 R1 F
1
R3
2 C3 F

=

=

=

=

Layout Considerations
For best performance of the RT8841, the following
guidelines must be strictly followed :
Input bulk capacitors and MLCCS have to be put near
high side MOSFETs. The connection plane of input
capacitors and high side MOSFETs then can be kept as
square as possible.
The shape of phase planes (the connection plane
between high side MOSFETs, low side MOSFETs and
output inductors) have to be as square as possible. Long
traces, thin bars or separated islands must be avoided
in phase planes.
Keep snubber circuits or damping elements near its
objects. Phase RC snubbers have to be close to low
side MOSFETs, UGATE damping resistors have to be
close to high side MOSFETs, and boot to phase damping
resistors have to be close to high side MOSFETs and
phase planes. Also keep the traces of these snubbers
circuits as short as possible.
The area of V
IN
plane (power stage 12V V
IN
) and V
OUT
plane (output bulk capacitors and inductors connection
plane) have to be as wide as possible. Long traces or
thin bars must be avoided in these planes. The plane
trace width must be wide enough to carry large input/
output current (40mil/A).
The following traces have to be wide and short : UGATE,
LGATE, BOOT, PHASE, and VCC12. Make sure the
width of these traces are wide enough to carry large
driving current(at least 40mil).
The voltage feedback loop contains two traces, VCC
and VSS, which are Kelvin sensed from CPU socket or
output capacitors. These two traces are suggested above
Figure 14. Bode Plot of Type-II Compensation
G
a
i
n

(
d
B
)
Frequency (Hz)
F
Z
F
P
Figure 15. Type-III Compensation
+
-
R2
C1
C2
R1
+
-
V
REF
EA
R3
C3
Figure 16. Bode Plot of the Type-III Compensation
G
a
i
n

(
d
B
)
Frequency (Hz)
F
Z
=F
Z1
=F
Z2
F
P
=F
P1
=F
P2
RT8841
31
DS8841-01 April 2011 www.richtek.com
10mil width and put away from high (di/dt) switching
elements such as high side MOSFETs, low side
MOSFETs, phase plane etc. The circuit elements of
voltage feedback loop, such as feedback loop short
resistors and voltage loop compensation RCs, have to
be kept near the RT8841 and also away from switching
elements.
The current sense mechanism of the RT8841 is fully
differential Kelvin sense. Therefore, the current sense
loops of the RT8841 contain two traces : the positive
traces(ISP1 to ISP4) come from the positive node of
output inductors(the node connecting phase plane) and
the negative traces (ISN1 to ISN4) come from the
negative node of output inductors(the node connecting
output plane).
DO NOT connect the current sense traces from phase
plane or output plane. Only connect these traces from
both sides of output inductors can achieve the goal of
precise Kelvin sense. The current sense feedback loops
have to be routed away from switching elements, and
the current sense RC elements have to be put near
their respective ISN or ISP pins of the RT8841 and also
away from noise switching elements. At least 10 mil
width is suggested for current sense feedback loops.
RT8841
32
DS8841-01 April 2011 www.richtek.com
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
Outline Dimension
Di mensi ons In Mi l li met ers Di mensi ons In Inches
Symbol
Mi n Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 5.950 6.050 0.234 0.238
D2 4.000 4.750 0.157 0.187
E 5.950 6.050 0.234 0.238
E2 4.000 4.750 0.157 0.187
e 0.500 0.020
L 0.350 0.450
0.014 0.018

W-Type 40L QFN 6x6 Package
D
E
D2
E2
L
b
A
A1
A3
e
1
SEE DETAIL A
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
DETAIL A
Pin #1 ID and Tie Bar Mark Options
1 1
2 2