RT8855

4/3/2/1-Phase PWM Controller for AMD AM2/AM2+ CPUs

General Description Features
The RT8855 is a 4/3/2/1-phase synchronous buck z 12V Power Supply Voltage
controller with two integrated MOSFET drivers for CPU z 4/3/2/1-Phase Power Conversion for VCORE Power
power application and a single-phase buck with integrated z 3 Embedded MOSFET Drivers (2 for CPU and 1 for
MOSFET driver for North-Bridge (NB) chipset.The RT8855 NB)
uses differential inductor DCR current sense to achieve z Internal Regulated 5V Output
phase current balance and active voltage positioning. Other z Support AMD AM2 6-bit Parallel and AM2+ 7-bit
features include adjustable operating frequency, power Serial VID Tables
good indication, external error-amp compensation, over z Continuous Differential Inductor DCR Current Sense
voltage protection, over current protection and enable/ z Adjustable Frequency (Typically at 300kHz)
shutdown for various applications. The RT8855 comes to z Selectable 1 or 2 Phase in Power-Saving (PS) Mode
a small footprint with WQFN-48L 7x7 package. z Phase-Interleaving for VCORE and NB Controller
z Power Good Indication
Applications z Adjustable Over Current Protection
z Over Voltage Protection
z Desktop CPU Core Power
z Small 48-Lead WQFN Package
z Low Voltage, High Current DC/ DC Converter
z RoHS Compliant and Halogen Free

Ordering Information
RT8855
Pin Configurations
Package Type (TOP VIEW)
QW : WQFN-48L 7x7 (W-Type) VID0/VFIXEN

UGATE_NB
PHASE_NB
LGATE_NB
VCC12_NB
VID3/SVC
VID2/SVD
VID1/PVI

Lead Plating System

PGOOD
VID5
VID4

G : Green (Halogen Free and Pb Free)

EN

Note :
48 47 46 45 44 43 42 41 40 39 38 37
Richtek products are : PWROK 1 36 BOOT_NB
` RoHS compliant and compatible with the current require- RT 2 35 BOOT1
FBRTN 3 34 UGATE1
ments of IPC/JEDEC J-STD-020. FBRTN_NB 4 33 PHASE1
` Suitable for use in SnPb or Pb-free soldering processes. FB_NB 5 32 LGATE1
COMP_NB 6 31 VCC12
ISP_NB 7
GND 30 LGATE2
ISN_NB 8 29 PHASE2
ADJ 9 28 UGATE2
OFS 10
49
27 BOOT2
COMP 11 26 PWM3
FB 12 25 PWM4
13 14 15 16 17 18 19 20 21 22 23 24
ISN1
ISP1
ISN2
ISP2
ISN3
ISP3
ISN4
ISP4

VCC5
IMAX_NB
IMAX

PS

WQFN-48L 7x7

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2
12V

RT8855
NTC
9 ADJ BOOT1 35
UGATE1 34

www.richtek.com
31 VCC12 L1
RT8855

12V
33
PHASE1

12V
40 VCC12_NB LGATE1 32

24 ISP1 16
VCC5 15
ISN1
12V 12V
23
12V PS

BOOT VCC BOOT2 27

Typical Application Circuit

UGATE GND UGATE2 28

L2 L2
PHASE 26 PHASE2 29
PWM PWM3
LGATE 30
LGATE2
RT9619
20 ISP3 18
ISP2
19 17
ISN3 ISN2
12V FB 12
12V 11
COMP
LOAD
BOOT VCC 3
FBRTN
UGATE GND
L2 12V
PHASE 25
PWM PWM4
LGATE
RT9619 BOOT_NB 36
22
ISP4 UGATE_NB 37
21 ISN4 L2
PHASE_NB 38
10 OFS
ROFS 46 to 41 LGATE_NB 39
VID[5:0]
48
EN ISP_NB 7
1 8
PWROK ISN_NB
47 PGOOD
FB_NB 5
2 RT
14 IMAX COMP_NB 6
4
13 IMAX_NB FBRTN_NB
LOAD

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 RT8855
Table 1. 7-bit VID Code Table for AM2+ CPU (Serial)
SVID[6:0] Voltage SVID[6:0] Voltage SVID[6:0] Voltage SVID[6:0] Voltage
0000000 1.5500 0100000 1.1500 1000000 0.7500 1100000 0.3500

0000001 1.5375 0100001 1.1375 1000001 0.7375 1100001 0.3375

0000010 1.5250 0100010 1.1250 1000010 0.7250 1100010 0.3250

0000011 1.5125 0100011 1.1125 1000011 0.7125 1100011 0.3125

0000100 1.5000 0100100 1.1000 1000100 0.7000 1100100 0.3000

0000101 1.4875 0100101 1.0875 1000101 0.6875 1100101 0.2875

0000110 1.4750 0100110 1.0750 1000110 0.6750 1100110 0.2750

0000111 1.4625 0100111 1.0625 1000111 0.6625 1100111 0.2625

0001000 1.4500 0101000 1.0500 1001000 0.6500 1101000 0.2500

0001001 1.4375 0101001 1.0375 1001001 0.6375 1101001 0.2375

0001010 1.4250 0101010 1.0250 1001010 0.6250 1101010 0.2250

0001011 1.4125 0101011 1.0125 1001011 0.6125 1101011 0.2125

0001100 1.4000 0101100 1.0000 1001100 0.6000 1101100 0.2000

0001101 1.3875 0101101 0.9875 1001101 0.5875 1101101 0.1875

0001110 1.3750 0101110 0.9750 1001110 0.5750 1101110 0.1750

0001111 1.3625 0101111 0.9625 1001111 0.5625 1101111 0.1625

0010000 1.3500 0110000 0.9500 1010000 0.5500 1110000 0.1500

0010001 1.3375 0110001 0.9375 1010001 0.5375 1110001 0.1375

0010010 1.3250 0110010 0.9250 1010010 0.5250 1110010 0.1250

0010011 1.3125 0110011 0.9125 1010011 0.5125 1110011 0.1125

0010100 1.3000 0110100 0.9000 1010100 0.5000 1110100 0.1000

0010101 1.2875 0110101 0.8875 1010101 0.4875 1110101 0.0875

0010110 1.2750 0110110 0.8750 1010110 0.4750 1110110 0.0750

0010111 1.2625 0110111 0.8625 1010111 0.4625 1110111 0.0675

0011000 1.2500 0111000 0.8500 1011000 0.4500 1111000 0.0500

0011001 1.2375 0111001 0.8375 1011001 0.4375 1111001 0.0375

0011010 1.2250 0111010 0.8250 1011010 0.4250 1111010 0.0250

0011011 1.2125 0111011 0.8125 1011011 0.4125 1111011 0.0125

0011100 1.2000 0111100 0.8000 1011100 0.4000 1111100 OFF

0011101 1.1875 0111101 0.7875 1011101 0.3875 1111101 OFF

0011110 1.1750 0111110 0.7750 1011110 0.3750 1111110 OFF

0011111 1.1625 0111111 0.7625 1011111 0.3625 1111111 OFF

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RT8855
Table 2. 6-bit VID Code Table for AM2 CPU (Parallel)
VID[5:0] Voltage VID[5:0] Voltage VID[5:0] Voltage VID[5:0] Voltage
000000 1.5500 010000 1.1500 100000 0.7625 110000 0.5625
000001 1.5250 010001 1.1250 100001 0.7500 110001 0.5500
000010 1.5000 010010 1.1000 100010 0.7375 110010 0.5375
000011 1.4750 010011 1.0750 100011 0.7250 110011 0.5250
000100 1.4500 010100 1.0500 100100 0.7125 110100 0.5125
000101 1.4250 010101 1.0250 100101 0.7000 110101 0.5000
000110 1.4000 010110 1.0000 100110 0.6875 110110 0.4875
000111 1.3750 010111 0.9750 100111 0.6750 110111 0.4750
001000 1.3500 011000 0.9500 101000 0.6625 111000 0.4625
001001 1.3250 011001 0.9250 101001 0.6500 111001 0.4500
001010 1.3000 011010 0.9000 101010 0.6375 111010 0.4375
001011 1.2750 011011 0.8750 101011 0.6250 111011 0.4250
001100 1.2500 011100 0.8500 101100 0.6125 111100 0.4125
001101 1.2250 011101 0.8250 101101 0.6000 111101 0.4000
001110 1.2000 011110 0.8000 101110 0.5875 111110 0.3875
001111 1.1750 011111 0.7750 101111 0.5750 111111 0.3750

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 RT8855
Functional Pin Description
Pin No. Pin Name Pin Function
1 PWROK PWROK Input Signal.
2 RT Connect this pin to GND by a resistor to adjust frequency.
3 FBRTN Remote sense ground for CORE.
4 FBRTN_NB Remote sense ground for NB.
5 FB_NB Inverting input of error-amp for NB.
6 COMP_NB Output of error-amp and input of PWM comparator for NB.
7 ISP_NB Positive current sense pin of NB
8 ISN_NB Negative current sense pin of NB
Connect this pin to GND by a resistor to set load line of
9 ADJ
VCORE.
Connect this pin to GND/5VCC by a resistor to set no-load
10 OFS
offset voltage of V CORE.
11 COMP Output of error-amp and input of PWM comparator of V CORE .
12 FB Inverting input of error-amp of V CORE.
13 IMAX_NB Connect this pin to GND by a resistor to set OCP of NB.
14 IMAX Connect this pin to GND by a resistor to set OCP of VCORE.
15, 17, 19, 21 ISN1, ISN2, ISN3, ISN4 Negative current sense pin of channel 1, 2, 3 and 4.
16, 18, 20, 22 ISP1, ISP2, ISP3, ISP4 Positive current sense pin of channel 1, 2, 3 and 4.
23 PS Power Saving Mode Selection Pin.
Output of internal 5V regulator for control circuits power supply.
24 VCC5
Connect this pin to GND by a ceramic capacitor larger than 1uF.
25,26 PWM4, PWM3 PWM output for channel 4 and channel 3.
27, 35, 36 BOOT2, BOOT1, BOOT_NB Bootstrap supply for channel 2 and channel 1 and NB.
28, 34, 37 UGATE2, UGATE1, UGATE_NB Upper gate driver for channel 2 and channel 1 and NB.
29, 33, 38 PHASE2, PHASE1, PHASE_NB Switching node of channel 2 and channel 1 and NB.
30, 32, 39 LGATE2, LGATE1, LGATE_NB Lower gate driver for channel 2 and channel 1 and NB.
31, 40 VCC12, VCC12_NB IC power supply. Connect this pin to 12V.
PVI Mode : Used as voltage identification input for DAC.
41 VID0/VFIXEN
SVI Mode : Functions as VFIXEN selection input.
This pin selects PVI/SVI mode based on the state of this pin
42 VID1/PVI prior to EN signal.
PVI Mode : Used as voltage identification input for DAC.
PVI Mode : Used as voltage identification input for DAC.
43 VID2/SVD
SVI Mode : Serial data input.
PVI Mode : Used as voltage identification input for DAC.
44 VID3/SVC
SVI Mode : Serial clock input.
45, 46 VID4, VID5 PVI Mode : Used as voltage identification input for DAC.
47 PGOOD Power Good Indicator (open drain).
48 EN Enable Input Signal.
Reference Ground for the IC. The exposed pad must be
Exposed pad
GND soldered to a large PCB and connected to GND for maximum
(49)
power dissipation.

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RT8855
Function Block Diagram

Modulator RAMP_NB
RT VCC12
Waveform
Generator Power-On 5V
POR
Reset Regulator
COMP
VCC5
FB -
EA
+
BOOT1
OFS Offset MOSFET UGATE1
+
Driver PHASE1
-
LGATE1
+
OV
-
+
1.8V BOOT2
+
MOSFET UGATE2
- Driver
PHASE2
Transient
Response LGATE2
Enhancement
+
PWM3
-
CH3_EN
OV Detector
OC
VIDOFF
Soft Start +
POR and PWM4
PGOOD -
Fault CH4_EN
PWROK Logic Detector
EN + PS
-
CH1
+ I_SEN1 ISP1
Current
+

1.25V - ISN1
SENSE

VID5 to VID0 I_SEN2 CH2

VID ISP2
+

Current
+

FBRTN Table - - SENSE ISN2

Generator
FBRTN_NB AVG
ADJ CH3
- I_SEN3 ISP3
Current
+

IMAX OC SENSE ISN3

OC
Detection

CH4
- I_SEN4
Current
ISP4
+

OC_NB SENSE ISN4

IMAX_NB OC_NB
Detection

I_SENNB NB ISP_NB
Current
Transient SENSE ISN_NB
Response
Enhancement VCC12_NB
COMP_NB BOOT_NB
FB_NB - MOSFET UGATE_NB
EA +
+ Driver PHASE_NB
+ RAMP_NB -
OV_NB LGATE_NB
-
+
1.8V

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 RT8855
Absolute Maximum Ratings (Note 1)
z Supply Input Voltage ---------------------------------------------------------------------------------------------------- −0.3V to 15V
z BOOTx to PHASEx ----------------------------------------------------------------------------------------------------- −0.3V to 15V
z BOOTx to GND
DC --------------------------------------------------------------------------------------------------------------------------- −0.3V to 30V
<200ns --------------------------------------------------------------------------------------------------------------------- −0.3V to 42V
z PHASEx to GND
DC --------------------------------------------------------------------------------------------------------------------------- −2V to 15V
<200ns --------------------------------------------------------------------------------------------------------------------- −5V to 30V
z Input/Output Voltage or I/O Voltage ---------------------------------------------------------------------------------- −0.3V to 7V
z Power Dissipation, PD @ TA = 25°C
WQFN−48L 7x7 ---------------------------------------------------------------------------------------------------------- 3.226W
z Package Thermal Resistance (Note 2)
WQFN-48L 7x7, θJA ----------------------------------------------------------------------------------------------------- 31°C/W
z Junction Temperature --------------------------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------------- 260°C
z Storage Temperature Range ------------------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Mode) --------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ---------------------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 4)

z Supply Voltage, VCC12 ------------------------------------------------------------------------------------------------ 12V ± 10%
z Junction Temperature Range ------------------------------------------------------------------------------------------ −40°C to 125°C
z Ambient Temperature Range ------------------------------------------------------------------------------------------ 0°C to 70°C

Electrical Characteristics
(VCC12 = 12V, GND = 0V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
VCC Supply Input
VCC12 Supply Voltage V VCC12 10.8 12 13.2 V
VCC12 Supply Current IVCC12 -- 10 -- mA
VCC12_NB Supply Voltage V VCC12_NB 10.8 12 13.2 V
VCC12_NB Supply Current IVCC12_NB -- 5 -- mA
VCC5 Power
VCC5 Supply Voltage V VCC5 ILOAD = 10mA 4.9 5 5.1 V
VCC5 Output Sourcing IVCC5 10 -- -- mA
Power-On Reset
VCC12 Rising Threshold V VCC12TH VCC12 Rising 9.2 9.6 10 V
VCC12 Hysteresis V VCC12HY VCC12 Falling -- 0.9 -- V
Input Threshold
Enable Input High Threshold V ENHI EN Rising 2 -- -- V
Enable Input Low Threshold V ENLO EN Falling -- -- 0.8 V
To be continued

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RT8855
Parameter Symbol Test Conditions Min Typ Max Unit
PWROK Input High Threshold V POKHI PWROK Rising 2 -- -- V
PWROK Input Low Threshold V POKLO PWROK Falling -- -- 0.8 V
VID5 to VID0 Rising Threshold V VID 5 to 0 VID5 to VID0 Rising 0.75 0.8 0.85 V
VID5 to VID0 Hysteresis V VID5 to 0 HYS VID5 to VID0 Falling -- 25 -- mV
VID5 to VID0 Pull-Down
IVID5 to 0 VVID5 to 0 = 1.5V -- 16 30 uA
Current
Reference Voltage accuracy
1V to 1.55V −0.5 -- +0.5 %
DAC Accuracy 0.8V to 1V −8 -- +8 mV
0.5V to 0.8V −10 -- +10 mV
Error Amplifier
DC Gain A DC No Load -- 80 -- dB
Gain-Bandwidth GBW CLOAD = 10pF -- 10 -- MHz
Slew Rate SR CLOAD = 10pF 10 -- -- V/us
Output Voltage Range V COMP RLOAD = 47kΩ 0.5 -- 3.6 V
Power Good
VDAC VDAC VDAC
Over-Voltage Threshold V PGOOD-OV FB Rising V
+210mV +240mV +270mV
VDAC VDAC VDAC
Under-Voltage Threshold V PGOOD-UV FB Falling V
−330mV −300mV −270mV
VDAC VDAC VDAC
Over-Voltage Threshold_NB V PGOOD-OV_NB FB_NB Rising V
+210mV +240mV +270mV
VDAC VDAC VDAC
Under-Voltage Threshold_NB V PGOOD-UV_NB FB_NB Falling V
−330mV −300mV −270mV
Power Good Low Voltage V PGOOD IPGOOD = 4mA -- -- 0.4 V
Current Sense Amplifier
VCSP = 1.3V
Max Current IGMMAX 100 -- -- uA
Sink Current from CSN
Input Offset Voltage V OSCS −2 0 +2 mV
Oscillator
Running Frequency fOSC RRT = 40kΩ 270 300 330 kHz
Ramp Amplitude V RAMP -- 1.6 -- V
Soft Start
Soft Start Slew Rate SRSS Slew Rate 2.5 3.25 4 mV/us
VID change Slew Rate SRVID Slew Rate 2.5 3.25 4 mV/us
Protection
V OVP Sweep FB Voltage 1.7 1.8 1.9 V
Over-Voltage Threshold
V OVP_NB Sweep FB_NB Voltage 1.7 1.8 1.9 V

To be continued

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 RT8855
Parameter Symbol Test Conditions Min Typ Max Unit
IOCP RIMAX = 40kΩ 68 80 92 uA
VIMAX RIMAX = 40kΩ 1.44 1.6 1.76 V
Over-Current Threshold
IOCP_NB RIMAX_NB = 40kΩ 68 80 92 uA
VIMAX_NB RIMAX_NB = 40kΩ 1.44 1.6 1.76 V
Gate Driver
BOOT − PHASE = 8V
UGATE Drive Source RUGATEsr -- 1 -- Ω
250mA Source Current
BOOT − PHASE = 8V
UGATE Drive Sink RUGATEsk -- 1 -- Ω
250mA Sink Current
LGATE Drive Source RLGATEsr VLGATE = 8V -- 1 -- Ω
LGATE Drive Sink RLGATEsk 250mA Sink Current -- 0.9 -- Ω

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a effective single layer thermal conductivity test board of
JEDEC thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

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RT8855
Application Information
The RT8855 is a dual output PWM controller supports Figure1. SVI interface also consider two additional signals
hybrid power control of AMD processors which operate needed to manage the system start-up. These signals
from either a 6-bit parallel VID interface (PVI) or a serial are EN and PWROK. The device asserts a PGOOD signal
VID interface (SVI). One of the outputs is a 4/3/2/1-phase if the output voltages are in regulation.
PWM controller with two integrated MOSFET drivers to
support CPU core voltage (VDD) and another is a single- Start Slave Addressing + W ACK Data Phase ACK Stop

phase buck controller with an integrated MOSFET driver

to power North-Bridge (NB) chipset (VDDNB) in SVI mode. 6 5 4 3 0 7 6 0
SVC
In PVI mode, only multiphase PWM controller is active
for single-plane VDD only processor. SVD
ACK ACK
110b
Richtek's proprietary Burst Transient Response(BTRTM), Start Slave Addressing Write ACK Data Phase ACK Stop
(7 Clocks) (1Ck) (1Ck) (8 Clocks) (1Ck)
provides fastest initial response to high di/dt load transients
and less bulk and ceramic output capacitance is required BUS Driven by RT8855 BUS Driven by Master (CPU)

to meet transient regulation specifications. The RT8855 Figure 1. SVI Communication-Send Byte
incorporates differential voltage sensing, continuous
inductor DCR phase current sensing, programmable load- Set VID Command
line voltage positioning and offset voltage to provide high
The Set VID Command is defined as the command
accuracy regulated power for both VDD and VDDNB. While
sequence that the CPU issues on the SVI bus to modify
VDDNB is enabled in SVI mode, it will be automatically
the voltage level of the Core section and NB section, as
phase-shifted with respect to the CPU Core phases in
shown is Figure 1. During a Set VID Command, the
order to reduce the total input RMS current amount.
processor sends the start (Start) sequence followed by
CPU_TYPE Detection and System Start-Up the address of the Section which the Set VID Command
applies. The processor then sends the write (WRITE) bit.
At system Start-up, on the rising-edge of EN signal,
After the write bit, The Voltage Regulator (VR) sends the
RT8855 monitors the status of VID1 and latches the PVI
acknowledge (ACK) bit. The processor then sends the
mode (VID1 = 1) or SVI mode (VID1 = 0).
VID bits code during the data phase. The VR sends the
PVI Mode acknowledge (ACK) bit after the data phase. Finally, the
processor sends the stop (Stop) sequence. After the VR
PVI is a 6-bit-wide parallel interface used to address the
has detected the stop, it performs an On-the-Fly VID
CPU Core section reference. According to the selected
transition for the addressed section(s). Refer to Table 3
code, the device sets the Core section reference and
for the details of SVI send byte.
regulates its output voltage according to Table 2. In this
mode, NB section is kept in high impedance. Furthermore, RT8855 is able to manage individual power off for both
PWROK information is ignored as well since the signal VCORE and NB sections. The CPU may issue a serial
only applies to the SVI protocol. VID command to power off or power on one section while
the other one remains powered. In this case, the PGOOD
SVI Mode signal remains asserted.
SVI is a two wire, Clock and Data, bus that connect a
single master (CPU) to one slave (RT8855). The master
initiates and terminates SVI transactions and drives the
clock, SVC, and the data, SVD, during a transaction. The
slave receives the SVI transactions and acts accordingly.
SVI wire protocol is based on fast-mode I2C as shown in

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 RT8855
Table 3. SVI Send Byte-Address and Data Phase Table 4. V_FIX Mode and Pre-PWROK Metal VID
Description / Example Output Voltage (V)
bits Description SVC SVD Pre-PWROK
Address Phase V_FIX Mode
Metal VID
6 : 4 Always 110b
3 Not Applicable, ignored. 0 0 1.1V 1.4V
2 Not Applicable, ignored. 0 1 1.0V 1.2V
CORE Section. (Note) 1 0 0.9V 1.0V
1 If set then the following data byte contains the
1 1 0.8V 0.8V
VID code for CORE Section.
NB Section. (Note)
0 If set then the following data byte contains the Power Ready Detection
VID code for NB Section. During start-up, RT8855 will detect VCC12, VCC5 and
Data Phase
EN signal. Figure 2 shows the power ready detection
PSI_L Flag (Active Low). When asserted, the
7 circuit. When VCC12 > 9.6V and VCC5 > 4.6V, POR
VR is allowed to enter Power-Saving Mode.
6 : 0 VID Code. (Power On Reset) will go high. POR is the internal signal
Note : Assertion in both bit 1 and 0 will address the VID to indicate all input powers are ready to let RT8855 and
code to both CORE and NB simultaneously. the companioned MOSFET drivers to work properly. When
Example : POR = L, RT8855 will turn off both high side and low side
SVI Address MOSFETs.
Description
Bits [6 : 0] CMP
VCC12 +
1100_000 Should be ignored. 9.6V -
1100_001 Set VID on VDDNB.
CMP
1100_110 Set VID on VDD0 and VDD1. VCC5 + POR
4.6V -
1100_100 Set VID on VDD1. Chip Enable
1100_010 Set VID on VDD0 or VDD (uniplane). EN

Set VID on VDDNB, VDD0 and

1100_111
VDD1. Figure 2. Circuit for Power Ready Detection

Power-Up Sequencing
PWROK De-assertion
Figure 3 and 4 are the power-up sequencing diagram of
PWROK stays low after EN signal is asserted, and the
RT8855. Once power_on_reset is valid (POR = H), on the
controller regulates all the planes according to the Pre-
rising edge of the EN signal, the RT8855 detects the VID1
PWROK Metal VID.
pin and determine to operate either in SVI or PVI mode.
PGOOD is de-asserted as long as Pre-PWROK Metal VID Figure3 shows the PVI-mode power sequence, the
voltage is out of the initial voltage specifications. controller stays in T1 state waiting for valid parallel VID
code sent by CPU. After receiving valid parallel VID code,
V_FIX Mode Function
VCORE continues ramping up to the specified voltage
Anytime the pin VID0/VFIXEN is pulled high, the controller according to the VID code in T2 state. Figure 4 shows the
enters V-FIX mode. When in V_FIX mode, both VCORE SVI-mode power sequence, the controller samples the
and NB section voltages are governed by the information two serial VID pins, SVC and SVD. Then, the controller
shown in Table 4. Regardless of the state of PWROK, the stores this value as the boot VID that is the so-called
device will work in SVI mode. SVC and SVD are considered “Pre-PWROK Metal VID” in T1 state. After the processor
as static VID and the output voltage will be changed starts with boot VID voltages, PWROK is asserted and
according to their status. Dynamic SVC/SVD-change the processor initializes the serial VID interface in T2 state.
management is provided in this condition. V_FIX mode is The processor uses the serial VID interface to issue VID
intended for system debug only. commands to move the power planes from the boot VID
values to the dual power planes in T3 state.
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 RT8855
VCC12 9.6V 8.7V
L DCR
VCC5 4.6V 4.2V
POR CS
RS
EN CSA: Current Sense Amplifier
VID(1)/PVI xx
ISP R CSP
PVI mode xx Valid 235nA +
(6-bits)
V OFS_CSA +
IX -
ISN R CSN
-
VDD 235nA

PGOOD

PWROK
T2
T1 Figure 5. Current Sensing Circuit.

Figure 3. PVI-Mode Power-sequencing Diagram CORE Section- Phase Detection

The number of the operational phases is determined by
VCC12 9.6V 8.7V
the internal circuitry that monitors the ISNx voltages during
VCC5 4.6V 4.2V
start up. Normally, the RT8855 operates as a 4-phase
POR
EN
PWM controller. Pull ISN4 and ISP4 to 5VCC programs
VID(1)/PVI xx 3-phase operation, pull ISN3 and ISP3 to 5VCC programs
SVC xx Valid 2-phase operation, and pull ISN2 and ISP2 to 5VCC
SVD xx Valid programs 1-phase operation. RT8855 detects the voltage
Vboot
of ISN4, ISN3 and ISN2 at rising edge of POR. At the
VDD or
VDDNB rising edge, RT8855 detects whether the voltage of ISN4,
PGOOD ISN3 and ISN2 are higher than “VCC5-1V” respectively
PWROK to decide how many phases should be active. Phase
T1 T2 T3
detection is only active during start up. Once POR = high,
Figure 4. SVI-Mode Power-sequencing Diagram the number of operational phases is determined and
latched.
CORE Section- Output Current Sensing
The RT8855 provides a low input offset current-sense CORE Section- Switching Frequency
amplifier (CSA) to monitor the continuous output current Connect a resistor (RT) from the RT pin to GND can program
of each phase for VCORE. Output current of CSA (IX[n]) is the switching frequency of each phase. Figure 6 shows
used for current balance and active voltage position as the relationship between the resistance and switching
shown in Figure 5. In this inductor current sensing topology, frequency.
RS and CS must be set according to the equation below : Frequency vs. RRT
1200
L = R ×C
S S
DCR 1000

Then the output current of CSA will follow the equation

Frequency (kHz)

800
below :
[IL × DCR − VOFS-CSA + 235nA × (RCSP − RCSN )] 600
IX =
RCSN
400
235nA is the typical value of the CSA input offset current.
VOFS-CSA is the input offset. Usually, “VOFS-CSA + 235nA x
200
(RCSP − RCSN)” is negligible except at very light load and
the equation can be simplified as the equation below : 0
0 40 80 120 160 200 240 280
IL × DCR
IX = RRT (k ohm)
(kΩ)
RCSN
Figure 6. RRT vs. Phase switching Frequency.
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 RT8855
CORE Section- Differential Output Voltage Sensing VOFSP = IOFSP × RFB − 9u × R ADJ
The RT8855 uses differential voltage sensing by a high R
= 0.4 × FB − 9u × R ADJ
ROFS
gain low offset ErrorAmp as shown in Figure 7. Connect
the negative on-die CPU remote sense pin to FBRTN.
CORE Section- Programmable Load-line
Connect the positive on-die remote sense pin to FB with
a resistor (R FB ) The ErrorAmp compares EAP Output current of CSA is summed and averaged in
( = VDAC − VADJ) with the VFB to regulate the output voltage. RT8855. Then 0.5Σ (IX[n]) is sent to ADJ pin. Because
Σ IX[n] is a PTC (Positive Temperature Coefficient) current,
C2
an NTC (Negative Temperature Coefficient) resistor is
CFB C1 needed to connect ADJ pin to GND. If the NTC resistor is
R1
properly selected to compensate the temperature
RFB IOFSN
coefficient of I X[n], the voltage on ADJ pin will be
VCCP FB
(Positive remote proportional to IOUT without temperature effect. In RT8855,
sense pin of CPU)
the positive input of ErrorAmp is “VDAC − VADJ” . VOUT will
-
+
EA
COMP
follow “VDAC − VADJ” , too. Thus, the output voltage
IOFSP
decreasing linearly with IOUT is obtained. The loadline is
defined as :
ΔVOUT ΔVADJ 1 R
+- LL(loadline) = = = × DCR × ADJ
VDAC
+ EAP ΔIOUT ΔIOUT 2 RCSN
(Negative remote
-
sense pin of CPU)
VCCN Briefly, the resistance of RADJ sets the resistance of
FBRTN
RADJ loadline. The temperature coefficient of RADJ compensates
ADJ
the temperature effect of loadline.

Figure 7. Circuit for VCORE Differential Sensing and No

CORE Section- Load Transient Quick Response
load Offest.
In steady state, the voltage of VFB is controlled to be very
close to VEAP. While a load step transient from light load
CORE Section- No-Load Offset
to heavy load could cause VFB lower than VEAP by several
In Figure 7, IOFSP and IOFSN are used to generate no-load
tens of mV. In prior design, owing to limited control
offset. Either IOFSP or IOFSN is active during normal operation.
bandwidth, controller is hard to prevent VOUT undershoot
Connect a resistor from OFS pin to GND to activate IOFSN.
during quick load transient from light load to heavy load.
IOFSN flows through RFB from FB pin to VCCP. In this case,
RT8855 buit in proprietary Burst Transient Response
negative no-load offset voltage (VOFSN) is generated.
(BTRTM ) technology, that detects load transient by
Connect a resistor from OFS pin to 5VCC to activate IOFSP. comparing VFB and VEAP. If VFB suddenly drops below
IOFSP flows through RFB from the VCCP to FB pin. In this “VEAP − VOR” , VQR is a predetermined voltage. The quick
case, positive no-load offset voltage (VOFSP) is generated. response indicator QR rises up. When QR = high, RT8855
Beside IOFSN and IOFSP, the RT8855 generates another DC turns on all high side MOSFETs and turn off all low side
current for initial no-load negative offset. A DC current MOSFETs. The sensitivity of quick response can be
source will continuously inject typical 9uA current into adjusted by the values of CFB and RFB. Smaller RFB and/
the resistors connected to ADJ pin, Therefore, the effect or larger CFB will make QR easier to be trigger. Figure8 is
of this 9uA current source and ADJ resistors should the circuit and typical waveforms.
counted into the calculation of no-load offset :
VOFSN = IOFSN × RFB + 9u × R ADJ
R
= 0.4 × FB + 9u × R ADJ
ROFS

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 RT8855
CFB C2
IOUT
VOUT
VOUT RFB R1 C1
I1
FB
FB COMP
I2

- - FB = VEAP
QR
+ + = VEAP - VQR
EAP = VDAC - VADJ IOUT, total
EAP - VQR Constant ratio
QR

Figure 8. Load Transient Quick Response

I1
CORE Section- Current Balance
I2
In Figure9, IX[n] is the current signal which is proportional
to the current flowing through channel n. The current error
signals IERR[n] ( = IX[n] − AVG(IX[n])) are used to raise or IOUT, total

lower the valley of internal sawtooth waveforms (EAMP[1] Constant difference

to RAMP[n]) which are compared with ErrorAmp output Figure 10. Category of Phase Current Imbalance
(COMP) to generate PWM signal. To raise the vally of
sawtooth waveform will decrease the PWM duty of the CORE Section-Over Current Protection (OCP)
corresponding channel while to lower the sawtooth V IN
waveform valley will increase the PWM duty. Eventually, ILX
HS L
current flowing through each channel will be balanced. PWM X DCR X
Controller
COMP RX CX
LS
OCP Comparator
+
CMP BUF PWM[1]
-
+

RAMP[1] + -
- 1/4IIMAX 1/8IX

Interleaved IERR [1] x R CB +

4 8 GM R CSNX
+ 1.6V + -
RAMP[n] CMP BUF PWM[n]
+ - - IIMAX
-
IX
V IMAX
IERR [n] x R CB
RT8855 CORE section
R IMAX
Figure 9. Circuit Channel Current Balance

CORE Section- Phase Current Adjustment Figure 11. Over Current Protection for CORE section.

If phase current is not balanced due to asymmetric PCB

CORE section uses an external resistor RIMAX connected
layout of power stage, external resistors can be adjusted
to IMAX pin to generate a reference current IMAX for over
to correct current imbalance. Figure10 shows two types
current protection as depicted in Figure 11.
of current imbalance, constant ratio type and constant
VIMAX
difference type. If the initial current distribution is constant IIMAX =
RIMAX
ratio type, according to Equation (3), reducing RCSN[1]
where VIMAX is typical 1.6V. RT8855 senses each phase
can reduce IL[1] and improve current balance. If the initial
current IX and OCP comparator compares sensed average
current distribution is the constant difference type,
current with the reference current. Equivalently, the
according to Equation (2), increasing RCSP[1] can reduce
maximum phase average current ILX(MAX) is calculated as
IL[1] and improve current balance.
below :

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 RT8855
1 ×I 1
IMAX = × IX(MAX)
4 8 L NB DCR NB
V
IX(MAX) = 2 × IIMAX = 2 × IMAX
RIMAX R S_NB
C S_NB
R V R
ILX(MAX) = IX(MAX) × CSNX = 2 × IMAX × CSNX CSA: Current Sense Amplifier
DCR X RIMAX DCR X +
IX_NB R CSN_NB
-
Once IX is larger than 2 x IIMAX, OCP of CORE section is
triggered and latched. Then, RT8855 will turn off both high
side MOSFET and low side MOSFET of all channels. A Figure 12. Current Sensing Circuit for NB Section
100us delay is used in OCP detection circuit to prevent
false trigger. NB Section- Over Current Protection (OCP)

Except the normal OCP function described above, there NB section uses an external resistor RIMAX_NB connected
is another short-circuit-OCP function especially designed to IMAX_NB pin to generate a reference current IMAX_NB
for short circuit protection. Since short circuit may cause for over current protection as depicted in Figure 13.
catastrophic damage over a very short period, this short- VIMAX_NB
IIMAX_NB =
circuit-OCP should have a very short delay for triggering RIMAX_NB
OCP latch. Also to prevent false trigger, the trigger level where VIMAX_NB is typical 1.6V. OCP comparator compares
of short-circuit-OCP is designed 1.5 times of normal OCP the sensed phase current IX_NB with the reference current.
level. Hence, the equation of short-circuit-OCP is : Equivalently, the maximum phase NB current ILX_NB(MAX)
V R is calculated as below :
ILX(MAX), short = 1.5 x ILX(MAX) = 3 × IMAX × CSNX ,
RIMAX DCR X
1 ×I 1
and the delay of short-curcuit-OCP is 20us. when short- IMAX_NB = × IX_NB
4 8
circuit-OCP is triggered, the RT8855 will turn off both high VIMAX_NB
IX_NB = 2 × IIMAX_NB = 2 ×
side MOSFET and low side MOSFET of all channels. RIMAX_NB
RCSN_NB
ILX_NB(MAX) = IX_NB ×
CORE Section- Over Voltage Protection (OVP) DCRNB
VIMAX_NB RCSN_NB
The over voltage protection monitors the output voltage = 2× ×
RIMAX_NB DCRNB
via the FB pin. Once VFB exceeds 1.8V, OVP is triggered
and latched for VCORE section. RT8855 will try to turn Once IX_NB is larger than 2 x IIMAX_NB, OCP of NB section
on each low side MOSFET and turn off each high side is triggered and latched. Then, RT8855 will turn off both
MOSFET to protect CPU. high side MOSFET and low side MOSFET of NB section.
A 100us delay is used in OCP detection circuit to prevent
NB Section- Output Current Sensing false trigger.
The RT8855 provides low input offset current-sense Except the normal OCP function described above, there
amplifier (CSA) to monitor the continuous output current is another short-circuit-OCP function especially designed
of NB scetion. Output current of CSA (IX_NB) is used for for short circuit protection. Since short circuit may cause
over current detection as shown in Figure 12. In this catastrophic damage over a very short period, this short-
inductor current sensing topology, RS_NB and CS_NB must circuit-OCP should have a very short delay for triggering
be set according to the equation below : OCP latch. Also to prevent false trigger, the trigger level
LNB of short-circuit-OCP is designed 1.5 times of normal OCP
= RS_NB × CS_NB
DCRNB
level of NB section. Hence, the equation of NB section
Then the output current of CSA will follow the equation short-circuit-OCP is :
below : ILX_NB(MAX), short = 1.5 x ILX_NB(MAX)
IL_NB × DCRNB VIMAX_NB RCSN_NB
IX_NB = = 3× × ,
RCSN_NB RIMAX_NB DCRNB
DS8855-01 April 2011 www.richtek.com
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RT8855
and the delay of short-curcuit-OCP of NB section is 20us. 5VCC
When short-circuit-OCP is triggered at NB section, the
PSOC2P (1) 5VCC for (4 phase to 2 phase)
RT8855 will turn off both high side MOSFET and low side
Latch (2) 3.3V for (4 phase to 1 phase)
MOSFET of NB section.
EN VDDIO
V IN

HS ILX PS
PSIA Control
L X_NB DCR
PWM NB
Controller
PSI PSI
(From I2C) (Active Low)
LS
OCP Comparator R X_NB C X_NB
-
+

1/4IIMAX_NB 1/8IX_NB Figure 14. Power-Saving-Mode Circuit.

+
4 8 GM Table 5. PSI Strategy
1.6V + -
R CSN_NB
- IIMAX_NB PS pin PSI Strategy
IX_NB
V IMAX_NB
Phase number is set to 1 while
Pull-Up to 3.3V
RT8855 NB section PSI is asserted.
R IMAX_NB
Phase number is set to 2 while
Pull-Up to 5V
PSI is asserted.
Figure 13. Over Current Protection for NB section.

PCB Layout Guideline

NB Section- Over Voltage Protection (OVP)
Careful PCB layout is critical to achieve low switching
The over voltage protection monitors the output voltage losses and clean, stable operation. The high-power
via the FB_NB pin. Once VFB_NB exceeds 1.8V, OVP is switching power stage requires particular attention. Follow
triggered and latched for NB section. RT8855 will try to these guidelines for optimum PCB layout.
turn on low side MOSFET and turn off high side MOSFET
Place the power components first, that includes power
to protect NB.
MOSFETs, input and output capacitors, and inductors. It
Power Saving Indicator (PSI) is important to have a symmetrical layout for each power
train, preferably with the controller located equidistant from
This is an active-low flag that can be set by the CPU to
each. Symmetrical layout allows heat to be dissipated
allow the regulator to enter Power-Saving mode to
equally across all power trains. Great attention should be
maximize the system efficiency when in light-load
paid for routing the UGATE, LGATE, and PHASE traces
conditions. The status of the flag is communicated to the
since they drive the power train MOSFETs using short,
controller through either the SVI bus or PS pin. RT8855
high current pulses. It is important to size them as large
monitors the PS pin to define the PSI strategy that is the
and as short as possible to reduce their overall impedance
action performed by the controller when PSI is asserted.
and inductance. Extra care should be given to the LGATE
According Figure 14, by programming different voltage on traces in particular since keeping their impedance and
PS pin, it configures the controller to operate in one or inductance low helps to significantly reduce the possibility
two phases condition when PSI is asserted. Pulling-up of shoot-through.
PS pin to 3.3V through a resistor, the controller operates
When placing the MOSFETs try to keep the source of the
in only 1 phase configuration. If the 3.3V is changed to
upper MOSFETs and the drain of the lower MOSFETs
5V, RT8855 operates in 2 phase configuration. When PSI
and as close as possible. Input Bulk capacitors should
is de-asserted, the controller will return to the original
be placed close to the drain of the upper MOSFETs and
configuration. The PSI strategy is summarized as shown
and the source of the lower MOSFETs and .
in Table 5.

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 RT8855
Locate the output inductors and output capacitors between
the MOSFETs and the load. Route high-speed switching
nodes away from sensitive analog areas (ISP, ISN, FB,
FBRTN, COMP, ADJ, OFS, IMAX.....)
Keep the routing of the bootstrap capacitor short between
BOOT and PHASE.
Place the snubber R&C as close as possible to the lower
MOSFETs of each phase.

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RT8855
Outline Dimension

2 1 2 1

DETAIL A
Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.200 0.300 0.008 0.012
D 6.950 7.050 0.274 0.278
D2 5.050 5.250 0.199 0.207
E 6.950 7.050 0.274 0.278
E2 5.050 5.250 0.199 0.207
e 0.500 0.020
L 0.350 0.450 0.014 0.018
W-Type 48L QFN 7x7 Package

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Headquarter Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

www.richtek.com DS8855-01 April 2011

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