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HFIC Chapter 13 SoC Design Flow

This document outlines the design flow for millimeter-wave systems-on-chip (SoCs). It describes a hierarchical top-down design approach moving from system-level specification to transistor-level implementation. Key aspects discussed include block-level modeling and layout, basic cell design including inductors, and addressing layout issues specific to millimeter-wave frequencies. Examples of millimeter-wave integrated circuits above 60 GHz are provided including 60 GHz phased arrays and 77 GHz automotive radar.

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Rachana Srinivas
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174 views47 pages

HFIC Chapter 13 SoC Design Flow

This document outlines the design flow for millimeter-wave systems-on-chip (SoCs). It describes a hierarchical top-down design approach moving from system-level specification to transistor-level implementation. Key aspects discussed include block-level modeling and layout, basic cell design including inductors, and addressing layout issues specific to millimeter-wave frequencies. Examples of millimeter-wave integrated circuits above 60 GHz are provided including 60 GHz phased arrays and 77 GHz automotive radar.

Uploaded by

Rachana Srinivas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Chapter 13.

SoC Design Flow

Outline
Design flow for HF ICs
Examples of mm-wave ICs

Top-down design flow for mm-wave SoCs


System level specification,
high-level model
Symbol, I/O, layout placeholder
Block level specification
high-level model
Symbol, I/O, layout placeholder
Transistor-level schematic
design of basic cells
high-level model

System layout, extraction,


Simulation, verification

Block level layout, extraction


and simulation, verification

Basic cell inductor design,


Inductor model
Cell layout, simulation after
extraction

SYSTEM level

Block (sub-block) level

Cell level

Transistor layout and extraction

Design flow for HF ICs in nanoscale CMOS


Check MOSFET model for sanity:
peak fT current density = 0.3mA/m ... 0.4 mA/m
Add RG and check fMAX, NFMIN and JOPT = 0.12-0.15 mA/m
Transistor/varactor cell optimization: Wf to balance RS, RG and
minimize Cgd and other parasitics. Fix Wf and vary just Nf.
Schematic level design with RG added to MOSFET digital model
Transistor(cascode,CMOS inverter) layout optimization: choice of
metal stack on drain and source depending on: CS, CG, CD,
cascode, CMOS inv
monitor fMAX, NFMIN, gain
Parasitic resistance seems to be the killer in 65nm and beyond

Design flow for HF ICs in nanoscale CMOS (ii)


Include RC-extracted transistor(cascode/CMOS inv)
layout in schematic (expect significant > 20% performance
degradation)
Design inductors and interconnect in EM simulator based
on schematic-level design with extracted transistors and
pad capacitance
Add metal ground and power mesh to cell and RC-extract
cell (without inductors)
Add inductor and interconnect models to schematic of
RC-extracted cell
Add interconnect modelled in ASITIC between cells

Example: Hierarchical breakout of cell


for parasitic extraction
VDD = 1 V
VDD = 1 V

330

330

330

330

1 nH

1 nH

OUT
OUT

Q1
Q1

Q2

Q3

LVT

DATA

Q4

DATA

Q2

Q3

LVT

LVT

LVT
CLK

HVT

CLK

HVT

HVT

Minimize cell layout footprint to reduce capacitance


Extract cell RC
Model inductors and long interconnect in ASITIC

Q4

HVT

Layout Issues
Specific to mm-waves:
For performance: gate finger width in LNA/VCO
For all applications using nano-scale CMOS:
For manufacturability (antenna rules, OPC)
For variability (strain, stress, and process variation)

D1

D2

D2

Dummy

G1

G1

G2

G2

G2

G2

G1

G1

Dummy

Diff. pair layout in nano-CMOS technologies

D1

Transistors share the same well and are interspersed


symmetrically to minimize impact of process variation
All fingers have the same orientation, W f, L, to avoid
photolithography problems and strain variation
Dummy gates are placed on each side to ensure L uniformity, ease
photolithographical phase correction, and reduce impact of strain
variation

CMOS Latch, Selector, and Gilbert Cell Layout


R R R
1 2 1

DUMMY

R1

VDD = 1 V
330

R2

1 nH

330

R R
1 2

R
2

DUMMY

1 nH

OUT

D1

D2

D2

D1

D1

D2

D1

D2

D2

Dummy

G1

G1

G2

G2

G2

G2

G1

HVT Pair

G1

HVT

Dummy

CLK

HVT

D1

D2

G1

Dummy

G1

G2

G2

G2

G2

G1

G1

Dummy

G1

Dummy

G1

G2

G2

LVT

G2

Q4

G2

Q3

G1

Q2

LVT

G1

Q1
DATA

Dummy

LVT QUAD

D1

Colpitts VCO Layout


Components are placed as
close as possible to each
other

C2

C1

Merged varactor pair with


shared n-well
Transistor fingers narrow
and contacted on both
sides (not shown)
Dummy gates on side to
minimize variability due to
STI-induced strain

C1

C2

Cross-Coupled VCO Layout


(K. Tang, et al CSICS-06)

Merged cross-coupled and buffer pair to minimize


interconnect capacitance

Bias and ground distribution and decoupling


Fine ground mesh with grounded substrate taps throughout
the circuit
At least two metals shunted together on ground mesh
Distributed de-coupling of power supply mesh over ground
mesh
Local MIM (0.5pF - 1pF) de-coupling to ground if available
Careful with MOM caps to ensure high Q
45 degree angles no longer allowed in 45nm

Bias Distribution (E. Laskin, ISSCC-08)

Metal mesh distributes ground, VDD, bias to all cells


Substrate contacts, distributed decoupling, low R, L
Meets all density rules

Signal distribution : t-line groundplane loss


5 m

5 m

3 m

3 m

7.5 m

2 m

8.2 m

1 m

Local supply distribution and de-coupling

Bias de-coupling in 100-GHz transceiver

Signal and block-to-block isolation strategies


GND

mm-wave

GND

Shielded bias/control
line

p+ p+ p+ p+ p+ p+ p+ p+ p+ p+ p+ p+ p+ p+ p+ p+ p+ p+ p+

p+ p+ p+ p+ p+ p+ p+ p+ p+ p+

SILICON SUBSTRATE: p-

Mm-wave transceiver examples


60-GHz CMOS and SiGe BiCMOS wireless phased arrays
77-GHz SiGe BiCMOS automotive radar transceiver
70-80 GHz SiGe BiCMOS active imaging array with digital
beamforming
140 to 170-GHz SiGe BiCMOS sensor transceivers with ondie BIST and antennas

60-GHz 1.5-5 Gb/s wireless links

SiGe BiCMOS 60-GHz phased array receiver

SiGe BiCMOS 60-GHz phased array receiver

SiGe BiCMOS 60-GHz phased array transmitter

65-nm CMOS 60-GHz receiver phased array

65-nm CMOS 60-GHz receiver phased array

77-GHz Automotive Radar


[5]

W-Band active imaging array with digital


beamforming

[7]

[S.S. Ahmed et al, IEEE Microwave Magazine October 2012]

Antenna array clusters

[7]

[S.S. Ahmed et al, IEEE Microwave Magazine October 2012]

Digital beamforming array concept

[S.S. Ahmed et al, IEEE Microwave Magazine October 2012]

Blcok diagram of single array

[S.S. Ahmed et al, IEEE Microwave Magazine October 2012]

RX and TX array elements

[7]

Differential LNA with ESD protection

Chip packaging

Push-push 150-170GHz Doppler transceiver


IF1 OUT

[28]
AM-MOD

148-170GHz

LO
AMP

LNA
RX1

LO
AMP

TX
AMP
TX ANT

74-85GHz

LO
AMP

LNA
RX2

/128

TXPD

fREF
578-664MHz

PLL

IF2 OUT

Monostatic 120/150 GHz distance sensors


890 mW with both
prescalers on from
1.8V and 1.2V supplies

[I. Sarkas et al.CSICS 2012]

Layout and performance summary


130nm SiGe BiCMOS technology,
HBT fT/fMAX= 230/280 GHz
Tuning range 143-152 GHz
NF<10 dB, Pout >-6 dBm
PN < -83 dBc/Hz at 1MHz
PDC = 800 mW

2.6mm2.3mm

Coupler with detectors

Coupler with detectors: Linearity

Digital Tuner States

1.0j

1.0j
0.5j

0.5j

2.0j

2.0j

122 GHz

145 GHz

0.2j

5.0j

0.2

0.5

1.0

2.0

-5.0j

-2.0j
-1.0j

5.0j

0.2

5.0

-0.2j

-0.5j

0.2j

0.5

1.0

2.0

5.0

-0.2j

-5.0j

-0.5j

-2.0j
-1.0j

145 GHz fundamental frequency VCO


152

Oscillation Frequency (GHz)

151

Coarse = 1.4V

150
149
148

Coarse = 0.8V

147
146
145
144

Coarse = 0V

143
142
0.0

0.2

0.4

143-152 GHz tuning range

PN=-103 dBc/Hz @10MHz offset

PDC = 72 mW

0.6
0.8
1.0
Fine Control (V)

1.2

1.4

39

Measured output power


-3
-4

TX Power (dBm)

-5

TX detector thru outputAntenna port terminated

-6
-7

Antenna port open

-8
-9
-10
-11

Antenna port
(after 6dB coupler)

-12
-13
-14
144 145 146 147 148 149 150 151 152 153
Frequency (GHz)

Power at antenna port measured with ELVA power sensor

On-chip and external measurements track very well

40

Receiver schematics

Receiver Gain and Noise Figure

Gain - DSB Noise Figure (dB)

16
15
14

Gain

13
12
11
10

NF

9
8

142 143 144 145 146 147 148 149 150 151 152 153

LO Frequency (GHz)

13-15 dB gain, 23 dB of gain control in LNA


Low noise figure: 8.5-10.5dB
42

Antenna and die in package


QFN package with
bondwire transition to
antenna on alumina

Courtesy of Robert Bosch


GmbH, Karlsruhe Institute of
Technology and EU SUCCESS
project partners
43

120-GHz Distance Sensor

Psat > 3 dBm


1.2/1.8V,
PD=0.9W

NF = 10 dB
RX Gain = 12 dB
PN= -100 dBc/Hz
[I. Sarkas et al. Trans. MTT, March 2012]

Layout and Packaging

Chip: 2.2mm2.6mm

Package: 7mmmm

Dr. J. Hasch

130-nm BiCMOS9MW: SiGe HBT fT= 230 GHz, fMAX = 280 GHz

Summary
Inductors and transformers are scalable to at least 200 GHz
Accurate modelling of passives is as critical as transistor models
Transistor layout is critical to nanoscale CMOS circuit
performance
Layout parasitics can degrade CMOS IC performance by as
much as one technology node
HF SoC performance critically dependent on
supply distribution and de-coupling strategies
Signal and block-to-block isolation strategies
Examples of mm-wave ICs above 60 GHz

TX/RX Packaging

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