2/24/2023

Dr. Ibrahim L. Abdalla

Integrated Circuits Laboratory (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Zagazig University

Integrated Circuits
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

Outline
 Course Description and Outline
 Course Administration
 Course Grade
 Syllabus

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Course Description and Outline

ECE326 Integrated Circuits
CMOS Combinational Digital Circuit: CMOS Inverter, Noise Margin, Propagation delay, Power
consumption, Layout and Lambda-Based Design Rules. CMOS Static Structure. Pass Transistor and
Transmission Gate Logic. CMOS Dynamic Structure, CMOS DOMINO.
CMOS Sequential Digital Circuits: Flip-Flops, Shift Registers, Counters, Latches. Pipelined Structures.
CMOS Schmitt Trigger. CMOS Ring Oscillator and VCO.
Semiconductor Memories: RAM, ROM, EPROM, EEPROM, SRAM, DRAM, Row and Column Decoders.
Array Structure: PLA, Finite State Machine.

Course Description and Outline

Course goals
Upon successful completion of this course, the student should be able to:
 Understand the basic principles and theory of operation of static and dynamic digital
circuits;
 Understand design rules for VLSI technology;
 Analyze CMOS Digital Circuits in Transistor Level;
 Determine the Performance of CMOS Digital Circuits in Terms of Noise-Margin, Speed,
and Power Dissipation;
 Design, simulate and implement static and dynamic digital circuits with emphasis on the
performance and chip area;
 Implement digital sub-systems with the optimization of total number of transistors,
propagation delay, and power consumption;
 Utilize the Electronic Design Automation (EDA) to deal with all analysis and design
issues of the electronic systems
Course prerequisites
 ECE321, CSE255

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Course Administration
Instructors Assis. Prof. Ibrahim L. Abdalla
The Electrical Building Rm: 27406
Office Hrs.: Sun 10:00-12:00
Lectures 2:15hrs a week
Tus. 10:10-12:25 @ 27520
TAs  Eng. Mohamed Tarek
Labs EDA Lab, Room 27508, Electrical Building
URL http://admineng.eps.zu.edu.eg/Views/StudentViews/StudentLogin
Text  Jan M. Rabaey, “Digital Integrated Circuits, A Design Perspectives,” 2nd edition, Prentice
Hall 2003.
Notes Lecture slides and Quizzes/Assignments/Project – on ZUEP

Course Grade

Evaluation Written Quizzes Attendance Project Total

Coursework 15 15 15 45

Final 80 80

Oral Exam

TOTAL 125

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Syllabus

Lec. Items/Topics Assignments

Course Description and Outline, Definitions and Terminologies, State-of-the art of

1
CMOS Technology, Design Rules, MOSFET Model, MOSFET Characteristics
Scaling and Reliability, Static Behaviour of CMOS Inverter, Dynamic Behaviour of CMOS
2
Inverter, Power, Energy, and Energy Delay
Design of Static CMOS Combinational Logic Gates (1), Design of Static CMOS
3-4
Combinational Logic Gates (2), Dynamic Logic: Basic Principles
Cascading Dynamic Gates, Speed and Power Dissipation of Dynamic Logic, Signal
5-6
Integrity Issues in Dynamic Design,
Introduction to Sequential Logic Circuits
7
Static Latches and Registers (1), Static Latches and Registers (2)
8 Midterm Exam

Syllabus

Lec. Items/Topics Assignments

Dynamic Latches and Registers , Pipelining Structures, NORA-CMOS- A Logic Style for
9
Pipelined Structures

10 Design Sequential Logic Circuits: Choosing a Clocking Strategy

11 Nonbistable Sequential Circuits, Designing Memory and Array Structures, The Memory Core

12 Memory Peripheral Circuitry (1), Memory Peripheral Circuitry (2)

Datapath, ALU: Adder Design , Datapath, ALU: Multiplier Design, Datapath, ALU: Shifter
13
Design

14 Final Review

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Definitions and Terminologies

1. Small Scale Integration (SSI): The Integrated Circuit (IC) includes several logic gates in
a single package.
2. Medium Scale Integration (MSI): The Integrated Circuit (IC) must perform a complete
logic function (Adders, Multipliers, Decoders, Encoders, …) and have complexity up to
100 gates.
3. Large Scale Integration (LSI): the IC performs a logic function with more than 100
gates and less than 1000 gates such as RAMs and ROMs.
4. Very large-Scale Integration (VLSI): the IC contains thousands or million of gates in a
single chip such as Processors.

Definitions and Terminologies (Continue)

5. A standard IC: It is available off-the-shelf and can fit in many applications (Examples:
gates, FFs, counters, memories, µPs, controllers, … etc). Standard ICs are fabricated in large
numbers (producing volume more than 1 million pieces).
6. Application Specific Integrated Circuit (ASIC): They are not available commercially.
They are designated for the customer and in many cases the designer is the customer himself
(Examples: most systems on chip and integration of standard ICs). ASICs are fabricated in
small or moderate volume (few pieces to 100000 or more).

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Definitions and Terminologies (Continue)

7. Electronic Design Automation (EDA): They are the software package that help in IC
design and testing (e.g. EDA Companies: Cadence, Mentor Graphics, Synopsis, Tanner, …).
8. Intellectual Property (IP): It is a special product designed and provided by a Company or a
Design Centers (e.g. Pentium-4 processor, controllers,.).
9. Silicon Foundries: Companies that fabricate the designed ICs (e.g. TSMC, UMC, AMS,
MOSIS, …).
10. Integrated Device Manufactures (IDM): Companies that design and fabricate devices
(e.g. IDM Companies TI, Philips, S T Micro-electronics, NEC,.).

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Definitions and Terminologies (Continue)

11. Technology Feature size: It represents the minimum length of the channel of the fabricated
transistor (e.g. 1µm, 0.5µm, 0.35µm, 0.25µm, 0.18µm technology). Submicron transistor (L
< 1 micron) and deep submicron device (L < 0.25 micron ).

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Definitions and Terminologies (Continue)

12. Clean Room: It is most critical part of foundry that controls its operating conditions such
as: air flow, dust particle size, pressure, temperature, humidity, electromagnetic shielding,
electrostatic shielding, noise and micro-vibrations.

13. Clean Room Class: It is number of particles of diameter > 0.5 µm/ft3 (e.g. clean room class
1 means that only one particle of diameter > 0.5 µm/ft3 and clean room class 10 means that
only 10 particle of diameter > 0.5 µm/ft3. Note that human hair diameter is 60 µm and
tobacco smoke ranges from 0.3 to 1 µm) Particles may cause short-circuit, partial or wire
open circuit.

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Clean Room Controlled Parameters

Air Cleaning

Micro- Temperature
Vibration /Humidity

Ultra
Noise Precision Pressure

Environment
Electrostatic
Air Flow
Shielding

Electromagn
etic Shielding

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Clean Room TRANSPORT

Robotic transport in fully automatic Fabs using Automatic Guided Vehicles (AGVs)

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Clean Room CLASSES

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Definitions and Terminologies (Continue)

14. Ingot: A large cylindrical bar of single crystalline pure silicon from which wavers are
produced.

15. Wafer: A large circular sheet of single crystalline silicon (the diameter  = 8”, 10” or
12”, thickness = 0.5 – 1 mm, resistively 3-5 Ω, p-type or n-type, mirror-like polished surface).
Many identical chips are to be fabricated on a single wafer typically 500 Die/wafer).

16. Die: It is the fabricated design or circuit on the wafer.

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Single Crystal Silicon Ingot

An Ingot

Wafer slicing

>3m

Weight > 60 kg

8” (200mm) to 12”(300mm)

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Silicon Wafer/Die

Single die

Wafer

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Definitions and Terminologies (Continue)

17. Chip: It is bonded die after packaging.
18. Pads: A chip consists of a core, or a die surrounded by a pad frame. The circuit designer
usually designs the core (normally works at low supply). A pad is needed for wire bonding to
a package pin (I/O connection and supply). A pad frame includes predesigned standard I/O
buffers and protection circuitry (normally works at high supply).
19. Packaging: The chip (die and wire bonded) is hermetically sealed inside a package.
Package material is either plastic or ceramic. Different type of packages exist: DIP, LCC,
PGA, BGA, …
20. Die Bonding: Fixing a chip inside a package cavity and Apply a glue on the cavity surface
to fix the chip backside down.

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17. Chip 18. Pads :

• A chip consists of a core surrounded by a pad frame.

• A pad is needed for wire bonding to a package pin (I/O connections and supply).
• A pad frame includes pre-designed standard I/O buffers and protection circuitry

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19. Packaging:

Packaging Requirements
 Electrical: Low parasitics
 Mechanical: Reliable and robust
 Thermal: Efficient heat removal
 Economical: Cheap

Package Parameters

Package Types

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20. Die Bonding

A special sewing
machine is used for wire
bonding using thermo-
compression

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System Design
• In this process the user Specs is interpreted to Prototype design circuit, which is the main
brain work.
• Requirements: Computer Workstations - EDA Tools - Highly Qualified Personnel.

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System Design : Design Steps

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Fabrication

Foundry

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Fundamental Design Metrics

(a) Functionality
(b) Cost
(c) Reliability and robustness
(d) Performance
 Noise immunity
 Speed (delay)
 Power consumption; energy
(e) Scalability
(f) Time-to-market

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Production Cycle
1. Market study
2. Idea
3. Feasibility study
4. Design
5. Prototype
6. Fabrication
7. Packaging
8. Testing and evaluation Design
9. Mass production

Fabrication

Packaging
Final Product

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VLSI Applications

Military Application Civilian Applications

Radars System Medical

Rockets Computers
Navigation System Satellites
Others. Appliance
Mobile Communication

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Evolution in DRAM Chip Capacity

human memory
human DNA

4X growth every 3 years! 0.07 m

100000000
m
0.164,000,000
16,000,000
10000000
0.13 m
4,000,000
book 0.18-0.25 m
Kbit capacity/chip

1000000 1,000,000

0.35-0.4 m
256,000
100000
64,000
0.5-0.6 m
16,000
10000 encyclopedia
4,000 0.7-0.8 m
2 hrs CD audio
1000 1,000
1.0-1.2 m 30 sec HDTV
256
1.6-2.4 m
100
64

10
page
1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010

Year

30

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What is this course all about?

 Introduction to digital integrated circuits.
CMOS devices and manufacturing technology. CMOS inverters and gates.
Propagation delay, noise margins, and power dissipation. Sequential circuits.
Arithmetic, interconnect, and memories. Programmable logic arrays. Design
methodologies.
 What will you learn?
Understanding, designing, and optimizing digital circuits with respect to
different quality metrics: cost, speed, power dissipation, and reliability

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Digital Integrated Circuits

 Introduction: Issues in digital design
 The CMOS inverter
 Combinational logic structures
 Sequential logic gates
 Design methodologies
 Interconnect: R, L and C
 Timing
 Arithmetic building blocks
 Memories and array structures

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Digital Integrated Circuits

A Design Perspective

Introduction

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The First Computer

The Babbage
Difference Engine (1832)

25,000 parts
Cost: ₤17,470

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ENIAC - The first electronic computer (1946)

ENIAC, U.S. Army, 1946 Smart phone, 2021

Size  Large hall (> 150m2) Size  Your pocket
Power Consumption ≈ 150kW Power consumption < 1W

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The Transistor Revolution

First transistor
Bell Labs, 1948

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The First Integrated Circuits

Bipolar logic
1960’s

ECL 3-input Gate

Motorola 1966

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Intel 4004 Micro-Processor

1971
1000 transistors
1 MHz operation

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Intel microprocessor

Core i5

Pentium IV

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Moore’s Law
 In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to
24 months.
 He made a prediction that semiconductor technology will double its effectiveness every 18
months

Electronics, April 19, 1965.

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Evolution in Complexity

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Transistor Counts

1 Billion
K Transistors
1,000,000

100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Courtesy, Intel Projected

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Moore’s law in Microprocessors

1000

Transistors (MT) 100 2X growth in 1.96 years!

10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
Transistors
0.01 on Lead Microprocessors double every 2 years
8080
8008
4004
0.001
1970 1980 1990 2000 2010
Courtesy, Intel Year

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Die Size Growth

100
Die size (mm)

P6
10 486 Pentium ® proc
386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Courtesy, Intel Year

Die size grows by 14% to satisfy Moore’s Law

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Frequency

10000
Doubles every
1000
2 years
Frequency (Mhz)
100 P6
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Courtesy, Intel Year
Lead Microprocessors frequency doubles every 2 years

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Power Dissipation

100
P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Courtesy, Intel Year

Lead Microprocessors power continues to increase

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Power will be a major problem

100000
18KW
10000 5KW
1.5KW
Power (Watts) 500W
1000
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004

0.1
1971 1974 1978 1985 1992 2000 2004 2008
Courtesy, Intel Year

Power delivery and dissipation will be prohibitive

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Power density

10000
Rocket
Power Density (W/cm2)

Nozzle
1000
Nuclear
100
Reactor

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
8080 286 486
1
1970 1980 1990 2000 2010
Courtesy, Intel Year

Power density too high to keep junctions at low temp

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Challenges in Digital Design

 DSM  1/DSM
“Microscopic Problems” “Macroscopic Issues”
• Ultra-high speed design • Time-to-Market
• Interconnect • Millions of Gates
• Noise, Crosstalk • High-Level Abstractions
• Reliability, Manufacturability • Reuse & IP: Portability
• Power Dissipation • Predictability
• Clock distribution. • etc.
Everything Looks a Little Different

? …and There’s a Lot of Them!

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Productivity Trends
Logic Transistor per Chip (M)

10,000
10,000,000 100,000
100,000,000
1,000 Logic Tr./Chip 10,000
1,000,000 10,000,000
Tr./Staff Month.
(K) Trans./Staff - Mo.

100
100,000 1,000
1,000,000
Complexity

Productivity

10 58%/Yr. compounded 100

10,000 Complexity growth rate 100,000

1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x
21%/Yr. compound
xx Productivity growth rate
x
0.01
10 0.1
100

0.001
1 0.01
10
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009

Courtesy, ITRS Roadmap Source: Sematech

Complexity outpaces design productivity

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Why Scaling?
 Technology shrinks by 0.7/generation
 With every generation can integrate 2x more functions per chip; chip cost does
not increase significantly
 Cost of a function decreases by 2x
 But …
 How to design chips with more and more functions?
 Design engineering population does not double every two years…
 Hence, a need for more efficient design methods
 Exploit different levels of abstraction

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Design Abstraction Levels

SYSTEM

MODULE

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

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