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PRAM Models

The document summarizes the Parallel Random Access Machine (PRAM) model of parallel computation. A PRAM consists of multiple processors that can access a shared memory simultaneously. Depending on how simultaneous memory accesses are handled, PRAMs are divided into four models: exclusive-read exclusive-write (EREW), concurrent-read exclusive-write (CREW), exclusive-read concurrent-write (ERCW), and concurrent-read concurrent-write (CRCW). Algorithms like parallel prefix sums, tree traversal, and sorting can be analyzed in terms of their time and processor complexities in the PRAM model.

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246 views6 pages

PRAM Models

The document summarizes the Parallel Random Access Machine (PRAM) model of parallel computation. A PRAM consists of multiple processors that can access a shared memory simultaneously. Depending on how simultaneous memory accesses are handled, PRAMs are divided into four models: exclusive-read exclusive-write (EREW), concurrent-read exclusive-write (CREW), exclusive-read concurrent-write (ERCW), and concurrent-read concurrent-write (CRCW). Algorithms like parallel prefix sums, tree traversal, and sorting can be analyzed in terms of their time and processor complexities in the PRAM model.

Uploaded by

jazz
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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PRAM Models

Architecture of an Ideal Parallel Computer

A natural extension of the Random Access Machine (RAM) serial architecture is the
Parallel Random Access Machine, or PRAM.

PRAMs consist of p processors and a global memory of unbounded size that is


uniformly accessible to all processors.

Processors share a common clock but may execute different instructions in each
cycle.

The power of a PRAM depends on the kind of access to the shared memory locations.
PRAM Submodels and Assumptions
Processors
0

Shared Memory
0
1
2
3

1
.
.
.
p1

.
.
.
m1

Fig. Conceptual view of a parallel random-access machine (PRAM).

Processor i can do the following in three phases of one cycle:

1.
2.

Fetch a value from address si in shared memory

Perform computations on data held in local registers

3. Store a value into address di in shared memory

We say model A is less powerful compared to model B if either:


The time complexity for solving a problem is asymptotically less in model B as compared to
model A.
OR
If the time complexities are the same, the processor or work complexity is asymptotically
less in model B as compared to model A.

PRAM Instruction Set

Accumulator architecture
o memory cell R accumulates results
0

Multiply/divide instructions take only constant operands


o prevents generating exponentially large numbers in polynomial time

Reads from same location


Exclusive

C o n c u rre n t E xc lu s ive

W rites to sa m e lo c a tio n

Types of PRAM

EREW
Least powe rful,
most realistic

ERCW
Not useful

Concurrent

CREW
Default

CRCW
Most powerful,
further subdivided

Architecture of an Ideal Parallel Computer

Depending on how simultaneous memory accesses are handled, PRAMs can be


divided into four subclasses:

o Exclusive-read, exclusive-write (EREW) PRAM.


o Concurrent-read, exclusive-write (CREW) PRAM.
o Exclusive-read, concurrent-write (ERCW) PRAM.
o Concurrent-read, concurrent-write (CRCW) PRAM.

What exactly concurrent write means?


o Common: write only if all values are identical.
o Arbitrary: write the data from a randomly selected processor.
o Priority: follow a predetermined priority order.
o Sum: Write the sum of all data items.
PRAM Algorithms Can be categorised such as:

o Parallel Reduction
Broadcast Algo
Divide and Conquer

o Prefix Sum
o Parallel List Ranking

o Pre Order Tree Traversal


o Parallel Merge Cost Optimal Algorithm
Broadcasting on a PRAM

o Broadcast can be done on CREW PRAM in O(1) steps:


Broadcaster sends value to shared memory
Processors read from shared memory
for each individual processor
time:
time: number of instructions executed
space:
space: number of memory cells accessed

PRAM machine
time:
time: time taken by the longest running processor
hardware:
hardware: maximum number of active processors
Thanks

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