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Analog Integrated Circuits Design by Ken Martin & Johns PDF

This document summarizes the contents of three chapters from an integrated circuit textbook. Chapter 1 discusses semiconductor materials and pn junctions, MOS and bipolar transistors, and device modeling. Chapter 2 covers CMOS and bipolar processing techniques as well as layout considerations. Chapter 3 introduces several basic current mirrors and single-stage amplifiers used in analog integrated circuits.

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Praveen Kumar
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1K views712 pages

Analog Integrated Circuits Design by Ken Martin & Johns PDF

This document summarizes the contents of three chapters from an integrated circuit textbook. Chapter 1 discusses semiconductor materials and pn junctions, MOS and bipolar transistors, and device modeling. Chapter 2 covers CMOS and bipolar processing techniques as well as layout considerations. Chapter 3 introduces several basic current mirrors and single-stage amplifiers used in analog integrated circuits.

Uploaded by

Praveen Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CHAPTER 1

INTEGRATED-CIRCUIT DEVICES AND MODELLING


Semiconductors and pn Junctions
1
16
MOS Transistors
Advanced MOS Modelling
39
Bipolar-Junction Transistors
42
Device Model Summary
56
SPICE-Modelling Parameters
61
Appendix
65
78
References
Problems
78

CHAPTER 2

PROCESSING AND LAYOUT


2.1
2.2
2.3
4 2.4
2.5
2.6
2.7

CHAPTER 3

CMOS Processing
82
Bipolar Processing
95
CMOS Layout and Design Rules
Analog Layout Considerations
Latch-Up
118
References
121
Problems
121

96
105

BASIC CURRENT MIRRORS AND SINGLE-STAGE AMPLIFIERS


Simple CMOS Current Mirror
125
Common-SourceAmplifier
128
Source-Follower or Common-Drain Amplifier
129
Common-Gate Amplifier
132
Source-Degenerated Current Mirrors
135
High-Output-Impedance Current Mirrors
137
Cascode Gain Stage
140
MOS Differential Pair and Gain Stage
142
Bipolar Current Mirrors
146
Bipolar Gain Stages
149

125

Chapter 1

IntegratedCircuit Devices and Modelling

Since the diode area is 100 x lo-'' m2, the total zero-bias depletion capacitance is

At a 3-V reverse-bias voltage, we have from (1.19)

As expected, we see a decrease in junction capacitance as the width of the depletion region is increased.

Graded Junctions
All of the above equations assumed an abrupt junction where the doping concentration changes quickly from p to n over a small distance. Although this is a good
approximation for many integrated circuits, it is not always true. For example, the
collector-to-base junction of a bipolar transistor is most commonly realized as a
graded junction. In the case of graded junctions, the exponent 112 in Eq. (1.15) is
inaccurate, and a better value to use is an exponent closer to unity, perhaps 0.6 to 0.7.
Thus, for graded junctions, (1.15) is typically written as

where rn is a constant typically around 113.


Differentiating (1.25) to find the depletion capacitance. we have

This depletion capacitance can also be written as

where

From (1.27), we see that a graded junction results in a depletion capacitance that
is less dependent on V, than the equivalent capacitance in an abrupt junction. In other
words, since rn is less than 0.5, the depletion capacitance for a graded junction is

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