Scribd
Upload
92 views37 pages

7-Bjt Amp Graph Design

This document provides an overview of designing a common emitter BJT amplifier. It begins by defining the key design specifications including voltage gain, output swing, input/output resistance, and power supply. It then explains how to set the DC biasing conditions to meet the specifications by transforming them into functions of collector current and load resistance. Graphical techniques are presented to find the acceptable design region that satisfies all constraints. Key design equations are derived for negative output swing, input resistance, gain, and harmonic distortion specifications. The process is demonstrated through an example amplifier design.

Uploaded by

Joe King
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
92 views37 pages

7-Bjt Amp Graph Design

This document provides an overview of designing a common emitter BJT amplifier. It begins by defining the key design specifications including voltage gain, output swing, input/output resistance, and power supply. It then explains how to set the DC biasing conditions to meet the specifications by transforming them into functions of collector current and load resistance. Graphical techniques are presented to find the acceptable design region that satisfies all constraints. Key design equations are derived for negative output swing, input resistance, gain, and harmonic distortion specifications. The process is demonstrated through an example amplifier design.

Uploaded by

Joe King
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 37

ECEN325: Electronics

Spring 2015
A Graphical Approach to BJT Amplifier Design

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University

Common Emitter Amp w/ Emitter Resistor

g m RC RL
Av
g m RE1
1

Rin RB r 1RE1
Rout RC

Typical Design Specifications


Loaded voltage gain, Av
Max output swing, vomax
This must be satisfied at a given linearity
(total harmonic distortion)

Input and output resistance, Rin & Rout


Power Supply, VCC

How to set DC Biasing Conditions?


In order to meet all design specifications,
the DC biasing conditions (IC, RC) must
be set appropriately
Can transform design specifications into
functions of IC & RC and graph them to
find acceptable solution space

Rin, VCC, & Neg. vomax Specifications


Rin Spec
Rin RB r 1RE1 RE1
RE1

Rin

Input resistance is primarily set by RE1

Rin, VCC, & Neg. vomax Specifications


Need a minimum VCE to keep transistor in
active mode with maximum negative swing
Set VCE min 500mV
(w/ 200mV design margin)
VCC Spec (w/ max negative swing)
VCC

IC

RE1 VCE min vo max I C RC

VCE min VCC I C RC vo max

IC

RE1 500mV

Rin, VCC, & Neg. vomax Specifications


Can solve for IC
VCC vo max 0.5V
IC
RE1
RC

Combining Rin spec

RE1

Rin

VCC vo max 0.5V


IC
Rin
RC

Minimum negative AC Swing constraint sets


an upper bound on IC

Pos. vomax Specification


Need to insure with a positive swing that the
output signal doesnt clip the power supply
VCC I C RC vo max VCC

vo max
IC
RC

Positive AC Swing constraint sets a lower


bound on IC
Additional linearity constraint (harmonic
distortion) generally sets a tighter bound
8

Gain Specification

IC

RC RL
vo g m RC RL Vth

Av
g m RE1
vi
I C RE1
1
1

Vth

IC

Av Vth
RC RL

Av RE1

Av Vth
RC RL

Av Rin

Gain constraint sets a lower bound on IC


9

Harmonic Distortion Specification


Need a minimum amount of bias current to insure that the
AC swing doesnt distort

Model a as a system which distorts


2
3
ic avbe a1vbe a2 vbe
a3vbe
...

where a1 g m , a2

1 I CQ
, ...
2 Vth2

Here vbe vb ve vb fic


where

f RE
10

Harmonic Distortion Specification

We want to express ic as a function of vb because that is our input


ic bvb b1vb b2 vb2 b3vb3 ....
Can show that *
I CQ
gm
1
, b2
, ...
b1
1 g m RE
2 Vth2 1 g m RE 3

For single-ended amplifiers with low-distortion, HD2 will


dominate the distortion terms
The second - order harmonic distortion is
1 b2
1
1

HD 2
i

c max
2 b12
4 1 g m RE

ic max

I
CQ

11

Harmonic Distortion Specification


To satisfy a given HD2 specification
ic max 4 HD 21 g m RE I CQ
vo max
RC
IC

4 HD 21 g m RE

IC

1
2

1
2

RE

Vth vo max
RC RE HD 2

Using RE

IC

vo max
RC
I
4 HD 2 C
Vth

Rin

Vth vo max
RC Rin HD 2

HD2 will dominate, but is not the only distortion term


For a -30dB THD, perhaps set HD2 to -40dB or (0.01)
12

Output Resistance Specification


Neglecting transistor
output resistance, Rout is
determined by RC

RC Rout , spec

13

Key CE Amp Design Equation Summary


VCC vo max 0.5V
Neg. Swing, Rin, VCC : I C
R
RC in

vo max
Pos. Swing : I C
RC
Gain : I C

Av Vth
RC RL

1
Harmonic Distortion : I C
2

Av Rin

Vth vo max
RC Rin HD 2

Output Resistance : RC Rout , spec


14

Design Example - Specifications


|Av| |-8|
Rin 200k
Rout 30k
Vomax = 20mVpk w/ THD -30dB
VCC = 5V

15

Design Equation Plots

Plots done with =110


due to low current level
necessary for high Rin

Pick a design point in the middle for margin


IC=78A, RC=24k
16

DC Operating Points

DC bias points must be reasonable for the


circuit to work as designed!
17

AC Gain, Rin, & Rout


|Av| = 19.2dB = 9.12

Rin = 106.6dB = 214k

Rout = 87.7dB = 24.0k


18

Transient & Distortion


Output with swing > vomax

FFT of output signal

19

Adding RE2 to Stabilize DC Biasing


Adding RE2 can help to make the DC biasing less sensitive to the
absolute transistor Beta value
Assume I want IC~80A
While the nominal is 110, assume that it can vary from 70-200
What is the difference in designs with RE2=0 and with 1V across RE2?
~70
~110
~200

Beta
70
110
200

Ic (No RE2)
53A
78A
116A

% Diff. from =110


-32.1%
N/A
48.7%

IC (w/ 1V RE2)
69A
79A
88A

% Diff. from =110


-12.7%
N/A
11.4%

What is the impact on the graphical design procedure?

20

Rin, VCC, & Neg. vomax Specs w/ RE2


The only equation impacted is the Neg. vomax
Need a minimum VCE to keep transistor in
active mode with maximum negative swing
Set VCE min 500mV
(w/ 200mV design margin)
VCC Spec (w/ max negative swing)
VCC

IC

RE1 RE 2 VCE min vo max I C RC

VCE min VCC I C RC vo max

IC

RE1 I E RE 2 500mV

21

Rin, VCC, & Neg. vomax Specs w/ RE2


Can solve for IC, assuming a VRE2 across RE2

VCC vo max 0.5V VRE 2


IC
RE1
RC

Combining Rin spec

RE1

Rin

VCC vo max 0.5V VRE 2


IC
Rin
RC

Minimum negative AC Swing constraint sets an


upper bound on IC which is reduced with RE2
22

Key CE Amp Design w/ RE2 Eq. Summary


VCC vo max 0.5V VRE 2
Neg. Swing, Rin, VCC : I C
Rin
RC

vo max
Pos. Swing : I C
RC

Only Eq. which changed

Av Vth
Gain : I C
Av Rin
RC RL

1 Vth vo max
Harmonic Distortion : I C
2 RC Rin HD 2
Output Resistance : RC Rout ,spec
23

Common Collector Amp


Av

RE RL
re RE RL

Rin RB r 1RE RL
Rout

RS RB
RE re

24

Typical Design Specifications


Loaded voltage gain, Av
Max output swing, vomax
This must be satisfied at a given linearity
(total harmonic distortion)

Input and output resistance, Rin & Rout


If you know RL, then Rout spec is somewhat
redundant with Av spec

Power Supply, VCC


25

How to set DC Biasing Conditions?


In order to meet all design specifications,
the DC biasing conditions (IE, RE) must be
set appropriately
Can transform design specifications into
functions of IE & RE and graph them to
find acceptable solution space

26

Rin Specification
Rin Spec
Rin RB r 1RE RL RE RL

1
RE

R

R
L
in , spec

Input resistance is primarily set by RE


and somewhat independent of IE
27

Neg. vomax Specification


Need to insure with a negative swing that the
output signal doesnt clip the power supply
I E RE vo max 0V

vo max
IE
RE

Negative AC Swing constraint sets a lower


bound on IE
Additional linearity constraint (harmonic
distortion) generally sets a tighter bound
28

Pos. vomax & VCC Specifications


Need a minimum VCE to keep transistor in
active mode with maximum positive swing

Set VCE min 500mV


(w/ 200mV design margin)
VCC Spec (w/ max positive swing)

Maximum positive AC
swing constraint sets an
upper bound on IE

VCC I E RE vo max VCE min


VCE min VCC I E RE vo max 500mV

VCC vo max 0.5V


IE
RE

29

Gain Specification

Av

RE RL
re RE RL

RE RL
Vth
RE RL
IE

AvVth
IE
RE RL 1 Av

Gain constraint sets a lower bound on IE


30

Harmonic Distortion Specification


Following a similar procedure as the Common-Emitter Amp, can relate
the HD2 specification to the ratio of AC current ic to ICQ
ic 4HD2 1 g m RE RL I CQ
Now, assuming a high or 1
ie 4HD 21 g m RE RL I EQ

I EQ

vo max
RE RL

vo max
RE RL

4HD21 g m RE RL
I EQ
RE RL
4HD2
Vth

I EQ

2RE RL

Vth vo max
HD 2

HD2 will dominate the distortion terms


For a -30dB THD, perhaps set HD2 to -40dB or (0.01)
31

Key CC Amp Design Equation Summary


Rin : RE

Rin, spec RL

vo max
Neg. vomax : I E
RE

VCC vo max 0.5V


Pos vomax, Vcc : I E
RE
AvVth
Gain : I E
RE RL 1 Av
Harmonic Distortion : I E

2RE RL

Vth vo max
HD 2

32

Design Example - Specifications


Av 0.95
Rin 1k
Vomax = 500mVpk w/ THD -30dB
Here I set HD2=40dB or 0.01

VCC = 5V
RL = 50

33

Design Equation Plots

Plots done with =170


due to high current level

Pick a low IE design point to save power


IE=20mA, RE=100

34

DC Operating Points

DC bias points must be reasonable for the


circuit to work as designed!
35

AC Gain & Rin


|Av| = -0.38dB = 0.96

Rin = 67.6dB = 2.4k

36

Transient & Distortion


Output with swing > vomax

37

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy