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Computer Organization 2016-2017

Unit 1
Processor datapath design
Introduction
Building the datapath
o Searching new instructions in memory
o Type R Instructions
o Load and Store Instructions
o A first scheme of a processor
Multiplexors
Control
o Conditions Branch Instructions
o The complete datapath
The datapath control
o The ALU control
o Designing the Main Control Unit
o The datapath with the control signals
Conclusions
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Introduction
The performance of a processor depends on several factors:
Execution Time = NI x CPI x Cycle
o Number of instructions: determined by the ISA and the compiler
o CPI and Cycle: determined by CPU hardware
We will study two implementations of the MIPS processor:
o A simplified version (a review of the design studied in the previous course)
o A more realistic pipelined version
A simple MIPS subset instructions will be used
o Memory accesses: lw, sw
o Arithmetic/logic Operations: add, sub, and, or, slt
o Control transferences (branches): beq, j
We will show that ISA determines a lot of the aspects of the implementation and
how the election among several implementation strategies affects the size of the
Unit 1: 2
clock cycle and the CPI of the computer.

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The MIPS ISA only has three instructions formats, all of them of 32 bits:
o Instructions with immediate (type I)
load and stores
all the operations with immediate
conditional branch instructions: bne, beq
o Instructions between registers (type R)
ALU operations register-register
func codifies the datapath operation
special read/write registers and transfers
o Unconditional Branch instructions (type J)
Branch
Branch and return
Trap and return after the exception

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Building the datapath

A lot of things necessary to execute an instruction do not depend on the
instruction type:
o To send the PC to the instruction memory and to load the next instruction.
o To read one or two registers using the fields in the instruction.
After that, the actions to be made depend on the instruction type:
o The ALU is used to compute
Arithmetic results
The addresses to memory accesses for load/store instructions
The target address in a branch
o The data memory is accessed for load/store instructions
o PC must be modified to PC target address or PC + 4
The simplicity and regularity of MIPS ISA simplify the implementation.
The processor datapath is formed by the elements that process data and
addresses:
o Registers, ALUs, multiplexers, memories,
We are going to build the processor datapath in an incremental way using
successive refinements of an original scheme.
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Searching new instructions from memory

We first need: PC, Instruction Memory and an Adder.

Register of
32 bits

Increases the
address by 4
for the next
instruction

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Type R instructions

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add $t1, $t2, $t3

Read two source registers.

Compute the specific arithmetic/logic operation.
Write the result register.

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Load or Store Instructions

Read the source registers.
Compute the memory access address using de 16bit offset:
o The ALU is used, and so the 16-bit offset must
be extended to form a 32-bit number.

lw $t1, 16($t2)

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A first processor scheme

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Multiplexors
We cannot join directly wires
o Multiplexors are used

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Control

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Activity (10 minutes)

In the previous figure, study how the following instructions would be executed:
o add $t1, $t2, $t3
o lw $t1, 16($t2)
o bne $t1, $t2, target

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Conditional Branch Instructions

bne, beq: Read the source registers
Compare the operands:
o The sub operation in the ALU is
used.
o The Zero output is checked.

bne $t1, $t2, offset

In order to compute the target address:

o The offset is relative to the next instruction after the branch
It is already computed when the instruction search was made
o The sign bit should be extended to convert the offset in a 32-bit number.
o Besides, the obtained number is shifted two positions to the left (word level alignment).

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Conditional Branch Instructions

Only
reorder
the bits

The sign bit

is replicated
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The complete datapath

Now the different things previously studied are combined together.
In this datapath each instruction will be executed in only one clock cycle
o Every datapath element is doing only a thing concurrently.
o So, different memories are needed for instructions and data.
Some things of the datapath can be shared by different instructions types:
o Multiplexors will be used when a datapath element could have different
sources depending on the instruction type.
I0
I1

M
u
x

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The complete datapath

The datapath for the type-R and Load/Store instructions

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The complete datapath

The hardware for the branch is included and the full datapath is obtained.

0
1

Unit 1: 16

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Activity (10 minutes)

In the previous figure, study which values the control signal should have to
execute the following instructions:
o add $t1, $t2, $t3
o lw $t1, 16($t2)
o bne $t1, $t2, target

Instrucciones

PCSrc

MemRead

MemtoReg

MemWrite

ALUSrc

RegWrite

add $t1, $t2, $t3

lw $t1, 16($t2)
bne $t1, $t2, target

Unit 1: 17

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ALU Control
The ALU is used for
o Load/Store: the operation to be performed is add
o Branch: the operation to be performed is subtract
o R-type: the operation to be performed depends on the funct field:
AND, OR, subtract, add, or set less than.

ALU control

Function

0000

AND

0001

OR

0010

add

0110

subtract

0111

set-on-less-than

1100

NOR

Only for
shifts

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ALU Control
We can generate 4 bits to control the ALU using a simple control unit with input
the funct field of the ALU instruction and 2 bits of configuration (ALUOp)
generated by the main control unit.
Assuming 2 bits ALUOp generated based on the instruction opcode:
o ALUOp = 00 an add operation must be performed for a load or a store.
o ALUOp = 01 a subtract operation must be performed for a conditional branch.
o ALUOp = 10 the specific operation to be performed is codified in the funct field.

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ALU Control
Using two control levels the size and complexity of the main control unit can be
reduced.
The ALU control unit is simple because a lot of combinations arent interesting.

Operation3 is always 0 for this instruction set of MIPS:

o Its only used for the NOR operation.

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ALU Control
The truth table for the bit Operation2=1 is:

The truth table for the bit Operation1=1 is:

The truth table for the bit Operation0=1 is:

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ALU Control
The control block which generates the 4 bits that govern the ALU has as
inputs:
o The 2 bits ALUOp
o The 6 bits of the funct field of the type-R operations.

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The main control unit

The control signals are based directly on the specific instruction type:
R-type

Load/
Store

Branch

rs

rt

rd

shamt

funct

31:26

25:21

20:16

15:11

10:6

5:0

35 or 43

rs

rt

address

31:26

25:21

20:16

15:0

rs

rt

address

31:26

25:21

20:16

15:0

Opcode

They
are
always
read

They are
always
read
except
for a load

Where to
write for a
type-R
instruction
and a load

Only
for
shifts

Its sign will be

extended, the
result will be
shifted and
finally the PC
will be added
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The datapath with the control signals

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Autonomous Activity
Review the execution process for each type of instruction in the previous datapath:
o Type-R instructions
o Load instruction
o Store instruction
o Conditional Branch instruction

Instructions

RegDst Branch MemRead MemtoReg

ALUOp

MemWrite

ALUSrc

RegWrite

Type-R
Load
Store
Conditional Branch

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The main control unit

The control signals are generated based on the six bits of the instruction
operation code :

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The main control unit

A possible implementation could be:

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Autonomous activity
Unconditional branches cannot be executed in the previous datapath.
Modify the implementation to be able to execute unconditional branches (Exercice 13).

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The datapath with the control signals

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Conclusions
We have reviewed the main elements that compose a processor datapath.
These elements have been interconnected to form the datapath.
We have also studied which control signals must be included and how to
obtain them.
For each instruction type, we have thoroughly studied how the designed
datapath works.

Sections 4.3 and 4.4 from the book

(pages 251 271)

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