Scribd
Upload
30 views15 pages

Exam Type D:: Monday PM Wednesday AM Wednesday PM

The document is a midterm examination for a digital systems course. It provides instructions for the exam, including the date and time, examiners, permitted aids, calculator policy, and submission instructions. It contains 10 questions worth a total of 70 marks. The questions cover topics such as logic gates, ModelSim simulation, DeMorgan's theorem, and Verilog modules for registers.

Uploaded by

lofawok
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
30 views15 pages

Exam Type D:: Monday PM Wednesday AM Wednesday PM

The document is a midterm examination for a digital systems course. It provides instructions for the exam, including the date and time, examiners, permitted aids, calculator policy, and submission instructions. It contains 10 questions worth a total of 70 marks. The questions cover topics such as logic gates, ModelSim simulation, DeMorgan's theorem, and Verilog modules for registers.

Uploaded by

lofawok
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 15

UNIVERSITY OF TORONTO

FACULTY OF APPLIED SCIENCE AND ENGINEERING


ECE241F Digital Systems
Midterm Examination
October 22, 2015
6:10 p.m. 7:55 p.m.
(105 minutes)
Examiners: J. Anderson, P. Chow, B. Wang,
Exam Type D: Examiner specified aids: One single sheet of letter size paper (8.5 x 11 inch), both
sides may be used.
Calculator Type 4: No calculators or other electronic devices are allowed.
All questions are to be answered on the examination paper. There are two extra pages at the
end and you may use the back of a page. If you use more than the given space, please direct
the marker to the appropriate page and indicate clearly on that page which question(s) you are
answering there. It is your responsibility to make sure the marker can find your solution.
The number of marks for each question are indicated.
The examination has 15 pages, including this one.
Circle your lab room (one mark deduction if you do not correctly indicate your room). This is to
facilitate the return of your test:
Monday PM

BA3135

BA3145

BA3155

Wednesday AM

BA3135

BA3145

BA3155

Wednesday PM

BA3135

BA3145

BA3155

Full Name:
Student Number:

UTORID:
MARKS

10

Total

/5

/6

/8

/7

/10

/6

/4

/8

/6

/10

/70

Question 1 [5 Marks]
(a) If you were only allowed to use one type of simple logic gate to build a large digital circuit,
which gate would you pick? Why?
Solution:
NAND or NOR gates are called universal gates and can implement
any logic function.
(b) Write the ModelSim commands to generate the following waveform:

1
Xin

0
20ns

10ns

15ns

Solution:
force Xin 0
run 10ns
force Xin 1
run 20ns
force Xin 0
run 15ns
(c) The signal OutputF is to be displayed on an LED connected to port pLED. The intended
behaviour is for the LED to turn on when OutputF is logic-1. You use the following assignment statement:
assign pLED = OutputF;
and find that the LED is off when OutputF = 1 and the LED is on when OutputF = 0. Write
the assignment statement to fix this.
Solution:
assign pLED = OutputF;

Question 1 continued . . .
(d) State both forms of DeMorgans Theorem (as Boolean equations).
Solution:
a+b=ab
or
ab=a +b
(e) What valuable information can be learned from simulation with ModelSim (vs. directly loading the design into the FPGA and testing the hardware)?
Solution:

In simulation, you can view ANY logic signal in the simulation (not
solely primary inputs + primary outputs). Or, some other response
about what can be observed in simulation that cannot be seen in the
actual hardware.

Question 10 [10 Marks]


(a) [7 Marks] Write a Verilog module for a 4-bit register that has a synchronous active-low reset
input called Resetb, i.e., reset the register when Resetb = 0. The schematic symbol for the
register is shown below:

D3 D2 D1 D0
Resetb

4-Bit Register

Clock
Q3 Q2 Q1 Q0

Solution:
module reg4bit (D, Clock, Resetb, Q);
input [3:0] D;
input Clock, Resetb;
output reg [3:0] Q;
always @(posedge Clock)
if (!Resetb)
Q <= 0;
else
Q <= D;
endmodule

12

Question 10 continued . . .
(b) [3 Marks] Starting with the register described above, write a Verilog module that adds an
Enable signal to the register. The register will only load a new value when Enable = 1. The
schematic symbol is shown below. If convenient, you may number your lines in Part (a) and
for this part, indicate which lines change and how they are changed.

Enable
Resetb

D3 D2 D1 D0

4-Bit Register

Clock
Q3 Q2 Q1 Q0

Solution:
module reg4bit (D, Clock, Resetb, Enable, Q);
input [3:0] D;
input Clock, Resetb, Enable;
output reg [3:0] Q;
always @(posedge Clock)
if (!Resetb)
Q <= 0;
else if (Enable)
Q <= D;
endmodule

13

This page has been left blank intentionally. You may use it for answers to any questions.

14

This page has been left blank intentionally. You may use it for answers to any questions.

15

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy