16-Elec-A4, December 2018 Page 1 of 6 National Exams December 2018 16-Elec-A4, Digital Systems & Computers 3 hours duration NOTES: 1. If doubt exists as to the interpretation of any question, the candidate is urged to submit with the answer paper, a clear statement of any assumptions made. 2. This is a Closed Book exam Candidates may use one of two calculators, the Casio or Sharp approved models. 3. FIVE (5) questions constitute a complete exam Clearly indicate your choice of any five of the six questions given otherwise the first five answers found will be considered your pick. 4. All questions are worth 12 points. See below for a detailed breakdown of the marking. Marking Scheme 1. (@) 2, (6) 2, (©) 2, A) 3, (€) 3, total = 12 (a) 6, (b) 3, (©) 3, total = 12 (a) 6, (b) 6, total = 12 (a) 4, (b) 4, (©) 4, total = 12 (a) 4, (b) 4, (©) 4, total = 12 (a) 4, (b) 4, (c) 4, total = 12 ‘The number beside each part above indicates the points that part is worth Aww16-Elec-A4, December 2018 Page 2 of 6 = (a) Using only one NAND gate build a NOT gate. (b) Using only NAND gates build a two-input OR gate. Draw circuits for the function g given by g = (G@¥B)-C+BCD)-E-(A+B) (©) as written above using AND, OR & NOT gates (assume 2 & 3-input gates are available). (d) using NAND gates only (assume literal complements as well as 2 and 3-input gates are available). (©) using NOR gates only (assume literal complements as well as 2 and 3-input gates are available). Note: Do not use Boolean algebra or K-map to simplify function g in parts (c)-(e) above. 2. A 3-bit counter advances through the sequence 000, 010, 100, 101, 011, 001 back to 000, and repeats. (a) Using the standard design process for synchronous counters, show how to implement this counter using JK flip-flops. Include: — state transition diagram, — state tcansition table including flip-flop inputs, and — adrawing of the final circuit implementing the counter. (b) Check whether the counter is self-starting or not. (©) Sketch the timing diagram for the counter showing its dynamic behavior for 8 clock pulses, include: ~The clock waveform CLK, containing at least six clock pulses after r= 0, and ~The output waveforms Qa, Qs & Qe, where Qa is the output of flip-flop A (MSB'), Qs is the output of flip-flop B and Qc is the output of flip-flop C (LSB). Assume the CLR input of all flip-flops is temporarily held LOW during the clock cycles preceding time 1 = 0, then it goes HIGH. ! MSB: most significant bit, LSB: least significant bit16-Elec-A4, December 2018 3. The following is a truth table of a 3-input, 4-output combinational circuit. (a) Using K-maps obtain the simplified expressions for A, B, C and D. (b) Implement using a PAL or PLA architecture. Justify your choice. Inputs Outputs x ¥ Zz A B c D 0 0 0 0 1 L 0 | 0 0 1 L 0 0 0 0 1 0 o 0 1 1 0 1 1 1 1 1 1 1 0 0 1 0 1 1 1 oO 1 0 1 oO 1 1 1 0 0 1 1 0 1 1 iL 1 1 0 1 4- @) Page 3 of 6 Identify by marking with a X which of the following are the 4 essential components of a computer system. — Mouse. _— Processor (CPU) _— Printer Hard drive __Memory __ Busses (address, data, control) — Keyboard __ Display monitor VO ports (b) Identify the main differences between a general purpose microprocessor and a ©) microcontroller. Identify which CPU register(s) is(are) typically associated with cach of the following - the address of the next instruction to be executed : = the next available location at the top of the stack : ~ pointing to an array or list of data values in memory : - containing the information an assembly program uses at decision making points (conditional branch statements):16-Elec-A4, December 2018 Page 4 of 6 5. For microprocessors, such as Motorola's, that use big-endian order for storing multiple-byte variables (a) Fill the memory block below with the result of the instruction: “Store the 16-bit number $7A01 to address $C239" 1-byte locations Low Memory $C238 $C239 $C23A : High Memory (p) Let SP = $DCS1. Fill the memory block below with the result of the instruction: “Push the 16-bit number $7A01 onto the stack” 1-byte locations . Low Memory $DC50 $DC51 +— SP (before PUSH) $DC52 High Memory (©) What is the value of the stack pointer register SP after the PUSH?16-Elec-A4, December 2018 Page 5 of 6 6. The figure below shows a circuit used to display two digits in two common-anode seven- segment LED displays. The LED arrangement for each seven-segment display is shown on the right side. Parallel Port B lines PBr-PBo of a microcontroller are used (o control the two- digit display. PBr is used for digit selection, while PBs-PBo are used to determine which segments are lit. Consider that inverters are open-collector TTL inverters and transistor saturation Vce value is approximately 0.3V. (a) Provide the binary values needed in Port B lines to display the decimal number 40, (b) From the programming point-of-view suggest the sequence of steps that will allow observing the number 40 lit on the display. Explain. (©) Find the value for the resistors Re that will allow limiting the current through each LED to 10mA. When turned on, consider the nominal voltage across a LED is 2V. Veource = 5V16-Elec-A4, December 2018 Page 6 of 6 Excitation Tat Q Qe |R ss kK {tr |p | 0 0 x o oO x 0 0 : 0 1 0 1 1 x 1 1 1 0 1 0 xX 1 1 0 1 1 0 x x 0 0 1 lean Tdey Comments 1 Operations with 0 and 1 2. Operatioris with 0 and 1 3. Idompotent 4, Complementarity 5. Operations with 0 and 1 6. Operations with 0 and 1. 7 Idompotent 8. Complementarity 9. Involution 10. Commutative I, A-B=BeA Commutative 12, A¥(B+C)=(A4B)+CHAFB+C Associative 13, Ae(B-C)=(A-B):C=A-B-C Associative 14. A(B+O)=(A-B)+(A-C) Distributive 15, A+(B-C)=(A+ B)-(A+O) Distributive 16. A+(A-B)=A Absorption 17. A(AtB)=A Absorption 18. (A-B)+(A-C) + (BC) =(A-B)+(A-O) Consensus 19. De Morgan 20. De Morgan 21 Simplification 22. (A:B)+B=A+B Simplification