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Area and Timing Constraints: by Minghua Li Mxl095420@utdallas - Edu

This document discusses area and timing constraints for RTL synthesis. It provides an example calculation to determine an area constraint of 16 square millimeters based on chip manufacturing costs and sales projections. It also describes how to model timing constraints for register-to-register paths, input/output paths, and combinational paths while accounting for clock skew and delay. The document recommends using slow process corners for pre-layout timing analysis and fast corners for post-layout.

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31 views25 pages

Area and Timing Constraints: by Minghua Li Mxl095420@utdallas - Edu

This document discusses area and timing constraints for RTL synthesis. It provides an example calculation to determine an area constraint of 16 square millimeters based on chip manufacturing costs and sales projections. It also describes how to model timing constraints for register-to-register paths, input/output paths, and combinational paths while accounting for clock skew and delay. The document recommends using slow process corners for pre-layout timing analysis and fast corners for post-layout.

Uploaded by

ajayg_lmg
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Area and Timing Constraints

by Minghua Li
mxl095420@utdallas.edu

RTL Synthesis Flow

Area Constraints

Why area constraints matters?

The number of gross die per wafer


(DPW)=pi*d^2/(4*S)
S: the size of each die (mm^2)

TSMC 0.18um (200mm 8inch)


(DPW)=pi*d^2/(4*S) =>
S=3.14*200^2/(4*DPW)=31400/DPW

TSMC 0.18um (200mm 8inch) price is: $1500


(DPW)=pi*d^2/(4*S) =>
S=3.14*200^2/(4*DPW)=31400/DPW
Sell your chips at $1 per chip, Tape-out cost is
$1500 per wafer, Packaging cost $0.1 per package,
Development cost is $15k*10person*3month
You want your profit at $0.3 per chip.
You estimate that you can sell 100k chips.

TSMC 0.18um (200mm 8inch) price is: $1500


(DPW)=pi*d^2/(4*S) => S=3.14*200^2/(4*DPW)=31400/DPW
Sell your chips at $1 per chip, Tape-out cost is $1500 per
wafer, Packaging cost $0.1 per package, Development cost is
$15k*10person*3month
You want your profit at $0.3 per chip.
You estimate that you can sell 100k chips.

Total cost is 10k*$0.7 $700,000


Packaging cost is $100,000
Development cost is $450,000
Tape-out cost $150,000
Number of Wafers $150,000/$1500=100
DPW 100k/100= 1000

TSMC 0.18um (200mm 8inch) (DPW)=pi*d^2/(4*S)


=> S=3.14*200^2/(4*DPW)=31400/DPW
DPW 1000
S 31.4 (mm^2)
Die area w/o pads 20 (mm^2)
Density to physical implementation 80%
The AREA CONSTRAINT for synthesis 16 (mm^2)
Design Compiler:

set_max_area 16000000

Timing Constraints

Reg-to-Reg Path

Treg-to-reg, max = P Setup_Time (assuming 0 clock skew) = 2 0.2 = 1.8ns

Modeling Clock Trees

Design Compiler do not synthesize clock


buffer trees
Clock tree synthesis (CTS) is done by layout
tool, based on the actual cell placement

Modeling Clock Uncertainty


Clock Uncertainty = Clock Skew + Clock jitter
Clock Skew models the maximum delay
different between the clock network
branches. Clock jitter the variation caused by
clock source

Modeling Clock Uncertainty

Constraining Input Paths

T input_logic, max = P Input_Delay Setup_Time (assuming zero clock skew)


Tmax = 2 - 0.6 - 0.2 = 1.2ns

Constraining Output Paths

Toutput_logic, max = P Output_Delay (assuming 0 clock skew)


Tmax = 2 0.8 = 1.2 ns

Constraining Combinational Paths

TF, max= 2 0.4 0.3 = 1.3ns

Pre-layout: fix setup violation, use SS corner


Post-layout: fix hold violation, use FF corner

Timing Report

Timing Report

Timing Report

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