UNIT-1

Introduction to
Physical design flow
Contents: VLSI Design Flow
Physical Design Optimizations
Libraries
ASIC Design Flow
RTL- Gate level synthesis
 Electronic Design Automation
(EDA)
Moore’s Law

Moore: „Cramming more components onto integrated circuits"

In 1965, Gordon Moore (Fairchild)
stated that the number of transistors
on an IC would double every year. 10
years later, he revised his statement,
asserting that they double every 18
months. Since then, this “rule” has
been famously known as Moore’s Law.

Electronics, Vol. 38, No. 8, 1965

4
 Electronic Design Automation
(EDA) Impact of EDA technologies on overall
IC design productivity and IC design
cost

ITRS 2009 Cost Chart

ITRS (in2009
Millions of Chart
Cost Dollars)
(in Millions of Dollars)
120.0
120.0
120.0
100.0
100.0
100.080.0
80.0
55.7
55.7
79.0 46.7
46.7
80.060.0
60.0 79.0 42.5
42.5 46.6
46.6 55.7
56.479.0 33.646.7
33.6 35.2
35.2 40.5
40.5
60.040.0 40.7 56.4 31.142.5
31.1 34.046.6
34.0
40.0 40.7 27.2
27.2 29.440.5
29.6 33.6 35.2 29.4
29.6 56.4 31.1 34.0 21.4
21.4
40.020.0 40.7 44.9 43.5
43.5
20.0 32.9 44.9 39.827.2
39.8 32.6 36.9
36.9 29.4 31.7
29.6 26.3 32.9 29.5
29.5 25.2 32.6 27.0 27.0 23.1 31.7
15.7 20.3
15.7 19.4 26.3
20.3 19.4 25.2 21.416.9
16.9 23.1 43.5
20.0 0.0
0.0 44.9 39.8 36.9
32.9 29.5 32.6 27.0 31.7
15.7 20.3 19.4 26.3 25.2 16.9202123.12022 2023 2024
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018
0.0 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 20242019 2020
2009 2010 HW
Total 2011 2012 2013
Engineering Costs2014 2015
+ EDA
EDA 2016 2017
Tool Costs
Costs Total2018 2019 2020Costs
SW Engineering
Engineering 2021+ ESDA
2022 Tool
2023 2024
Costs
Total HW Engineering Costs + Tool Total SW Costs + ESDA Tool Costs
Total HW Engineering Costs + EDA Tool Costs Total SW Engineering Costs + ESDA Tool Costs
5
Electronic Design Automation (EDA)
Time Period Circuit and Physical Design Process Advancements

1950 -1965 Manual design only.

1965 -1975 Layout editors, e.g., place and route tools, first developed for printed
circuit boards.

1975 -1985 More advanced tools for ICs and PCBs, with more sophisticated
algorithms.

1985 -1990 First performance-driven tools and parallel optimization algorithms for
layout; better understanding of underlying theory (graph theory,
solution complexity, etc.).

1990 -2000 First over-the-cell routing, first 3D and multilayer placement and routing
techniques developed. Automated circuit synthesis and routability-
oriented design become dominant. Start of parallelizing workloads.
Emergence of physical synthesis.

© 2011 Springer Verlag

2000 - now Design for Manufacturability (DFM), optical proximity correction (OPC),
and other techniques emerge at the design-manufacturing interface.
Increased reusability of blocks, including intellectual property (IP)
blocks.

6
Basic Terminology in Physical Design
https://lmr.fi/int/basic-terminology-in-physical-design/#:~:text=Design%3A%20A%20circuit%20that%20performs,ports%20or%20ports
%20to%20pins

• Design: A circuit that performs one or more logical functions.

• Cell: An instance of a design or library primitive within a design.
• Port: The input or output of a design.
• Pin: The input or output of a cell.
• Net: A wire that connects ports to ports or ports to pins.
• Clock: A timing reference object to describe a waveform for timing analysis.
• Logical Libraries: Logical libraries are libraries which provide
• Timing and functionality information for all standard cells (like AND, OR, Flipflops)
• Timing information for Hard Macros (IP, ROM, RAM)
• Define drive/load design rules ( Max Transition, Max Fanout, Max/Min Capacitance
• Physical Libraries: Physical libraries are libraries which contain Physical Information of Standard
cells and Macro cells necessary for placement. Define placement unit tile
• Standard Cell: A standard cell is a group of transistors and interconnect structures that provides a
boolean logic function (e.g., AND, OR, XOR, XNOR, inverters) or a storage function (flipflop or
latch).
• Macro: Macros are intellectual properties that can be directly used in the design. These are need
not to be design. For example memories, processor core, PLL etc. A macro can be hard or Soft
macro.
• Target Library: A technology library that Design Compiler maps to during optimization. Along with
the link_library and search_path variables, you need to specify the logical library that will be used
for mapping/optimization.
• Link Library : The technology library that contains the definition of the cells used in the mapped
design. In principle should be the same as target_library unless a technology translation is being
performed.
• Search Path: If the library variables only specify file names, search_path is used to locate libraries.
By default points to current working directory. By default, you must specify the unix-path for all
files (relative or absolute). It specifies where to look for files.
Constraints: Constraints are the instructions that the designer can apply during various steps in the VLSI chip
implementation, such as logic synthesis, Clock Tree synthesis (CTS), Place & Route, and Static Timing Analysis
(STA). Constraints are 2 types:
1. Design Rule Constraints
2. Optimization Constraints
• Design Rule Constraints:
• These are implicit constraints.
• The technology library (.lib) defines them.
• These constraints are requirements for a design to them.
• These constraints are requirements for a design to function correctly, and they apply to any design using the library.
• You can make these constraints more restrictive than optimization constraints.
• Different types of Design Rule Constraints are
1. Maximum Transition time
2. Maximum Fanout
3. Maximum/Minimum Capacitance
4. Cell Degradation
• Optimization Constraints:
• These are explicit constraints;
• Designer define them.
• Optimization constraints apply to the design on which you are working for the duration of the dc_shell session and represent the
design’s goals.
• They must be realistic.
• Optimization Constraints describe the design goals (Area, Timing etc)
• Maximum Transition time: The maximum transition time for a net is the longest time required
for its driving pin to change logic values. Typically fixed by buffering the output of driving gate.
• Maximum Fanout: The maximum fanout of an output measures it’s load driving capability.
Most technology libraries (.lib) place fanout restrictions on driving pins, creating an implicit
fanout constraint for every driving pin in designs using that library. Design Compiler models
fanout restrictions by associating a fanout_load attribute with each input pin and a
max_fanout attribute with each output (driving) pin on a cell.
• Maximum Capacitance: The maximum total capacitance that an output pin can drive. The
maximum capacitance design rule constraint allows you to control the capacitance of nets
directly. (The design rule constraints max_fanout and max_transition limit the actual
capacitance of nets indirectly.)
• Minimum Capacitance: The min_capacitance design rule specifies the minimum load a cell
can drive. It specifies the lower bound of the range of loads with which a cell has been
characterized to operate.
Optimization Constraints:
• Timing Constraints: Timing Constraints are required to communicate the design’s timing intentions
to IC Compiler. They should be the same ones used for synthesis with Design Compiler (preferably
SDC).
• Synopsys Design Constraints (SDC): A format used to specify the design intent including the timing,
power and area constraints of a design. SDC is tool based. SDC contains 4 types of information.
1. SDC Version
2. SDC units
3. Design Constraints
4. comments
SDC version: It sets the version. Default version is 1.9
Design Constraints: The following are the design constraints are specified in SDC
• system clock definition
• clock delays
• Multi Cycle Paths
• Input & output delays
• Minimum & Maximum path delays
• Input transition and output load capacitance
• False paths
Clock Tree Synthesis (CTS): CTS is the process of inserting buffers/inverters along the clock paths of the design
in order to balance the skew and to minimize insertion delay. Skew: Skew is the difference in arrival of clock at
two consecutive pins of a sequential element.
• Positive skew– If capture clock comes late than launch clock then it is called positive skew.
• Negative skew-If capture clock comes early than launch clock it is called -ve skew.
• Local skew– It is the difference in arrival of clock at two consecutive pins of a sequential element.
• Global skew– It is Defined as the difference between max insertion delay and the min insertion delay of any
flops. Boundary skew-It is defined as the difference between max insertion delay and the min insertion
delay of boundary flops.
• Useful skew-If clock is skewed intentionally to resolve violations, it is called useful skew.
• Latency– Latency is the delay of the clock source and clock network delay.
• Source latency– The delay from the clock origin point to the clock definition point in the design.
• Network latency– The delay from the clock definition point to the clock pin of the register.
• Uncertainity– Clock uncertainty is the time difference between the arrivals of clock signals at registers in
one clock domain or between domains.
• Jitter– Jitter is the short-term variations of a signal with respect to its ideal position in time. It is the variation
of the clock period from edge to edge.
Setting Operating conditions:
1.Process Variation: Variations in the process parameters, such as impurity concentration
densities, oxide thicknesses, and diffusion depths. These are caused by non-uniform
conditions during the deposition and/or the diffusion of the impurities. This introduces
variations in the sheet resistances and transistor parameters such as the threshold voltage
Variations in the dimensions of the devices, mainly resulting from the limited resolution of the
photo lithographic process. This causes (W/L) variations in MOS transistors and mismatches in
the emitter areas of bipolar devices.
2.Supply Voltage Variation
3.Ambient temperature Variations
4.It is important to analyze the design for best case and worst case scenarios. Best case to find
issues with hold time violations and worst case to find issues with setup violations.
Timing Analysis: Timing analysis is a method of validating the timing performance of a design by checking
the timing paths for timing violations.
• Net Delay: Interconnect relationships between a driver pin and its fanout In the absence of physical
design information, the timing analyser in Synopsys uses statistically generated wire load models to
estimate wire lengths in a design. Two important concepts behind wire load models are
1. Wire load models provide a fanout to length relationship. So by knowing fanout, one can estimate the length.
2. capacitance and resistance per unit length are given and the estimated length is then translated into estimated R
and C values to give an estimated delays. Wire load models are area dependent. Larger the area, greater the R and C
value per unit length.
• Cell Delay: Timing relationships between an input pin and an output pin, or between an output pin and
another output pin of the same gate. Cell delay is calculated using non-linear delay models, which are
stored in the ‘LM’ view of each cell.
• NLDM is highly accurate as it is derived from SPICE characterizations.
• The delay is a function of the input transition time of the cell (TInput) [also called slew], the driving
strength of the cell (RCell), the wire capacitance (CNet) and the pin capacitance of the receivers (CPin).
• A slow input transition time will slow the rate at which the cell’s transistors can change state (from “on”
to “off”), as well as a large output load (Cnet + Cpin), thereby increasing the “delay” of the logic gate.
• There is another NLDM table in the library to calculate output transition. Output transition of a cell
becomes the input transition of the next cell down the chain.
VLSI Design Domains
VLSI DESIGN FLOW
VLSI Design Styles
Full-Custom: In its most general form of design style, the circuit is partitioned into a
collection of sub-circuits according to some criteria such as functionality of each sub-
circuit.
The process is done hierarchically and thus full-custom designs have several levels of
hierarchy. The chip is organized in clusters, clusters consist of units, and units are composed
of functional blocks (in short, blocks).
For sake of simplicity, we use the term blocks for units, blocks, and clusters. The full-custom
design style allows functional blocks to be of any size. In the full-custom design style, blocks
can be placed at any location on the chip surface without any restrictions. In other words,
this style is characterized by the absence of any constraints on the physical design process.
Full custom design is very time consuming; thus the method is inappropriate for very large
circuits, unless performance or chip size is of utmost importance. Full custom is usually
used for the layout of microprocessors and other performance and cost sensitive designs.
Standard Cell: The design process in the standard cell design style is somewhat simpler than full-
custom design style. Standard cell architecture considers the layout to consist of rectangular cells of
the same height.
Initially, a circuit is partitioned into several smaller blocks, each of which is equivalent to some
predefined subcircuit (cell). The functionality and the electrical characteristics of each predefined
cell are tested, analyzed, and specified. A collection of these cells is called a cell library.
Usually a cell library consists of 500-1200 cells. Terminals on cells may be located either on the
boundary or distributed throughout the cell area. Cells are placed in rows and the space between
two rows is called a channel. These channels and the space above and between cells is used to
perform interconnections between cells. If two cells to be interconnected lie in the same row or in
adjacent rows, then the channel between the rows is used for interconnection.
However, if two cells to be connected lie in two non-adjacent rows, then their interconnection wire
passes through empty space between any two cells or passes on top of the cells. This empty space
between cells in a row is called a feedthrough.
A standard cell design usually takes more area than a full-custom or a handcrafted design. The
standard cell layout is inherently non-hierarchical.
Gate Arrays: This design style is a simplification of standard cell design. Unlike standard cell design, all
the cells in gate array are identical. Each chip is an array of identical gates or cells. These cells are
separated by both vertical and horizontal spaces called vertical and horizontal channels.
The circuit design is modified such that it can be partitioned into a number of identical blocks. Each block
must be logically equivalent to a cell on the gate array. The name ‘gate array’ signifies the fact that each
cell may simply be a gate, such as a three input NAND gate. Each block in design is mapped or placed
onto a prefabricated cell on the chip during the partitioning/placement phase, which is reduced to a
block to cell assignment problem.
Figure above shows an ‘uncommitted’ gate array, which is simply a term used for a prefabricated chip.
The gate array wafer is taken into a fabrication facility and routing layers are fabricated on top of the
wafer. The completed wafer is also called a ‘customized wafer’.
This simplicity of gate array design is gained at the cost of rigidity imposed upon the circuit both by the
technology and the prefabricated wafers. The advantage of gate arrays is that the steps involved for
creating any prefabricated wafer are the same and only the last few steps in the fabrication process
actually depend on the application for which the design will be used.
Hence gate arrays are cheaper and easier to produce than full-custom or standard cell. Similar to
standard cell design, gate array is also a non-hierarchical structure.
FPGAs: In FPGAs, cells and interconnect are prefabricated. The user simply ‘programs’ the interconnect.
FPGA designs provide large scale integration and user programmability.
A FPGA consists of horizontal rows of programmable logic blocks which can be interconnected by a
programmable routing network. Given a certain input, the logic block ‘looks up’ the corresponding
output from the logic table and sets its output line accordingly. Thus by loading different look-up tables,
a logic block can be programmed to perform different functions.

Connection between horizontal segments is provided through antifuses, whereas the connection
between a horizontal segment and a vertical segment is provided through a cross fuse.
Figure above shows the general architecture of a FPGA, which consists of four rows of logic blocks. The
cross fuses are shown as circles, while antifuses are shown as rectangles. One disadvantage of fuse
based FPGAs is that they are not reprogrammable.

There are other types of FPGAs which allow re-programming, and use pass gates rather than
programmable fuses. Many FPGAs allow the user to re-program the interconnect, as many times as
needed. These FPGAs use non-destructive methods of programming, such as pass-transistors. The
programmable nature of these FPGAs requires new CAD algorithms to make effective use of logic and
routing resources.
Layout Layers and Design Rules
Layout layers of an inverter cell
with external connections

Inverter Cell

Vdd
Metal2 Contact

Metal1 Via

polysilicon

p/n diffusion

GND

© 2011 Springer Verlag

External
Connections

28
Layout Layers and Design Rules
Categories of design rules

• Size rules, such as minimum width: The dimensions of any component (shape), e.g., length of a
boundary edge or area of the shape, cannot be smaller than given minimum values. These
values vary across different metal layers.

• Separation rules, such as minimum separation: Two shapes, either on the same layer or on
adjacent layers, must be a minimum (rectilinear or Euclidean diagonal) distance apart.

• Overlap rules, such as minimum overlap: Two connected shapes on adjacent layers must have a
certain amount of overlap due to inaccuracy of mask alignment to previously-made patterns on
the wafer.

29
Layout Layers and Design Rules
Categories of design rules

: smallest meaningful technology-

dependent unit of length

a 
c
Minimum Width: a
Minimum Separation: b, c, d
e
Minimum Overlap: e
d
b

© 2011 Springer Verlag

30
VLSI Physical
Design Cycle
 VLSI Physical Design cycle
• The input to the physical design cycle is a circuit diagram and the output is
the layout of the circuit.
• This is accomplished in several stages such as partitioning,
floorplanning, placement, routing, and compaction.
• Physical design, like VLSI design, is iterative in nature and many steps, such
as global routing and channel routing, are repeated several times to obtain
a better layout.
• The quality of results obtained in a step depends on the quality of the
solution obtained in earlier steps. For example, a poor quality placement
cannot be ‘cured’ by high quality routing.
• As a result, earlier steps have more influence on the overall quality of the
solution.
 Physical Design Optimizations
Types of constraints

• Technology constraints enable fabrication for a specific technology node and are derived from
technology restrictions. Examples include minimum layout widths and spacing values between layout
shapes.

• Electrical constraints ensure the desired electrical behavior of the design. Examples include meeting
maximum timing constraints for signal delay and staying below maximum coupling capacitances.

• Geometry (design methodology) constraints are introduced to reduce the overall complexity of the
design process. Examples include the use of preferred wiring directions during routing, and the
placement of standard cells in rows.

33
 ASIC Design Flow

• ASIC (Application Specific Integrated

Circuit) Design flow
• The very first step of ASIC flow is design
specification, which comes from the customer
end. Where customer writes down the
specification of the chip basically the
functionality which he wants to develop in a
chip.
• The whole design process is going through
various design cycles and it generally takes 6 to
24 months to complete the design depending on
the complexity inside the chip. The complete
ASIC design process can be divided into two
parts:
1.Front End Design
2.Back End Design
https://teamvlsi.com/2020/05/asic-design-flow-overview-v1.html
Front End Design:
• Front end design process starts with the specification received
from the customer end. RTL (Register Transfer Level) design
engineer converts the specification into an RTL code using the
HDL (Hardware Description Language) generally either in Verilog
or VHDL.
• Once the RTL code is written, RTL designer simulates the code in
RTL Simulator and check the functionality of the design. Once the
functionality of code is correct and verified by the verification
engineers and if there is no bug found, This RTL code is taking to
the next stage which is logic synthesis.
• This flow starts with RTL coding and ends with GDS (Graphic Data
Stream) file which is the final output of back end design, so this
complete flow is also known as RTL to GDS (RTL2GDS) flow.
Back End Design:
• RTL code received from the front end engineer is technology independent, now the next step is Logic synthesis.
• Logic Synthesis: In logic synthesis, a high-level description of the design (RTL Code) is converted into an
optimized gate-level representation of a given standard cell library and certain design constraints. Now the code is in
the form of a gate-level netlist of a particular standard cell library. LEC (Logic Equivalence Check is must in this
stage to make sure that there are not logical changes occurred during the synthesis. During logical Synthesis, we
also get various reports on timing power and area of design. We also get an SDC (Synopsys Design Constraint) file
in this stage which is used in the next stage. DFT (Design For Testability) Insertion is also done in this stage to verify
the chip after fabrication is done.
• Place and Route (PnR): Gate level netlist after DFT Insertion and SDC file is taken as input for the PnR and based
on standard cells library, PnR starts. The goal of PnR stage is to place all the standard cells, Macros and I/O pads
with minimal area, with minimal delay and Route them together in such a way that there is no DRC (Design Rule
Check) error. The final output of this stage is the layout of design in the form of GDSII file which is defacto standard
of layout file in the industry. PnR stage is a very challenging stage with large design cycle time depending on the
complexity of a chip. This stage is further divided into various sub-stages. The main stages are starting from Design
Import, followed by FloorPlan, Power Plan, Placement, CTS (Clock Tree Synthesis), and Routing. After routing we
expect the design has met the timing and all DRC, But in the modern chip, it’s not easy to close the design in this
stage. So Further we go to Signoff stage.

• Signoff: If there are some timing violations in post route design, we have a further stage called ECO (Engineering
Change Order) where we can fix the timing violations. Apart from timing violation, there may be issues like IR Drop,
DRC Violations all these are fixed in this stage and a final layout file free from all the violation is streamed out in
GDSII format. This process is known as tapeout in ASIC flow. This is the final design stage and GDSII file is sent to
fabrication lab for the fabrication of chip.
 Libraries
Various types of datasets or libraries are required for the physical design
of an ASIC. Technology libraries are integral part of the ASIC backend
EDA tools.

Libraries are the collection of the physical layout, abstract views, timing
models, simulation or functional models and transistor level circuit
descriptions.

As such, libraries are considered one of the most critical parts of the ASIC
physical design, and the accuracy of these libraries and their associated
views and models has a great impact on the success of the final
fabricated ASIC design.
 Important two libraries are briefly explained below:
Technology File Libraries:

• Technology file defines basic characteristic of cell library pertaining

to a particular technology node.
• They are units used in the design, graphical characteristics like
colors, stipple patterns, line styles, physical parameters of metal
layers, coupling capacitances, capacitance models, dielectric
values, device characteristics, design rules.
• Units for power, voltage, current etc are defined in technology
section.
• The color section defines primary and display colors that a tool uses
to display designs in the library.
• Stipple pattern are defined in stipple sections.
• Different layer definitions like its current density, width etc are
defined in layer section.
• Fringe capacitances generated by crossing of interconnects are
defined in fringe cap section.
• Similarly several other specifications like metal density, design rules
that apply to design in library, place and route (P&R) rules, slot rule,
resistance model are defined in their respective sections.
Standard Cell Libraries, I/O Cell Libraries, Special Cell Libraries

• A standard cell library is a collection of pre designed layout of basic logic gates like inverters,
buffers, ANDs, ORs, NANDs etc.
• All the cells in the library have same standard height and have varied width. These standard
cell libraries are known as reference libraries in Astro.
• These reference libraries are technology specific and are generally provided by ASIC vendor
like TSMC, Artisan, IBM etc. Standard cell height for 130 TSMC process is 3.65 µM.
• In addition to standard cell libraries, reference libraries contain I/O and Power/Ground pad cell
libraries. It also contain IP libraries for reusable IP like RAMs, ROMs and other pre-designed,
standard, complex blocks. These IP libraries also referred as Custom libraries which are the
collection of manually crafted analog function layouts such as PLL, ADC, DAC, VR etc.
• The TSMC universal I/O libraries include several power/ground cells that supply different
voltages to the core, pre-drivers and post drivers. Internal pull-up or pull-down is provided to
some cells in I/O libraries.
The concept of Libraries can be understood
with the detailed analysis of the following
aspects:
 Standard Cells
 Transistor Sizing
 Input-Output Pads
 Library Characterization

Figure: Library Development Steps

 RTL-Gate Level Synthesis
https://youtu.be/PUxrn6NJIlM

The journey of RTL to Gate level synthesis can be analyzed in 3 aspects:

• Logic Synthesis
• Physical aware synthesis
• Power aware synthesis
 RTL description
• Register transfer level (RTL) is an abstraction for defining
the digital portions of a design. It is the principle abstraction
used for defining electronic systems today and often serves
as the golden model in the design and verification flow.
• The RTL design is usually captured using a hardware
description language (HDL) such as Verilog or VHDL. While
these languages are capable of defining systems at other
levels of abstraction, it is generally the RTL semantics of
these languages, and indeed a subset of these languages
defined as the synthesizable subset.
• This means the language constructs that can be reliably fed
into a logic synthesis tool that in turn creates the gate-level
abstraction of the design that is used for all downstream
implementation operations.
• RTL is based on synchronous logic and contains three
primary pieces namely, registers which hold state
information, combinatorial logic which defines the nest state
inputs, and clocks that control when the state changes.
Note before design and synthesis:
Your RTL design
 Functional verification by some high-level language
 Also, the code coverage of your test benches should be verified
 Coding style checking (i.e. n-Lint) Good coding style will reduce most hazards while synthesis
 Better optimization process results in better circuit performance
 Easy debugging after synthesis
Constraints
• The area and timing of your circuit are mainly determined by your circuit/design architecture and
coding style.
• There is always a trade-off between the design timing and area.
• In fact, a super tight timing constraint may work while synthesis, but failed in the Place & Route
(P&R) procedure.
Stages of Synthesis:
• Identify the Time based State Machine
• Infer the logic and state elements.
• Perform technology independent optimization(logic simplification and state assignment.
• Map elements to the target technology
• Perform technology dependent optimizations (multi level logic optimization , choose gate
History of Synthesis Tools
Importance of Synthesis in ASIC design flow
Gate level Synthesis

• The term "gate level" refers to the netlist view of a circuit,

usually produced by logic synthesis. So while RTL
simulation is pre-synthesis, GLS is post-synthesis. The
netlist view is a complete connection list consisting of
gates and IP models with full functional and timing
behavior.
• RTL is the input to synthesis, gate level is the output from
synthesis.
 Unit-1: Assignment Questions
1. Briefly explain the work flow of VLSI design cycle.
2. Explain the importance of different stages available in Physical
Design Cycle.
3. Explain the classification of Design styles in VLSI design.
4. Briefly explain the work flow of ASIC Design Flow.
5. Explain the importance of Libraries in VLSI design.
6. Describe the process involved in RTL to Gate level synthesis.
7. What is the importance of Library Characterization.
8. Explain the significance of Layout layers and Design rules.
Deconstructing the synthesis steps