International Journal of Engineering and Technical Research (IJETR)

ISSN: 2321-0869, Volume-3, Issue-6, June 2015

Energy Efficient High Speed Floating Point

Arithmetic Unit
Somya Kumawat, Arpan Shah, Ramesh Bharti

whether the operation was performed successfully [5]. (If it

Abstract Energy Efficient High Speed Floating Point wasn't, some sort of status would be stored in a everlasting
Arithmetic Unit is introduced in this paper where power place that was sometimes called the machine status word).
optimization has been done. In this paper, the concept of [6]
Floating Point (FLP) operation into a single arithmetic logic Usually, the ALU included storage places for input
unit (ALU) that can perform multiplication, subtraction and
operands, operands that were being added, result stored in
addition more rapidly, accurate and less complex has been
reviewed. The merit of floating point is that precision is an accumulator, and shifted results [7]. Gated circuits
maintained with a wide dynamic range, where fixed point controlled the flow of bits and the operations performed on
numbers lose precision them in the sub units of the ALU. The gates in these circuits
were controlled by a series logic unit that used a particular
Index Terms ALU, FLP, IEEE-754, IEEE-854 algorithm or series for each operation code. Multiplication
and division were done by a series of adding or subtracting
and operations which done shifting in the arithmetic unit [8].
I. INTRODUCTION There were several ways to represent numbers which are
Floating-point arithmetic was taken as a mysterious topic by negative. In the logic unit, one out of 16 possible logic
several people. This was rather surprising because floating- operations could be performed - such as comparing two
point was omnipresent in computer systems. Almost every operands and identifying where bits do not match. A
language had a floating-point data type; computers from floating-point group could be used to represent with a fixed
PCs to supercomputers have floating-point accelerators [1]; number of digits, numbers of dissimilar orders of
most of the compilers would be called upon to compile magnitude: e.g. the distance between galaxies or the
floating-point algorithms from time to time; and practically diameter of an atomic nucleus could be expressed with the
every operating system must react to floating-point same unit of length [9] - [10]. The result of this dynamic
exceptions such as flooded [2]. An arithmetic-logic unit range was that the numbers that could be represented were
(ALU) was the part of a computer processor (CPU) that not uniformly spaced; the diversity between two consecutive
carried out arithmetic and logic operations on the operands numbers grows with the selected scale.
in computer instruction words. In several processors, the Floating-point numbers were well defined by IEEE-754
ALU was split into two units, an arithmetic unit (AU) and a (32 and 64 bit) and IEEE-854 (variable width)
logic unit (LU). Some processors contained one or more AU specifications. Floating point had been used in processors
- for example, one for fixed-point operations and another for and IP for years and was a well-understood system. This
floating-point operations. Usually, input and output was a sign magnitude system, where the sign was processed
approach to the processor controller, main memory (random a different way from the magnitude [10]. There were many
access memory or RAM in a PC), and input/output devices concepts in floating point that made it unusual from our
had been directly done the ALU [2] - [3]. A bus was an common signed and unsigned number notations. These
inputs and outputs flow along an electronic lane. The input came from the definition of a floating-point number [11].
consisted of an instruction word (occasionally called a All the floating point numbers were made up of
machine instruction word) that contained an operation code following components:
(occasionally called an "op code"), one or more operands, Sign: it indicated the sign of the number (0 positive
and occasionally a format code. What operation to perform and 1 negative)=1 bit
and the operands were used in the operation was told by the Mantissa: it place the value of the number=23 bits
operation code to the ALU (For example, two operands Exponent: it contained the value of the base power
might be added together or compared logically) [4].The (biased)=8 bits
format might be combined with the op code and it was told, Base: the base (or radix) was suggested and it was
for example, whether this was a floating-point or a fixed- common to all the numbers (2 for binary numbers
point instruction. The output consisted of a result that was We had used the following packages [11] - [12]:
placed in a storage register and settings that indicated Denormalize Boolean: This was used to turn on and off
denormal numbers. The default was true (permit denormal
numbers)
Somya Kumawat, student M.Tech (VLSI), Jagan Nath University, Round_style round_type: This was used to denote the
Jaipur, India. rounding style to be used. The default was Round_nearest
Arpan Shah, Assistant Professor Department of ECE, Jagan Nath
University, Jaipur, India. and the most hardware was taken by it. A truncation,
Ramesh Bharti, Associate Professor Department of ECE, Jagan Nath round_inf and round_neginf round up or down were done by
University, Jaipur, India. Round_zero depending on whether the number was positive
or negative.

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 Energy Efficient High Speed Floating Point Arithmetic Unit

Check_error Boolean: Infinity processing and turns off III. RESULTS

NAN. At the commencement of every operation these
checks were needed and if we had already checked once we
needed not check again.
Guard_bits natural: This was the number of extra bits
POWER(mW)
used on each operation to preserve accuracy. The default
was 3. But rounding was automatically turned off, if we
154
took this down to zero.
152
No_warning Boolean: Permit us to turn off the
metavalue warnings by setting this to false. 150
POWER(mW)
Float_exponent_width: For conversion routines, it was 148
default. Set by default to the size of a 32 bit floating point 146
number (8). Previous Proposed
Float_fraction_width: For conversion routines, it was Design Design
default. Set by default to the size of a 32 bit floating point
number (23).
Fig 1 Graphical Comparison of Power

II. ALGORITHMS DELAY(ns)

A. Adder
1. Take two floating points numbers. 29
2. Separate the numbers into mantissa and exponent. 28
3. Find the larger exponent. Let say Ex and Ey. 27 DELAY(ns)
4. If Ex=Ey then only add the mantissa together. 26
5. If exponents are not same then normalize to higher Previous Proposed
exponent ,let Ex > Ey then Design Design
a. Find the difference between
exponents Ex-Ey Fig 2 Graphical Comparison of Delay
b. Shift mantissa of smaller number
right by difference Ex-Ey
c. Set exponent of result Ez to
bigger exponent Ex
AREA(No. of LUTs)
6. Now that exponent are identical add mantissa
together, mantissa of result Mz = Mx + My .
1000
7. Set sign of result according to previous result.
B. Subtractor 500 AREA(No. of
LUTs)
1. Take two floating points numbers. 0
2. Separate the numbers into mantissa and exponent. Previous Proposed
3. Find the larger exponent. Let say Ex and Ey. Design Design
4. If Ex=Ey then only subtract the mantissa.
5. If exponents are not same then normalize to higher
Fig 3 Graphical Comparison of Area
exponent, let Ex > Ey then
a. Find the difference between
exponents Ex-Ey
b. Shift mantissa of smaller number Fig 4 Graphical Compar
right by difference Ex-Ey
c. Set exponent of result Ez to DELAY(ns) * POWER
bigger exponent Ex
6. Now that exponent are identical, subtract mantissa, (mW)
mantissa of result Mz = Mx + My
7. Set sign of result according to previous result.
4.4
C. Multiplier
4.2 DELAY
1. Take two floating points.
2. Separate the numbers into mantissa (Mx, My)and 4 (ns)*POWER
exponent (Ex, Ey). 3.8 (mW)
3. Calculate the sign of the result from the sign of the Previous Proposed
inputs. Design Design
4. Add the exponents Ex + Ey.
5. Multiply the mantissa Mx * My. ison of Delay * Power
6. Store the result by combining the sign, mantissa DELAY(ns)*
POWER DELAY AREA
and exponent. POWER

62 www.erpublication.org
 International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869, Volume-3, Issue-6, June 2015

(No. of Somya Kumawat, Student of M.Tech in Jagan Nath University, Jaipur.

(mW) (ns) (mW) I have completed my M.Tech (VLSI) in 2015 from Jagan Nath University
LUTs)
and B.Tech degree in 2013 from Rajasthan Technical University. I am
PREVIOUS currently working in the VLSI field
153 28.743 838 4.397
DESIGN
PROPOSED Arpan Shah, Assistant Professor Department of ECE in Jagan Nath
149 27.505 634 4.098 University, Jaipur, India. He has completed his M.Tech (VLSI) in 2012
DESIGN
and publish various research papers in field of VLSI and Embedded
Table 1 Overall Comparison of Previous Design and Proposed Design
System. He has guided more than 10 M.Tech students for their research
work.

IV. CONCLUSION Ramesh Bharti, Associate Professor Department of ECE in Jagan Nath
University, Jaipur. He is currently pursuing PhD from Jagan Nath
Table 1 shows the Overall Comparison of Previous Design University. He has completed his M.Tech (ECE) in 2010 from MNIT
and Proposed Design. It was clear that there is a decrease in Jaipur, and B.E degree in 2004 from Rajasthan University. He is currently
circuitry, power consumption, time consumption as working in the wireless communication.
compared to the previous design, also the overall
performance (delay (ns) *power (mW) )is reduced by 6.8%.

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