Design & Simulation Of 32-Bit Floating Point ALU

DESIGN & SIMULATION OF 32-BIT FLOATING POINT ALU

1
KAVITA KATOLE, 2ASHWIN SHINDE, 3SUMEDHA CHOKHANDRE, 4BHUSHAN MANJRE,
5
NIRJA DHARMALE
1234
Asst.Prof, 123DBACER, 4PCOE, 5RCOE

Abstract— VHDL environment for floating point arithmetic and logic unit design is introduced the novelty in the ALU design
which provides a high performance ALU to execute multiple instructions simultaneously. In top-down design approach,
arithmetic modules, addition, subtraction, multiplication, division, comparison & logical functions are combined to form a
floating point ALU unit. Each module is divided into sub- modules with four selection bits are combined to select a particular
operation. Each module is independent to each other. The modules are realized and validated using VHDL simulation in the
Active HDL software.

Keywords— VHDL, Xilinx 9.2 ISE, ALU, Floating point

I. INTRODUCTION fixed point representation. In this representation, each

number is treated as a fraction between -1 and 1. The
The term floating point is derived from the fact that magnitude of each number ranges from 0 to 1. The
there is no fixed number of digits before and after the main advantage of this format is that multiplication
decimal point, that is, the decimal point can float. doesn’t cause overflow, only addition can cause an
There are also representations in which after the overflow. Many DSP coefficients and transforms,
decimal point, that is, the decimal point can float. especially FFT and IFFT, that we will be using in
The number of digits before and after the decimal OFDM are typically fractions and can be easily
point is set, called fixed-point representations. In expressed in this format. to implement this approach,
general, floating point representations are slower various types of formats are available such as unsigned
and less accurate than fixed-point algorithms from integer, offset binary, sign and magnitude and two’s
time to time; and virtually every operating system complement. Of them all, two’s complement is the
must respond to floating-point exceptions such as most useful and is normally employed in all the digital
overflow representations, but they can handle a systems available. Using 16 bits, two's complement
larger range of numbers that can contain a can represent numbers from -32,768 to 32,767. The
fractional part. For e.g. following numbers are the left most bit is a 0 if the number is positive or zero, and
floating point numbers: 3.0, -111.5, ½, 3E-5 etc. a 1 if the number is negative. Consequently, the left
most bit is called the sign bit, just as in sign &
(A) Fixed point magnitude representation. Since each storage bit is a
In applications where a very narrow range is required, flip-flop, 2’s complement is the most convenient and
fixed point arithmetic may be appropriate. Using pure productive format that can be readily implemented
integer arithmetic provides a dramatic performance with positive as well as negative numbers.
improvement or decrease in cost when compared to
floating point. Float watch is unable to guarantee that (C) IEEE 754 Standards for Binary Floating-Point
values outside a particular range will not appear, so Arithmetic
appropriate handling of exceptional cases is required. The IEEE (Institute of Electrical and Electronics
Many of the test runs we have performed show Engineers) has produced a Standard to define
symmetry around 0, allowing the sign of a fixed-point floating-point representation and arithmetic the
number to be represented in the standard way for a standard brought out by the IEEE come to be known as
processor or custom design. For those with IEEE 754. The IEEE 754 Standard for Floating-Point
asymmetric value ranges a solution such as Dual Arithmetic is the most widely-used standard for
Fixed-point may be suitable. floating-point computation, and is followed by many
hardware (CPU and FPU) and software
(B) Fixed Point Approach implementations. Many computer languages allow or
Fixed point representation is used to store integers, the require that some or all arithmetic be carried out using
positive and negative whole numbers: … -3,-2,-1, 0, 1, IEEE 754 formats and operations. The current version
2, 3… The variant of the fixed point approach that are is IEEE 754-2008, which was published in August
normally used in a DSP application is called fractional 2008;

Proceedings of 3rd IRF International Conference, Pune, 2nd March. 2014, ISBN: 978-93-82702-62-7

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 Design & Simulation Of 32-Bit Floating Point ALU

It includes nearly all of the original IEEE 754-1985 A bias of 127 is added to the actual exponent to make
(which was published in 1985) and the IEEE Standard negative exponents possible without using a sign bit.
for Radix-Independent Floating-Point Arithmetic So for example if the value 100 is stored in the
(IEEE 854-1987). exponent place holder, the exponent is actually -27
The standard specifies: (100 – 127). Not the whole range of E is used to
 Basic and extended floating-point number formats represent numbers. As you may have seen from the
 Add, subtract, multiply, divide, square root, above formula, the leading fraction bit before the
remainder, and compare operations decimal point is actually implicit (not given) and can
 Conversions between integer and floating-point be 1 or 0 depending on the exponent and therefore
formats saving one bit. Table shows single precision
 Conversions between different floating-point representation with the corresponding values for a
formats given representation to help better understand what
 Conversions between basic format floating-point was explained above each quantity in an equation.
numbers and decimal strings The SI unit for magnetic field strength H is A/m.
 Floating-point exceptions and their handling, However, if you wish to use units of T, either refer to
including non numbers magnetic flux density B or magnetic field strength
symbolized as µ0H. Use the center dot to separate
(C) Formats compound units, e.g., “A·m2.”
The standard defines five basic formats, named using
their base and the number of bits used to encode them. (E) Arithmetic Logic Unit
There are three binary floating-point formats (which The arithmetic unit, also called the arithmetic logic
can be encoded using 32, 64, or 128 bits) and two unit (ALU), is a component of the central processing
decimal floating-point formats (which can be encoded unit (CPU). It is often referred to as the “engine” of the
using 64 or 128 bits). The first two binary formats are CPU because it allows the computer to perform
the ‘Single Precision’ and ‘Double Precision’ formats mathematical calculations, such as addition,
of IEEE 754-1985, and the third is often called 'quad'; subtraction, and multiplication. The ALU also
the decimal formats are similarly often called 'double' performs logic operations, like “AND,” “OR,” and
and 'quad'. “NOT.” The arithmetic unit works along with the
register array, which holds data, when processing

(D) Single Precision

The most significant bit starts from the left. The three
basic components are the sign, exponent, and
any of these operations. The arithmetic unit is
mantissa. The storage layout for single-precision is
comprised of many interconnected elements that are
shown below:
designed to perform specific tasks.
The number represented by the single-precision
format is:
(F) Flow-Chart
Value ==(−1) 2 × 1. f (normalized) when E > 0 else
Flow chart of addition/subtraction unit
(−1) 2 × 0. f (denormalized)
Fig shows Flow chart of addition/subtraction unit. Let
us see from flow-chart ,if we take 2 numbers in
Where, f = ( + + +…. + ) Where =1 or 0
standard 32-bit floating point format .We get both the
s = sign (0 is positive; 1 is negative)
number in mantissa and exponent form. At first the
E =biased exponent; Emax = 255, Emin =0. E=255 and
exponent of both the number is compared. If it is equal
E=0 are used to represent special values.
then mantissa of both numbers are added. After
e =unbiased exponent; e = E – 127(bias)
adding mantissas if we get normalized result then can
store result directly. But if the result is not normalized

Proceedings of 3rd IRF International Conference, Pune, 2nd March. 2014, ISBN: 978-93-82702-62-7

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 Design & Simulation Of 32-Bit Floating Point ALU

then we have to increment the exponent and mantissa Manual Simulation Window
is shifted to the right, then we get normalized result You can perform either a single step simulation,
and we can store result. But if exponent is not equal which is useful for source code debugging, or a
then we have to increment smaller exponent to make continues simulation. Finish simulation by selecting
both exponent equal and mantissa is shifted right and the End Simulation option in the Simulator menu.
further repeats the same process. Save your waveform before exit.

II. BLOCK DIAGRAM OF Test Bench Simulation

ADDER/SUBTRACTOR You have an option to create the test bench and run the
simulation automatically instead of assigning
stimulators. Following picture is a result of running
counter test bench

Fig : Block Diagram of Addition/Subtraction unit

Please note that the references at the end of this

document are in the preferred referencing style. Give CONCLUSION
all authors’ names; do not use “et al.” unless there are
six authors or more. Use a space after authors' initials. This paper suggests the behavioral design method for
Papers that have not been published should be cited as VHDL implementation of a 32-bit ALU using Xilinx
“unpublished”. Papers that have been submitted for 9.2 tool. Its functionality was discussed for all the
publication should be cited as “submitted for operations specified. As per the nature of behavioral
publication”. Papers that have been accepted for description, it is easy to convert the precision to 64- bit
publication, but not yet specified for an issue should be r more. This behavioral design can be made
cited as “to be published” . Please give affiliations and synthesizable and thus can be used for layout and
addresses for private communications. fabrication on FPGA based digital circuits.

A. Syntax Checking Successful REFERENCES

[1] D. Gajski and R. Khun, “Introduction: New VLSI Tools,” IEEE

Computer, Vol. 16, No. 12, pp. 11-14, Dec. 1983.
[2] www.forteds.com/behavioralsynthesis/index.asp
[3] Douglas L. Perry, VHDL, third edition, McGraw-Hill, pp.
60-63, 238, July 1999.
[4] S.Yalamanchali, “Introductory VHDL: From simulation to
synthesis”, Prentice Hall, United States, 2002.
[5] V.A.Pedroni, “Circuit design with VHDL”, Cambridge,
Massachusetts, London, England, 2004.
[6] P.J.Ashenden, “The VHDL Cookbook”, University of Adelaide,
South Australia, July, 1990.
[7] http://www.xilinx.com

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Proceedings of 3rd IRF International Conference, Pune, 2nd March. 2014, ISBN: 978-93-82702-62-7

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