International Journal of Engineering and Technical Research (IJETR)

ISSN: 2321-0869 (O) 2454-4698 (P), Volume-3, Issue-10, October 2015

High Speed Pipelined 4 Input Decimal Adder

Rishabh Panday, Himanshu Joshi

Abstract In the present days after increasing the complexity II. PREVIOUS WORK
in the computation, internet based applications we need a fast
and compact decimal adder which work with less delay and A. BCD adder
same power consumptions. So we can design a pipelined four
input decimal adder using the DG, DP signals and Correction
digits. By using the CSA, CLA, PG generator and with a
register we reduce the delay of the adder with 46.22% compare
to conventional decimal adders by synthesize the simulation in
Xilinx software. In our proposed work decimal adder is divided
in two parts and a register is used in between that for reduce the
delay of critical path. So the pipelined decimal adder can work
fast addition of the decimal numbers.

Index TermsAdder, CSA, CLA, DG & DP generator,

Register.

I. INTRODUCTION

In the past time all the computers and processers and many
digital devices used the binary arithmetic such that addition
but that type of addition have some approximate errors. For an
example take (0.9)10= (0.1110)2 this is not show the exact
result of the decimal fraction number. It requires the infinite
bits for represent the decimal number so for overcome by
these types of problems BCD binary coded decimal numbers
are used for take the exact result. In the BCD numbers every
decimal digit represent in the four bits. By using the BCD,
decimal numbers are exactly represented like
(0.9)10=(0.1001)2. So the results are taken in finite bits.
So we proposed a work on high speed pipelined four input
decimal adder. In the BCD adder sums of two digits are Fig 1: One digit BCD adder
generated but when the sums are greater than 9 than in every
digit a special correction value (0110)2 is added to the sum of Previously three input decimal adders are proposed. In the
every digit [2]. But by using these methods the delay of addition of the two digits (each 4 bits) one digit BCD adders
addition in the adders is so much. are used for add the decimal numbers. In that DG and DP
So our proposed pipelined decimal adder can reduce the delay signals [1] are used for generate the real carries and then add
of the decimal adder with using same area constraints. So we the sums with the correction logic digits for take the valid
provide the fast addition of the decimal numbers compare to results of the decimal numbers.
convention decimal adders. In a BCD adder we take two decimal digits A and B and take
Now with following this in section [2] a brief idea on the the sums of that with the one digit BCD adder with composed
convention decimal adders is given. In section [3] our with the four full adders. Now if the sum of the digit is greater
proposed pipelined work is explained with a numerical than 9 than a correction value 6 (0110)2 is added to the each
example. And in section [4] our implementation results and sum of the digit. For that a carry network is used in the
comparison between the conventional adders and pipelined addition. It is used for generate the carries of the decimal
decimal adder is given. In section [5] the summery of our digits.
proposed work is given.
Digit 1 A3 A2 A1 A0
Digit 2 B3 B2 B1 B 0

Carry S3 S2 S1 S0
Rishabh Panday, Electronics & Communication, Jagannath University,
Jaipur, India, 09460344714. And CC= carry + (Z8.Z4) + (Z8.Z2)
+ denotes logical OR
Himanshu Joshi, Assistant Professor, Jagannath University, Jaipur,
India, Mobile No. 9414618668. . denotes logical AND

222 www.erpublication.org
 High Speed Pipelined Four Input Decimal Adders

So if we increase the number of input in the decimal adder III. PROPOSED HIGH SPEED PIPELINED FOUR INPUT DECIMAL
than full adders are also increase in the decimal number and ADDER
the delay of the addition is also increased by that. So a new In our proposed pipelined decimal adder three stages are
type of BCD adder is designed for reduce the delay of the used for add the decimal numbers. each decimal number has
adder. four bits. In the first stage of our proposed decimal adder first
B. Reduced delay BCD adder block consists CSA and DG, DP generator. This block
generate the sums of each decimal digit and also DG (digit
In the second type of adder there are three stages which are
generate) and DP (digit propagate) signals. These DG and DP
used in the reduced delay BCS adders. In the first stage of the
signals are sent to the second stage which is carry network.
adder a block Adder+ Analyzer [2] is used. Two inputs are
Carry network generate the real carries of the decimal digits.
given to that block. This block is used for sum the digits and
generate the DG (Digit Generation) and DP (Digit
Propagation) signals. The sums which are generate by this
block if more than 9 than DG identify the condition of the
sums in the decimal adder. And when the sum is equal to 9
than condition is identified by the DP. Bothe these signals are
sent to the second stage which is a carry network. In the carry
network real carries are generate by using DG and DP signals.

Carry out = DG+DP.Cin

Fig 3: Architecture of four input decimal adder

In the second stage DG signals are identify the conditions

for the sums that if sums are not more than 9 or 19 or 29. And
DP signals are identify the condition that if sums are equal to
7,8,9,17,18,19,27,28 or 29 and generate these signals. And
after that in the third stage a adder is used for add the
correction values with the sums of each digit which is
generate in the last stage and produce the valid results.
In our proposed pipelined decimal adder also a stage is used
before the carry network. In that stage a register is used for
Fig2: Adder + Analyzer
store the values of the carries in the decimal adder. Register
divides the decimal adder in two parts. By divide the adder in
In the third stage the correction values are added to the digit
two parts the critical path of the adder is reduced so the delay
sums for take the valid results.
of the adder is also reduced. A clock signal is given to the
register or flip-flop.

223 www.erpublication.org
 International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869 (O) 2454-4698 (P), Volume-3, Issue-10, October 2015
Digit 4 Digit 3 Digit 2 Digit 1
1001 1000 0010 0000 W
1000 1001 0111 0100 X
0101 1000 1001 1001 Y
0111 0100 0111 0110 Z
11101 11101 11001 10011 Sum[4]

1 1 1 1 DG[1]
1 1 1 0 DG[2]
0 0 0 0 DG[3]
0 0 0 0 DP[1]
0 0 0 0 DP[2]
0 0 0 0 DP[3]
0 0 0 0 DP[4]
0 0 0 0 DP[5]
0 0 0 1 DP[6]
0 0 0 0 DP[7]
0 0 0 0 DP[8]
1 1 0 0 DP[9]

1 1 1 1 C10
Fig4: Proposed pipelined four input decimal adder 1 1 1 0 C20
1 1 0 0 C30
Table1: For DG and DP identifying conditions 10101 10100 01101 00110 Corr
Signals Conditions of the sum in 11101 11101 11001 10011 Sum[4]
each digit 10101 10100 01101 00110 Corr[4]
DG[1] >9 (110010)(110001)(100110)(11001) Result
DG[2] >19 IV. IMPLEMENTATION RESULTS AND COMPARISON
DG[3] >29 In the designing of pipelined four input decimal adder we
DP[1] =7 use the Xilinx software. In that verilog module is used for the
designing. After implementation and simulation of the codes
DP[2] =8 we get the delay of the decimal adder.
DP[3] =9
DP[4] =17
DP[5] =18
DP[6] =19
DP[7] =27
DP[8] =28
DP[9] =29

So by using the register the delay of the path is reduced. And

the total delay of the decimal adder is also decreased.
We take a numerical example of four input decimal numbers
9820 W
8974 X
5899 Y
+7476 Z
32169 Result

Fig5: Simulation result

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 High Speed Pipelined Four Input Decimal Adders

By comparing our results with the previously developed 754-2008 Decimal Rounding," Proc. 19th IEEE Symposium on
Computer Arithmetic (ARITH-19), pp. 135-144,2009.
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ACKNOWLEDGMENT [22] R.D. Kenney and M.J. Schulte, Multioperand Decimal
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The completion of that project gives us so much pleasure. I 251-253, Feb.2004.
would like to express my sincere gratitude to my project guide
Mr Himanshu Joshi for giving me the opportunity and
guideline to work on that. It would never be possible for us to Rishabh Panday, Student of M.Tech (Embedded System) in jagannath
university, Jaipur, India. I am completed B.Tech (Electronics &
take this project to this level without his innovative ideas and Communication) degree in 2012 from Rajasthan Technical University.
his relentless support and encouragement.
Himanshu Joshi, Assistant Professor Department of ECE in Jagannath
University, Jaipur, India. He has completed his M.Tech (VLSI and
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