This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2018.2878717, IEEE
Transactions on Circuits and Systems II: Express Briefs

New Majority Gate Based Parallel BCD Adder

Designs for Quantum-dot Cellular Automata
Tingting Zhang, Vikramkumar Pudi and Weiqiang Liu, Senior Member, IEEE

Abstract—In this paper, we first theoretically re-defined output use a new approach to compute carry logic in the multi-digit
decimal carry in terms of majority gates and proposed a carry BCD adder.
lookahead structure for calculating all the intermediate output In this paper, we propose a new definition for BCD adder
carries. We have used this method for designing the multi-digit
decimal adders. Theoretically, our best n-digit decimal adder output carry computation in terms of majority gates and use
design reduces the delay and area-delay product (ADP) by 50% it for computing all the carries of the multi-digit BCD adder
compared with previous designs. We have implemented our in parallel. We have introduced decimal group generate and
designs using QCADesigner tool. The proposed QCADesigner decimal group propagate signals to calculate carries in the
based 8-digit PBA-BCD adder achieves over 38% less delay BCD adder. As a result, we have reduced delay in the multi-
compared with the best existing designs.
digit BCD adder. We have used different types of binary
Index Terms—Majority gate, parallel BCD adder, carry looka- adders, such as RCA, CFA and parallel binary adder (PBA) for
head, quantum-dot cellular automata realizing the proposed multi-digit BCD adder. Theoretically,
our PBA based n-digit BCD adder reduces the delay and
area-delay product (ADP) by 50% compared with the existing
I. I NTRODUCTION
designs.
The decimal arithmetic has received wide attention in re- We have implemented our designs using QCA technology
sponse to the increasing demand for precision in financial and and designed using QCADesigner [4]. The proposed QCADe-
commercial based applications [1]. Several digital processors signer based 8-digit PBA-BCD adder achieves at least 38% less
and computers were designed including decimal arithmetic delay compared with the best existing designs in [10]–[12].
hardware units [2], [3]. The rest of the paper is organized as follow. The conven-
The current CMOS technology is approaching its scaling tional structure of decimal adders are presented in Section
limitation. New nanotechnologies including quantum-dot cel- II. The proposed structure of decimal adders, especially the
lular automata (QCA) [4], nanomagnetic Logic (NML) [5], circuit for calculating decimal carry is provided in Section III.
and spin-wave devices (SWD) [6] are studied due to their Section IV presents the complexity analysis, area complexity
advantages in terms of low power and high density. These and delay complexity included. Experimental results using
emerging nanotechnologies are based on majority logic, which QCA and comprehensive comparison with previous relevant
is different from conventional Boolean logic in CMOS. works are provided in Section V. Finally, Section VI concludes
As the core of decimal arithmetic, previous works have the paper.
been conducted into majority-based parallel decimal adders
II. BACKGROUND
[7]–[12]. The existing majority logic based parallel decimal
adders mostly share the same structure, but differ from each Fig. 1 shows the block diagram of conventional 1-digit
other in the usage of binary adders. The 1-digit ripple carry BCD adder. The 1-digit BCD adder consists of 4-bit binary
adder (RCA) based BCD adders are proposed in [7], [8]. adder (ADD1), correction logic (CL) and 4-bit binary adder
However, these designs can be further optimized to reduce (ADD2). The binary adder (ADD1) adds the decimal number
hardware complexity. Carry flow adder (CFA) based and carry dA3:0 , dB3:0 and dCin to produce the binary sum bS3:0
lookahead adder (CLA) based BCD adders are presented in and output carry bCout . The CL circuit produces the cL3:0
[9], which show good performance. Moreover, [10] exploits and decimal output carry signals dCout for converting binary
novel binary adder to propose the efficient 1-digit BCD adder, sum bS3:0 to decimal sum dS3:0 . The cL3:0 = (0110)2 , if
reducing comprehensive consumption. In order to fully utilize dCout = 1 otherwise cL3:0 = (0000)2 . The binary adder
the majority gates, [11] and [12] rewrite the correction function (ADD2) produces decimal digit dS3:0 by adding bS3:0 and
for less majority gates. Different from the existing designs, we cL3:0 .
The theoretical delay required for generating 1-digit BCD
This work is supported by grants from National Science Foundation China adder dCout signal (dc (1)) and dS3:0 signal (d(1)) are given
(No. 61871216 and No. 61401197) and Six Talent Peaks Project in Jiangsu in (1) and (2).
Province (XYDXX-009).
T. Zhang and W. Liu are with College of Electronic and Information dc (1) = da1 + dcl (1)
Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing,
211106, China (emails: {ztt0416, liuweiqiang}@nuaa.edu.cn) d(1) = da1 + dcl + da2 (2)
V. Pudi is with the Hardware and Embedded Systems Lab, School of Com-
puter Science and Engineering, Nanyang Technological University, 639798, where da1 , dcl and da2 represent the delays required for single
Singapore (email: pudi@ntu.edu.sg) ADD1, CL and ADD2 blocks, respectively.

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Transactions on Circuits and Systems II: Express Briefs

4-bit Correction 4-bit

Binary Adder Logic Binary Adder
ADD1 (CL) ADD2 4-bit CL 4-bit
Binary Adder using Binary Adder
ADD1 CLA ADD2

Fig. 1: Block diagram of 1-digit BCD adder.

Fig. 3: Proposed block diagram of 1-digit BCD adder.

We are going to define the dCout in terms of majority gates.

For this, we rewrite (6) as follows:

dCout = bCout + (bS3:0 >= 10) + (bS3:0 >= 9)dCin

= bCout + (bS3:0 >= 10)
+ [bCout + (bS3:0 >= 9)]dCin (7)

The logic signals bCout + (bS3:0 >= 10) and bCout +

(bS3:0 >= 9) can be rewritten as [bCout + (bS3:0 >=
10)] · [bCout + (bS3:0 >= 9)] and [bCout + (bS3:0 >=
Fig. 2: Block diagram of 4-digit BCD adder. 10)] + [bCout + (bS3:0 >= 9)], respectively. By substituting
these values in dCout , we can rewrite the equation of dCout
as follows:
Similarly, the theoretical delay required for generating n- dCout
digit BCD adder output carry and decimal sum signals are = [bCout + (bS3:0 >= 10)] · [bCout + (bS3:0 >= 9)] +
given in (3) and (4). From Fig. 2, we can observe that the delay
required for the calculation of output carry signal (dc (n)) and [bCout + (bS3:0 >= 10) + bCout + (bS3:0 >= 9)]dCin (8)
decimal sum signal (d(n)). The delay path in Fig. 2 is marked The dCout in (8) is clearly in 3-input majority gate form
using the dotted line. with inputs bCout + (bS3:0 >= 10), bCout + (bS3:0 >= 9)
and dCin . We can write the dCout using the majority gate as
dc (n) = n(da1 + dcl ) (3) shown in (9).
d(n) = n(da1 + dcl ) + da2 (4)
dCout = M (bCout + (bS3:0 >= 10),
The delay dc (n) and d(n) are in multiples of n. This is due bCout + (bS3:0 >= 9), dCin ) (9)
to the computation of output carry in the form of ripple carry
style. The terms (bS3:0 >= 10) and (bS3:0 >= 9) are binary
The theoretical definition for calculating the ripple carry signals and we are calling these signals as decimal group
style output carry of the single digit output carry is given as generate and decimal group propagate signals. These two
follow: signals are represented as dG3:0 and dP3:0 , as shown in (10)
and (11), respectively.
dCout = bCout + (bS3:0 >= 10) (5)
dG3:0 = bCout + (bS3:0 >= 10) (10)
The recent proposed BCD design in [10] uses the output dP3:0 = bCout + (bS3:0 >= 9) (11)
carry shown in (5). The multi-digit BCD adder design in [10]
achieved low delay due to the parallel nature of 4-bit binary The proposed majority gate form of dCout using dG3:0 and
adder (ADD1). In this paper, we propose a new definition dP3:0 signals is given as follows:.
for the output carry in (5), which is employed into parallel
dCout = M (dG3:0 , dP3:0 , dCin ) (12)
implementation of the multi-digit BCD adders.
The dCout in (12) uses decimal group generate and decimal
group propagate signals for calculation. This is similar to CLA
III. P ROPOSED BCD A DDER D ESIGNS
method for the calculation of carry. Because of this, we are
The block diagram of parallel 1-digit BCD circuit is shown calling CL stage as CL-CLA. The cL3:0 signal is calculated
in Fig. 3. The design in [12] used the same block diagram for using the dCout as shown in (13).
the implementation of BCD adder but they have used AND- cL3:0 = {0, dCout , dCout , 0} (13)
OR gate based output carry as shown in (6).
The proposed dCout in (12) requires only 1 majority gate
after calculating the dG3:0 and dP3:0 signals. Fig. 4 shows the
dCout = bCout + (bS3:0 >= 10) + (bS3:0 == 9)dCin (6) majority gate diagram of proposed dCout in (12). We have

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Transactions on Circuits and Systems II: Express Briefs

Fig. 6: Proposed block diagram of multi-digit BCD adder.

Fig. 4: Proposed majority gate circuit for calculating dCout .

BCD adder. To verify the vadility, three different types of 4-bit

binary adder are employed into proposed designs, which are
RCA [7], CFA [9] and parallel binary adder (PBA) [10]. We
are calling these designs as RCA-BCD, CFA-BCD and PBA-
BCD, respectively.

A. Area Complexity
Fig. 5: Proposed majority gate circuit for calculating dC1 , dC2 , The I(n) represents the total majority gates required for
dC3 and dC4 . the proposed BCD adder. I(n) is the sum of Ia1 (n), Ia2 (n)
and Icl (n), where Ia1 (n), Ia2 (n) and Icl (n) represent total
majority gates required for all ADD1, ADD2 and CL-CLA
used the majority gate results presented in [10] for calculation blocks in n-digit BCD adder, respectively. The expressions
of dG3:0 , as shown in (14). for Ia1 (n) and Ia2 (n) are given as follow:
dG3:0 = bCout + bS3 · bS2 + bS3 · bS1 Ia1 (n) = nIa1 (1) (16)
= M (bCout , M (bCout , bS3 , 1), M (bS3 , bS2 , bS1 )) (14) Ia2 (n) = nIa2 (1) (17)
To save the area, we have calculated dP3:0 as follows: The Ia1 (1) and Ia2 (1) values depend upon the selection of
dP3:0 = bCout + (bS3:0 >= 9) binary adder for ADD1 and ADD2 blocks. In case of PBA-BCD
design, both Ia1 (1) and Ia2 (1) require 14 majority gates.
= bCout + (bS3:0 >= 10) + (bS3:0 == 9)
The proposed CL-CLA block first calculates all the dGi+3:i s
= dG3:0 + bS3 · bS0 (15) and dPi+3:i s. The calculation of each dGi+3:i and dPi+3:i
We can observe that the decimal group generate and decimal requires 5 majority gates, as shown in Fig. 4. Overall calcula-
group propagate signals are independent of decimal input tion of all dGi+3:i and dPi+3:i requires 5n majority gates
carry, which are produced parallelly in the multi-digit BCD for n-digit BCD adder. After calculation of dGi+3:i s and
adder. Consequently, all decimal group generate and decimal dPi+3:i s, calculation of dCi s requires n majority gates. The
group propagate signals of the multi-digit BCD adder share total majority gates required for the calculation Icl (n) are
the same delay. Fig. 5 shows the majority gate circuit for given as follow:
calculating the carries dC1 , dC2 , dC3 and dC4 using decimal Icl (n) = 5n + n = 6n (18)
group generate and decimal group propagate signals. The
delay required for calculating the dC4 in Fig. 5 is only the The generalized expression for calculating the area com-
delay of four majority gates, which can be achieved from the plexity of an n-digit BCD adder (in terms of majority gates)
proposed definition of dCout in (12). is given as follow:
The Fig. 6 shows the proposed block diagram of parallel
I(n) = n(Ia1 (1) + Ia2 (1)) + 6n (19)
4-digit BCD adder.
The area complexity for the n-digit RCA-BCD, CFA-BCD
IV. C OMPLEXITY A NALYSIS and PBA-BCD designs using (19) are given in (20)-(22),
The BCD adder uses the 4-bit binary adder for generation of respectively.
decimal digits. The performance of BCD adder also depends I(n) = 30n (20)
upon the selection of 4-bit binary adder. In this section, we
I(n) = 30n (21)
are going to derive the generalized expression for area and
delay complexity (in terms of the majority gate) of n-digit I(n) = 34n (22)

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TABLE I: Theoretical Area, Delay and ADP Comparisons for Different Types of n-digit BCD Adders
Type Area Delay ADP
Ia1 (n) Ia2 (n) Icl (n) I(n) da1 da2 dcl (n) d(n) I(n) × d(n)
Prop. RCA-BCD 12n 12n 6n 30n 7 7 3+n 17 + n 30n2 + 510n
Prop. CFA-BCD 12n 12n 6n 30n 7 7 3+n 17 + n 30n2 + 510n
Prop. PBA-BCD 14n 14n 6n 34n 5 5 3+n 13 + n 34n2 + 442n
PBA-BCD [10] 16n 10n 3n 29n 5 4 7n − 5 7n + 4 203n2 + 116n
BCD [11] 12n 10n 3n 25n 5 2 7n − 5 7n + 2 175n2 + 50n
CFA-BCD [12] 16n 12n 6n 34n 5 4 2 + 2n 2n + 11 68n2 + 374n

B. Delay Complexity
The total delay required for the n-digit BCD adder is the
sum of delay required for ADD1 (da1 ), ADD2 (da2 ) and CL-
CLA (dcl (n)) circuits as shown in Fig. 6. All ADD1 blocks
in n-digit BCD adder can calculate in parallel. The da1 , da2
and dcl (n) represent the delay of 1-digit ADD1, ADD2 and
n-digit CL-CLA blocks, respectively. The delay da1 and da2
depend upon the selection of 4-bit binary adder. In case of
proposed PBA-BCD design, both of the da1 and da2 values
are 5 majority gates. Fig. 7: Proposed layout of 1-digit PBA based BCD adder.
The delay dcl (n) of n-digit BCD adder is the sum of delay
required for calculation of dGi+3:i , dPi+3:i and all dCout s, as
shown in Fig. 6. The delay required for dGi+3:i and dPi+3:i
terms is 3 majority gates, as shown in Fig. 4. An n-digit BCD
adder requires delay of n majority gates for calculation of all
dCout s after calculation of dGi+3:i s and dPi+3:i s, as shown
in Fig. 4. The delay term dcl (n) is given as follow:
dcl (n) = 3 + n (23)
The generalized expression for calculating the delay com-
plexity of an n-digit BCD adder (in terms of majority gates)
is given as follow:
d(n) = da1 + da2 + 3 + n (24)
The delay complexity for an n-digit RCA-BCD, CFA-BCD Fig. 8: Proposed layout of 4-digit PBA based BCD adder.
and PBA-BCD designs using (24) are given in (25)-(27),
respectively.
d(n) = 17 + n (25)
d(n) = 17 + n (26)
d(n) = 13 + n (27)

V. E XPERIMENTAL R ESULTS AND C OMPARISONS

Table I presents the theoretical comparisons of area, delay
and ADP of BCD adder circuits in terms of majority gates
for proposed designs and designs in [10]–[12]. From Table I,
we can observe that the proposed designs require less delay Fig. 9: Proposed layout of 1-digit PBA-BCD adder based on
compared with the best existing designs. Theoretically, our n- the 2DDWAVE clocking scheme (Area: 1.56µm2 , Delay: 4.25
digit PBA-BCD adder design requires less than 80% in delay clocks).
and ADP compared with the design in [10], about 50% in
delay and ADP compared with the design in [12].
Multi-layer design method is adopted in order to be consis- diagrams of proposed 1-digit and 4-digit BCD adder using
tent with designs in [10]–[12], for the sake of fair and valid QCADesigner tool (version 2.0.3). Besides, in order to verify
comparisons and evaluations. Fig. 7 and Fig. 8 show the layout that our proposed BCD adder can be efficiently implemented

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Transactions on Circuits and Systems II: Express Briefs

less delay, 51% less ADP and 52% less CostQCA compared
with designs in [10]–[12]. For the 1-digit case, the 2DDWAVE
clocking scheme introduces slightly more clocking delay and
also occupies slightly larger area. However, the results are
still consistent with that using the conventional clocking
scheme. Obviously, due to the proposed new formulations as
presented in the previous sections, when the scale of the design
increases, our proposed approach shows excellent performance
in terms of delay. Consequently, overall designs have achieved
substantial savings.
Fig. 10: Simulation result of proposed 1-digit PBA-BCD adder
based on the 2DDWAVE clocking scheme. VI. C ONCLUSIONS
In this paper, we have developed a general methodology
TABLE II: Comparisons of proposed and other designs ob- to obtain low-delay for multi-digit BCD adders in QCA. The
tained from QCADesigner methodology has been applied to the RCA, CFA, PBA based
BCD adders to obtain the low-delay. Theoretically, our n-digit
Approach Area Delay ADP CostQCA
PBA-BCD adder design requires 50% less delay and ADP
(µm2 ) (Clocks) (µm2 × Clocks) (105 )
compared with the design in [10]–[12]. We have validated
Prop. RCA-BCD1 1.01 4 4.04 3.47 our designs using the QCADesigner tool. From QCADesigner
Prop. RCA-BCD4 5.68 7 39.76 168.71 layout results, 8-digit PBA-BCD adder requires at least 38%
Prop. RCA-BCD8 16.09 11 176.99 1664.03 less delay compared with the existing best designs.
Prop. CFA-BCD1 1.52 3 34 5.70 3.05 R EFERENCES
Prop. CFA-BCD4 8.14 6 34 54.94 156.88 [1] L. K. Wang, M. J. Schulte, J. D. Thompson, and N. Jairam, “Hardware
Prop. CFA-BCD8 21.65 10 34 232.73 1589.25 designs for decimal floating-point addition and related operations,” IEEE
Transactions on Computers, vol. 58, no. 3, pp. 322-335, 2009.
Prop. PBA-BCD1 0.88 3 34 3.30 4.53 [2] S. Shankland, “IBMs POWER6 gets help with math, multimedia,” in
ZDNet News, 2006.
Prop. PBA-BCD4 3.82 5 14 20.05 135.15
[3] X. Cui, W. Dong, W. Liu, E. E. Swartzlander Jr, and F. Lombardi, “High
Prop. PBA-BCD8 11.71 7 14 84.89 1120.30 performance parallel decimal multipliers using hybrid BCD codes,” IEEE
Transactions on Computers, vol. 66, no. 12, pp. 1994-2004, 2017.
PBA-BCD1 [10] 0.89 3 3.12 3.08 [4] K. Walus and G. A. Jullien, “Design tools for an emerging SoC technol-
PBA-BCD4 [10] 3.96 8 14 32.67 288.93 ogy: quantum-dot cellular automata,” in Proceedings of the IEEE, vol.
94, no. 6, pp. 1225-1244, 2006.
PBA-BCD8 [10] 12.32 15 14 187.75 4091.51 [5] M. Vacca, M. Graziano, J. Wang, F. Cairo, and G. Causapruno, NanoMag-
net Logic: An Architectural Level Overview. Springer Berlin Heidelberg,
BCD1 [11] 0.76 3 2.28 1.43 2014.
BCD4 [11] 3.68 8 14 30.36 172.32 [6] A. Khitun and K. L. Wang, “Nano scale computational architectures with
spin wave bus,” Superlattices & Microstructures, vol. 38, no. 3, pp. 184-
BCD8 [11] 11.44 15 14 174.46 2351.67 200, 2005.
[7] M. Taghizadeh, M. Askari, and K. Fardad, “BCD computing structures
CFA-BCD1 [12] 1.37 3 12 4.80 3.71
in quantum-dot cellular automata,” in Proc. International Conference on
CFA-BCD4 [12] 6.68 6 34 45.09 293.81 Computer and Communication Engineering, 2008, pp. 1042-1045.
[8] F. Kharbash and G. M. Chaudhry, “The design of quantum-dot cellular
CFA-BCD8 [12] 14.95 11 34 175.66 3084.47 automata decimal adder,” in Proc. IEEE International Conference on
Multitopic, 2008, pp. 71-75.
[9] W. Liu, L. Lu, M. O’Neil, and E. E. Swartzlander Jr, “Cost-efficient
decimal adder design in quantum-dot cellular automata,” in Proc. IEEE
with different clocking schemes, PBA based BCD adder is International Symposium on Circuits and Systems, 2011, pp. 1347-1350.
designed by applying the 2DDWAVE mechanism [13] (Fig. [10] G. Cocorullo, P. Corsonello, F. Frustaci, and S. Perri, “Design of efficient
BCD adders in quantum-dot cellular automata,” IEEE Transactions on
9). The simulation result is shown in Fig. 10. Circuits & Systems II Express Briefs, vol. 64, no. 5, pp. 575-579, 2017.
The following parameters have been used for coherence [11] D. Abedi and G. Jaberipur, “Decimal full adders specially designed for
quantum-dot cellular automata,” IEEE Transactions on Circuits & Systems
vector simulation engine: Number of Samples: 128000; Con- II Express Briefs, vol. 65, no. 1, pp. 106-110, 2017.
vergence Tolerance: 0.00001; Radius of Effect: 55 nm. The [12] D. Ajitha, K. Ramanaiah, and V. Sumalatha, “An enhanced high-speed
rest of parameters are set as the default values. multi-digit BCD adder using quantum-dot cellular automata,” Journal of
Semiconductors, vol. 38, no. 2, pp. 38-46, 2017.
Table II presents comparisons of area, delay, ADP and QCA [13] A. Roohi, R. Zand, S. Angizi, and R. F. Demara, “A parity-
cost function CostQCA (defined in [14], where k is 2, l is 2, preserving reversible QCA gate with self-checking cascadable resilien-
p is 2) of proposed designs with designs in [10]–[12]. The cy,” IEEE Transactions on Emerging Topics in Computing, 2018, DOI:
10.1109/TETC.2016.2593634.
power consumption of the designs can be further analyzed [14] W. Liu, L. Lu, M. O’Neill, and E. E. Swartzlander, “A first step
by the method proposed in [15]. The proposed PBA-BCD toward cost functions for quantum-dot cellular automata designs,” IEEE
adders require only 0.88 µm2 and 11.71 µm2 area for 1- Transactions on Nanotechnology, vol. 13, no. 3, pp. 476-487, 2014.
[15] F. S. Torres, R. Wille, P. Niemann, and R. Drechsler, “An energy-
digit and 8-digit BCD adders, respectively; the delay required aware model for the logic synthesis of quantum-dot cellular automata,”
are 3.75 and 7.25 clocks, respectively, as shown in Table II. IEEE Transactions on Computer-Aided Design of Integrated Circuits and
The proposed 8-digit PBA-BCD adder achieves at least 38% Systems, 2018, DOI: 10.1109/TCAD.2018.2789782.

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