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KT14203 Sem 2 20132014 Test 1 - Solution

This document contains a midterm exam for a computer architecture and organization course. [1] It includes multiple choice and short answer questions testing knowledge of basic computer functions, instruction set formats, interrupt classes, memory types, cache mapping, and cache organization. [2] Questions cover topics such as program counter size, addressable memory units, advantages of SRAM and DRAM, cache line size, tag and set values, mapping addresses to cache lines, and differences between direct mapping and set associative caches. [3]

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309 views3 pages

KT14203 Sem 2 20132014 Test 1 - Solution

This document contains a midterm exam for a computer architecture and organization course. [1] It includes multiple choice and short answer questions testing knowledge of basic computer functions, instruction set formats, interrupt classes, memory types, cache mapping, and cache organization. [2] Questions cover topics such as program counter size, addressable memory units, advantages of SRAM and DRAM, cache line size, tag and set values, mapping addresses to cache lines, and differences between direct mapping and set associative caches. [3]

Uploaded by

b2uty77_593619754
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Solution Mid Test 1

SEKOLAH KEJURUTERAAN DAN TEKNOLOGI MAKLUMAT


KT14203 COMPUTER ARCHITECTURE AND ORGANIZATION
MIDTERM (35 marks) 1 hour 30 minutes
---------------------------------------------------------------------------------------------------------

Question 1 (15 marks)

a) Define and explain four basic functions of a computer. (4 marks)


- Data processing
- Data storage
- Data movement
- Control
b) Consider a hypothetical machine with instruction set formats as given in Figure 1. What is the
size of:
i. Program Counter (PC)?
16 bits [1].
ii. Instruction Register (IR)?
24 bits [1].
iii. Addressable memory units?
216 = 65536 Bytes [2].
(4 marks)

Figure 1

c) There are four different classes of interrupts, explain two of them. (4 marks)
Any two of the following, 2 marks each:

1
Solution Mid Test 1

d) Two types of semiconductor memory are Static and Dynamic Random Access Memory
(SRAM and DRAM).
i. Give one common feature of SRAM and DRAM. (1 mark)
Power must be continuously supplied to the memory to preserve the bit values.
ii. Provide one advantage each of SRAM and DRAM.
(2 marks)
SRAM Faster
DRAM
- Simpler to build, smaller
- More dense (smaller cells = more cells per unit area).
- Less expensive.

Question 2 (20 marks)

A 2-way set associative cache has 4096 lines and a total size of 32 Kbytes. The main memory size
is 2 Mbytes.
a. How many bits are needed for addressing a space in the memory? (2 marks)
Memory = 2 MB

= 2 x 220 B [1]

= 21 x 220 B

= 221

address = 21 bit [1]

2
Solution Mid Test 1

b. Find the Tag, Set and Word value. (6 marks)


cache lines = 4096 lines Word = 32 Kb / 4096 lines [1]

= 212 [1] = (25 x 210)/ 212

sets = 212/21 = 23

sets = 211 [1] word = 3 bits [1]

Tag Set Word Tag = 21 11 3 [1]

= 7 bit. [1 M]
7 11 3

c. For hexadecimal main memory address 1EF34A, show the Tag, Set and Word values by
using the address format in (a) and (b). (5 marks)
1 E F 3 4 A
1 1110 1111 0011 0100 1010 [1]
Tag Set Word
111 1011 11001101001 010 [1]
110 0110 1001
7B 669 2
[1 M] [1 M] [1 M]

d. Give two other addresses that will be mapped into the same set as (c). (2 marks)
Any address where set = 669, 0 <= tag <= 7F and 0 <= word <= 7

e. Other cache mapping is known as direct mapping.


i) Describe direct mapping and its advantage. (2 marks)
Maps each block of main memory into only one possible cache line.
Advantage = simple.

ii) What is the difference between direct mapping and set associative cache? (1 mark)
Set associative permits each main memory block to be loaded into any line in a set of
the cache.

iii) Explain one advantage of using a set associative cache than using a direct mapped
cache. (2 marks)
A memory block can be stored in more than one line in a cache, thus reduce the
disadvantage of direct mapping where block replacement will be reduced.

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