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Unit Iii: Design With Msi Devices

This document discusses decoders and multiplexers. It begins by defining a decoder as a combinational circuit that converts binary inputs to unique outputs. It then discusses applications of decoders such as memory addressing and instruction decoding. The document proceeds to provide truth tables and diagrams for 3-to-8 line decoders and 2-to-4 line decoders with enable inputs. It also discusses using decoders to implement combinational logic functions. The document then defines a multiplexer as a circuit that selects one of many inputs to output. It provides diagrams of 4-to-1 line multiplexers and discusses implementing functions using multiplexers. Finally, it introduces three-state gates that can exhibit high impedance and discusses using three-state gates with

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Arjun Seshadhry
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161 views16 pages

Unit Iii: Design With Msi Devices

This document discusses decoders and multiplexers. It begins by defining a decoder as a combinational circuit that converts binary inputs to unique outputs. It then discusses applications of decoders such as memory addressing and instruction decoding. The document proceeds to provide truth tables and diagrams for 3-to-8 line decoders and 2-to-4 line decoders with enable inputs. It also discusses using decoders to implement combinational logic functions. The document then defines a multiplexer as a circuit that selects one of many inputs to output. It provides diagrams of 4-to-1 line multiplexers and discusses implementing functions using multiplexers. Finally, it introduces three-state gates that can exhibit high impedance and discusses using three-state gates with

Uploaded by

Arjun Seshadhry
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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UNIT III

DESIGN WITH MSI DEVICES


DECODERS

A decoder is a combinational circuit that converts binary information


from n input lines to an 2n unique output lines.

Applications:

• Microprocessor memory system: selecting different banks of memory.


• Microprocessor I/O: Selecting different devices.
• Microprocessor instruction decoding: Enabling different functional
units.
• Memory: Decoding memory addresses (e.g. in ROM).
3-to-8-line DECODER
3-to-8-line DECODER Truth Table

Outputs
Binary Inputs D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

If the input corresponds to minterm mi then the decoder ouputi


will be the single asserted output.
2-to-4-line DECODER with Enable Input
The decoder is enabled when E = 0. The output whose value = 0 represents the
minterm is selected by inputs A and B.
The decoder is disabled when E = 1 D0 … D3 = 1
A Decoder with enable input is called a decoder/demultiplexer. Demultiplexer
receives information from a single line and directs it to the output lines.
Complemented outputs
A 4 x 16 DECODER

• When w = 0, the top decoder is enabled and the bottom is disabled.


Top decoder generates 8 minterms 0000 to 0111, while the bottom
decoder outputs are 0’s.
• When w = 1, the top decoder is disabled and the bottom is enabled.
Bottom decoder generates 8 minterms 1000 to 1111, while the top
decoder outputs are 0’s.
Combinational Logic (Full-Adder) using Decoder

( x, y, z ) = Σ(1,2,4,7)

( x, y, z ) = Σ(3,5,6,7)
MULTIPLEXERS/DATA SELECTORS
A multiplexer is a combinational circuit that selects one of many
input lines (2n) and steers it to its single output line. There
are (2n) and n selection lines whose bit combinations determine
which input is selected.
4-to-1LINE MULTIPLEXER DESIGN
In general, a 2n–to–1-line multiplexer is constructed from an
n–to 2n decoder by adding to it 2n lines, one to each AND gate.

1
0
QUADRUPLE 4-to-1LINE MULTIPLEXER
Function implementation using multiplexers
Function with n variables and multiplexer with n – 1 selection
F ( x, y, z ) = Σ(1,2,6,7)
Input variables x, y: Selection lines, S1 and S0
Variable z: Date line 0
Data lines 1,2,3: z ' , 0, 1
OR gates
are included
Function implementation using 4x1multiplexer

z’

0
1

x
y
Function implementation using 8x1multiplexer
F ( A, B, C , D) = Σ(1,3,4,11,12,13,14,15)

1. Complete the truth table from the SOP.


2. The first n – 1 variables in the table are applied to the
selection inputs of the multiplexer.
3. For each combination of the selection variables, we evaluate
the output as a function of the last variable.
4. Apply these values to the data input in proper order.
Function implementation using 8x1 MUX
note the order of input lines
Three State Gates
A three-state gate is a digital circuit that exhibits three states: 0, 1
and a high-impedance (high z state). The high impedance state
behaves as an open circuit.

Because of this feature (high z state), a large number of three-state


gate outputs can be connected to form a common line without
endangering load effects.
Multiplexers with Three State Gates
When EN = 0, decoder outputs are zero,
and the bus lines are in high z state.
When EN = 1, one of the three-state buffers
will be active depending on the binary value in
the select inputs of the decoder.
Note that the two output
connections can not be done
with other gates.

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