DSP Lab Manual
DSP Lab Manual
CONTENTS
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Department of Electronics and Communication Engineering Digital Signal Procesing Lab
EXPERIMENT NO:1
AIM:
To write a program for low pass filter and high pass filter and to observe its output
using MATLAB7.0
SOFTWARE REQUIRED:
MATLAB 7.0
PROGRAM:-
%program to design low pass filter
clc
n=input('enter the order of filter');
f=input('enter frequency');
disp(n);
disp(f);
[b,a]=butter(n,f,'low','s');
w=[0:200:1200*pi];
h=freqs(b,a,w);
gain=20*log(abs(h));
subplot(2,2,1);
stem(w/2*pi,gain);
xlabel('frequency');
ylabel('amplitude');
title('lpf');
%program to design high pass filter
n=input('enter the order of filter');
f=input('enter frequency');
disp(n);
disp(f);
[b,a]=butter(n,f,'high','s');
w=[0:200:1200*pi];
h=freqs(b,a,w);
gain=20*log(abs(h));
subplot(2,2,2);
stem(w/2*pi,gain);
xlabel('frequency');
ylabel('amplitude');
title('hpf');
PROCEDURE:
1.Switch on the computer system and enter into MATLAB7.0
2.Create a new M-file from File menu and write the program.
3.Save the program in one of thr Directory.
4.Debug and run the program,if there are errors then correct them,save and run it again.
5.Observe the output waveform.
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RESULT:
The program for low pass and high pass filters is executed and the corresponding
waveforms are plotted in the graph.
OUTPUT:
Enter the order of the filter : 3
Enter the frequency : 3000Hz
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Department of Electronics and Communication Engineering Digital Signal Procesing Lab
EXPERIMENT NO: 2
THEORY:
The TMS320C6713s high performance CPU and rich peripheral set are tailored for
multichannel audio applications such as broadcast and recording mixing, home and large
venue audio decoders, and multi-zone audio distribution. The TMS320C6713 device is
based on the high-performance advanced VelociTI very-long-instruction-word (VLIW)
architecture developed by Texas Instruments (TI). The VelociTI architecture provides
sample performance to decode a variety of existing digital audio formats and the
flexibility to add future formats.
1.System I/O
Figure 1 shows a block diagram of a digital surround receiver. Figure 2 generalizes that to
many high performance multichannel audio systems. The TMS320C6713s peripheral set
enables ease of connection to the major elements of these systems. The peripheral set
includes:
Two McASPs that provide simple cost effective, connectivity to multiple serial digital
audiostreams
Two Inter-IC (I2C) buses for connection to serial ROMs or to control other system
interfacedevices like user I/O
A dedicated general-purpose input/output (GPIO) module to provide direct control lines
system components, eliminating much of the glue logic in many designs/
2.C67x CPU and Instruction Set
The TMS320C6713 floating-point digital signal processor uses the C67x VelociTI
advancedvery-long instruction words (VLIW) CPU. The CPU fetches (256 bits wide) to
supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI
VLIW
architecture also features variable-length execute packets; these variable-length execute
packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW
architectures.
Operating at 225 MHz, the TMS320C6713 delivers up to 1350 million floating-point
operationsper second (MFLOPS), 1800 million instructions per second (MIPSfixed-
floating-point multipliers up to 450 million multiply-accumulate operations per second
(MMACS).
2.1 Functional Units
CPU features eight of functional units supported by 32 32-bit general purpose registers.
This data path is divided into two symmetric sides consisting of 16 registers and 4
functional units each. Additionally, each side features a data bus connected to all the
registers on the other side, by which the two sets of functional units can access data from
the register files on the opposite side.
2.2 Fixed and Floating Point Instruction Set
The C67x CPU executes the C62x integer instruction set. In addition, the C67x CPU
natively supports IEEE 32-bit single precision and 64-bit double precision floating point.
In addition to
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C62x fixed-point instructions, six out of the eight functional units also execute floating-
point instructions: two multipliers, two ALUs, and two auxiliary floating point units. The
remaining twofunctional units support floating point by providing address generation .
C67x CPU adds to the C62x instruction set. This provides 128-bits of data bandwidth per
cycle.
This double-word load capability allows multiple operands to be loaded into the register
file for 32-bit floating point instructions. Unlike other floating point architectures the
C67x hadindependent control of the its two floating point multipliers and its two the
floating point ALUs.
This enables the CPU to operate on a broader mix of floating point algorithms rather than
to be tied to the typical multiply-accumulate oriented functions.
2.3 Load/Store Architecture
Another key feature of the C67x CPU is the load/store architecture, where all instructions
operate on registers (as opposed to directly on data in memory). Two sets of data-
addressing units are responsible for all data transfers between the register files and the
memory. The data address driven by the .D units allows data addresses generated from
one register file to be usedT CPU features eight of functional units supported by 32 32-bit
general purpose registers.
This data path is divided into two symmetric sides consisting of 16 registers and 4
functional units each. Additionally, each side features a data bus connected to all the
registers on the other side, by which the two sets of functional units can access data from
the register files on the opposite side.
2.4 Fixed and Floating Point Instruction Set
The C67x CPU executes the C62x integer instruction set. In addition, the C67x CPU
natively
supports IEEE 32-bit single precision and 64-bit double precision floating pointC62x
fixed-point instructions, six out of the eight functional units also execute floating-point
instructions: two multipliers, two ALUs, and two auxiliary floating point units. The
remaining two functional units support floating point by providing address generation for
the 64-bi.t
C67x CPU adds to the C62x instruction set. This provides 128-bits of data bandwidth per
cycle.
This double-word load capability allows multiple operands to be loaded into the register
file for 32-bit floating point instructions. Unlike other floating point architectures the
C67x had independent control of the its two floating point multipliers and its two the
floating point ALUs.
This enables the CPU to operate on a broader mix of floating point algorithms rather than
to be tied to the typical multiply-accumulate oriented functions.
2.5 Load/Store Architecture
Another key feature of the C67x CPU is the load/store architecture, where all instructions
operate on registers (as opposed to directly on data in memory). Two sets of data-
addressing units are responsible for all data transfers between the register files and the
memory. The data address driven by the .D units allows data addresses generated from
one register file to be usedhe
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3.Two-Level Cache
Cache Overview
The TMS320C6713 device utilizes a highly efficient two-level real-time cache for
internal program and data storage. The cache delivers high performance without the cost
of large arrays of on-chip memory. The efficiency of the cache makes low cost, high-
density external memory, such as SDRAM, as effective as on-chip memory.
Interrupt Handling
Interrupt handling is an important part of DSP operation. It is crucial that the DSP be able
to receive and handle interrupts while maintaining real-time operation. In typical
applications,interrupt frequency has not increased in proportion to the increase in device
operation frequency. As processing speeds have increased, latency requirements have not.
The TMS320C6713 is capable of servicing interrupts with a latency of a fraction of a
microsecond when the service routine is located in external memory. By configuring the
L2memory blocks as memory-mapped SRAM, or by using the L2 memory mapped space,
it is possible to lock critical program and data sections into internal memory. This is ideal
for situations such as interrupts and OS task switching. By locking routines that need to
be performed in minimal time, the microsecond delay for interrupts is reduced.
Real Time I/O
Peripherals are a feature of most DSP systems that can take advantage of the memory-
mapped L2 RAM. Ty ical processors require that peripheral data first be placed in
external memory before it can be accessed by the CPU. The TMS320C6713 can maintain
data buffers in on-chip memory, rather than in off-chip memory, providing a higher data
throughput to peripherals. This increases performance when using on-chip McASPs, the
HPI, or external peripherals. The EDMA can be used to transfer data directly into mapped
L2 space while the CPU processes the data. This increases performance since the CPU is
not stalled while fetching data from slow
external memory or directly from the peripheral. Using this method for transferring data
also minimizes EMIF activity, which is crucial as data rates or the number of peripherals
increase.
The McASP is a serial port optimized for the needs of multichannel audio applications.
With two McASP peripherals, the TMS320C6713 device is capable of supporting two
completely independent audio zones simultaneously.
RESULT:
The TMS320C6713 peripheral set enables the device to directly interface to a variety of
components in these systems. The McASPs provide highly-flexible direct interconnect to
the digital audio streams as well as high performance audio data converters. The two-
level cache enables efficient data management and real time I/O while hiding
performance issues associated with low cost external SDRAM. The TMS320C6713 DSP
device architecture is ideally suited for multichannel, high-performance audio
applications.
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Department of Electronics and Communication Engineering Digital Signal Procesing Lab
LINEAR CONVOLUTION
AIM:-
To write a program for Linear Convolution and to observe its output using MATLAB 7.0
SOFTWARE REQUIRED:-
MATLAB 7.0
PROGRAM:-
clc;
clear all;
close all;
x=input('enter x sequence:');
n1=length(x);
h=input('enter h sequence:');
n2=length(h);
y=conv(x,h);
n=0:1:n1+n2-2;
stem(n,y);
xlabel(n);
ylabel(y);
title('linear convolution');
PROCEDURE:-
1.Switch on the computer system and enter into MATLAB7.0
2.Create a new M-file from File menu and write the program.
3.Save the program in one of thr Directory.
4.Debug and run the program,if there are errors then correct them,save and run it again.
5.Observe the output waveform.
RESULT:-
The program for linear convolution is executed,output values are obtained and the
corresponding waveforms are plotted in the graph.
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OUTPUT:-
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Department of Electronics and Communication Engineering Digital Signal Procesing Lab
LINEAR CONVOLUTION
AIM:-
To write a program for linear convolution,find the result and plot the graph.
SOFTWARE REQUIRED:-
Code Composer Studio 3.0V
PROGRAM:-
#include<stdio.h>
int y[5];
main()
{
int i,x[10],h[10],j;
for(i=0;i<10;i++)
{
x[i]=0;
h[i]=0;
}
printf("\nenter x values");
for(i=0;i<3;i++)
scanf("%d",&x[i]);
printf("\nenter n values");
for(i=0;i<3;i++)
scanf("%d",&h[i]);
for(i=0;i<5;i++)
{
y[i]=0;
for(j=i;j>=0;j--)
y[i]=y[i]+x[j]*h[i-j];
}
printf("\noutput values are :");
for(i=0;i<5;i++)
printf(" %d ",y[i]);
}
PROCEDURE:-
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5) Start a new project using project new pull down menu and save it in a separate
directory.
6) Create a new source file to the file menu and then type linear convolution
program and save it.
7) Add the source file to the source folder using add files to project pull down
menu.
8) Add the linker command file hello.cmd to the source folder.
9) Add the rts file rts6700.lib to library folder.
10) Compile the program using the project compile pull down menu.
11) Build the program using project build pull down menu if there is no errors.
12) Load the program in program memory of dsp chip using the file load program
pull down menu.
13) Run the program using debug run.
14) Observe the output graph by using view graph time/freq menu & plot it on the
graph paper.
RESULT: The program for linear convolution has been verified and output graphs are
Plotted.
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OUTPUT:
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Department of Electronics and Communication Engineering Digital Signal Procesing Lab
CIRCULAR CONVOLUTION
AIM:-
To write a program for Circular Convolution and to observe its output using MATLAB
7.0
SOFTWARE REQUIRED:-
MATLAB 7.0
PROGRAM:-
%circular convolution
clc;
x=input('enter x elements');
y=input('enter y elements');
n1=length(x);
n2=length(y);
if(n1>=n2)
n=n1;
z1=zeros(1,n-n2)
x1=x;
y1=[y z1];
else
n=n2;
z2=zeros(1,n-n1);
x1=[x z2]
y1=y;
end
for i=1:n
u(i,1)=x1(i);
end
for i=2:n
for j=2:n
u(1,i)=u(n,i-1);
u(j,i)=u(j-1,i-1);
end
end
out=u*shiftdim(y1);
e=0:1:n-1;
stem(e,out);
xlabel('e');
ylabel('output sequence');
title('circular convolution');
PROCEDURE:-
1.Switch on the computer system and enter into MATLAB7.0
2.Create a new M-file from File menu and write the program.
3.Save the program in one of thr Directory.
4.Debug and run the program,if there are errors then correct them,save and run it again.
5.Observe the output waveform.
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RESULT:-
The program for circular convolution is executed, output values are obtained and the
corresponding waveforms are plotted in the graph.
OUTPUT:-
Enter the elements of X [1 1 1 1]
Enter the elements of Y [1 1 1]
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Department of Electronics and Communication Engineering Digital Signal Procesing Lab
EXPERIMENT NO:4(B)
CIRCULAR CONVOLUTION
AIM:-
To write a program for Circular Convolution and observe the corresponding waveforms.
SOFTWARE REQUIRED: -
Code Composer Studio 3.0V
PROGRAM:-
#include<stdio.h>
int m,n,x[10],h[10],y[10],i,j,k,x2[10],a[10];
void main()
{
for(i=0;i<10;i++)
{
x[i]=0;
h[i]=0;
}
printf("enter m value\t");
scanf("%d",&m);
printf("enter n value\t");
scanf("%d",&n);
printf("enter x[m] values\t");
for(i=0;i<m;i++)
scanf("%d",&x[i]);
printf("enter h[n] values\t");
for(i=0;i<n;i++)
scanf("%d",&h[i]);
if((m-n)!=0)
{
if(m>n)
{
for(i=n;i<m;i++)
h[i]=0;
n=m;
}
else
{
for(i=m;i<n;i++)
x[i]=0;
m=n;
}
}
y[0]=0;
a[0]=h[0];
for(j=1;j<n;j++)
a[j]=h[n-j];
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for(i=0;i<n;i++)
y[0]+=x[i]*a[i];
for(k=1;k<n;k++)
{
y[k]=0;
for(j=1;j<n;j++)
x2[j]=a[j-1];
x2[0]=a[n-1];
for(i=0;i<n;i++)
{
a[i]=x2[i];
y[k]+=x[i]*x2[i];
}
}
for(i=0;i<n;i++)
printf("y[%d]= %d\n",i,y[i]);
}
PROCEDURE:-
RESULT:- The program for circular convolution has been verified and output graphs
are plotted.
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Department of Electronics and Communication Engineering Digital Signal Procesing Lab
SOFTWARE REQUIRED:-
MATLAB 7.0
PROGRAM:-
fs=1000;
t=0:1/fs:1-1/fs;
x=cos(2*pi*100*t)+randn(size(t));
n=length(x);
xdft=fft(x);
xdft=xdft(1:n/2+1);
psdx=(1/fs*n)*abs(xdft).^2;
psdx(2:end-1)=2*psdx(2:end-1);
freq=0:fs/length(x):fs/2;
plot(freq,10*log(psdx));
grid on
title('p');
xlabel('freq');
ylabel('power');
PROCEDURE:-
1.Switch on the computer system and enter into MATLAB7.0
2.Create a new M-file from File menu and write the program.
3.Save the program in one of thr Directory.
4.Debug and run the program,if there are errors then correct them,save and run it again.
5.Observe the output waveform.
RESULT:-
The program for power spectral density is executed and the corresponding waveforms are
plotted in the graph.
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OUTPUT:-
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Department of Electronics and Communication Engineering Digital Signal Procesing Lab
EXPERIMENT NO:5(B)
EXPERIMEN
T NO
POWER SPECTRAL DENSITY
:5
AIM:-
To verify the Power Spectral Density using DSP kit.
SOFTWARE REQUIRED:-
Code Composer Studio 3.0V
PROGRAM:-
//PSD MAIN
#include <math.h>
#define PTS 128 //# of points for FFT
#define PI 3.14159265358979
typedef struct {float real,imag;} COMPLEX;
void FFT(COMPLEX *Y, int n); //FFT prototype
float iobuffer[PTS]; //as input and output buffer
float x1[PTS],x[PTS]; //intermediate buffer
short i; //general purpose index variable
short buffercount = 0; //number of new samples in iobuffer
short flag = 0; //set to 1 by ISR when iobuffer full
float y[128];
COMPLEX w[PTS]; //twiddle constants stored in w
COMPLEX samples[PTS]; //primary working buffer
main()
{
float j,sum=0.0 ;
int n,k,i,a;
for (i = 0 ; i<PTS ; i++) // set up twiddle constants in w
{
w[i].real = cos(2*PI*i/(PTS*2.0)); //Re component of twiddle constants
w[i].imag =-sin(2*PI*i/(PTS*2.0)); /*Im component of twiddle constants*/
}
for(i=0,j=0;i<PTS;i++)
{ x[i] = sin(2*PI*5*i/PTS);// Signal x(Fs)=sin(2*pi*f*i/Fs);
samples[i].real=0.0;
samples[i].imag=0.0;
}
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for(n=0;n<PTS;n++)
{
sum=0;
for(k=0;k<PTS-n;k++)
{
sum=sum+(x[k]*x[n+k]);// Auto Correlation R(t)
}
iobuffer[n] = sum;
}
//END OF MAIN
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do
{
num_stages +=1;
i = i*2;
}while (i!=N);
leg_diff = N/2; //difference between upper&lower legs
step = (PTS*2)/N; //step between values in twiddle.h // 512
for (i = 0;i < num_stages; i++) //for N-point FFT
{
index = 0;
for (j = 0; j < leg_diff; j++)
{
for (upper_leg = j; upper_leg < N; upper_leg += (2*leg_diff))
{
lower_leg = upper_leg+leg_diff;
temp1.real = (Y[upper_leg]).real + (Y[lower_leg]).real;
temp1.imag = (Y[upper_leg]).imag + (Y[lower_leg]).imag;
temp2.real = (Y[upper_leg]).real - (Y[lower_leg]).real;
temp2.imag = (Y[upper_leg]).imag - (Y[lower_leg]).imag;
(Y[lower_leg]).real = temp2.real*(w[index]).real
-temp2.imag*(w[index]).imag;
(Y[lower_leg]).imag = temp2.real*(w[index]).imag
+temp2.imag*(w[index]).real;
(Y[upper_leg]).real = temp1.real;
(Y[upper_leg]).imag = temp1.imag;
}
index += step;
}
leg_diff = leg_diff/2;
step *= 2;
}
j = 0;
for (i = 1; i < (N-1); i++) //bit reversal for resequencing data
{
k = N/2;
while (k <= j)
{
j = j - k;
k = k/2;
}
j = j + k;
if (i<j)
{
temp1.real = (Y[j]).real;
temp1.imag = (Y[j]).imag;
(Y[j]).real = (Y[i]).real;
(Y[j]).imag = (Y[i]).imag;
(Y[i]).real = temp1.real;
(Y[i]).imag = temp1.imag;
}
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Department of Electronics and Communication Engineering Digital Signal Procesing Lab
}
return;
}
PROCEDURE:-
RESULT:- Hence Power Spectral Density is verified and output waveforms are plotted..
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INPUT:
OUTPUT:
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Department of Electronics and Communication Engineering Digital Signal Procesing Lab
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Department of Electronics and Communication Engineering Digital Signal Procesing Lab
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Department of Electronics and Communication Engineering Digital Signal Procesing Lab
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