Real-Time Specification Patterns and Tools: Abstract
Real-Time Specification Patterns and Tools: Abstract
1 Introduction
2 Technical Background
Since patterns are used to express timing and behavioral constraints on the
execution of a system, we base the semantics of patterns on the notion of timed
traces, which are sequences mixing events and time delays, (see Def. 1 below).
We use a dense time model, meaning that we consider rational time delays and
work both with strict and non-strict time bounds.
The semantics of a pattern will be expressed as the set of all timed traces
where the pattern holds. We use two different approaches to define set of traces:
(1) Time Transition Systems (TTS), whose semantics relies on timed traces; and
(2) a timed extensions of Linear Temporal Logic, called MTL. In our verification
tool chain, both Fiacre and specification patterns are compiled into TTS.
Time Transition Systems (TTS) are a generalization of Time Petri Nets [17] with
priorities and data variables. We describe the semantics of TTS using a simple
example. Figure 1 gives a model for a simple airlock system consisting of two
doors (D1 and D2 ) and two buttons. At any time, at most one door can be open.
This constraint is modeled by the fact that at most one of the places D1 isOpen
and D2 isOpen may have a token. Additionally, an open door is automatically
closed after exactly 4 units of time (u.t.), followed by a ventilation procedure
that lasts 6 u.t. This behavior is modeled by adding timing constraints on the
transitions Open1 , Open2 and Ventil. Moreover, requests to open the door D2
have higher priority than requests to open D1 . This is modeled using a priority
(dashed arrow) from the transition Open2 to Open1 . A shutdown command can
be triggered if no request is pending.
Open1
req1
pre:
[6; 6] D1 isOpen
pre: ¬req1 [4; 4]
Button1
act: req1 := true
Ventil. [4; 4]
Idle Refresh D2 isOpen
pre: ¬req2 act: req2 := false
Button2 [0, 0] Close2
act: req2 := true
req2
pre:
Open2
To understand the model, the reader may, at first, ignore side conditions and
side effects (the pre and act expressions inside dotted rectangles). In this case,
a TTS is a standard Time Petri Net, where circles are places and rectangles
are transitions. A transition is enabled if there are enough tokens in its input
places. A time interval, such as I = [d1 ; d2 [, indicates that the corresponding
transition must be fired if it has been enabled for d units of time with d ∈ I.
As a consequence, a transition associated to the time interval [0; 0] must fire
as soon as it is enabled. Our model includes two boolean variables, req1 and
req2 , indicating whether a request to open door D1 (resp. D2 ) is pending. Those
variables are read by pre-conditions on transitions Openi , Buttoni , and Shutdown
and are modified by post-actions on transitions Buttoni and Closei . For instance,
the pre-condition ¬req2 on Button2 is used to disable the transition when the
door is already open. This implies that pressing the button while the door is
open has no further effect.
We introduce some basic notations used in the remainder of the paper. (A
complete, formal description of the TTS semantics can be found in [2].) Like with
Petri Nets, the state of a TTS depends on its marking, m, that is the number
of tokens in each place. We write M the set of markings. Since we manipulate
values, the state of a TTS also depends on its store, that is a mapping from
variable names to their respective values. We use the symbol s for a store and
write S for the set of stores. Finally, we use the symbol t for a transition and T
for the set of transitions of a TTS. The behavior of a TTS is defined by the set
of all its (timed) traces. In this particular case, a trace will contain information
about fired transitions (e.g. Open1 ), markings, the value of variables, and the
passing of time. Formally, we define an event ω as a triple (t, m, s) recording the
marking and store immediately after the transition t has been fired. We denote Ω
the set T ×M×S of events. The set of non-negative rational numbers is written
Q+ .
Definition 1 (Timed trace). A timed trace σ is a possibly infinite sequence of
events ω ∈ Ω and durations d(δ) with δ ∈ Q+ . Formally, σ is a partial mapping
from N to Ω ∗ = Ω ∪ {d(δ) | δ ∈ Q+ } such that σ(i) is defined whenever σ(j) is
defined and i ≤ j.
Given a finite trace σ and a—possibly infinite—trace σ ′ , we denote σσ ′ the con-
catenation of σ and σ ′ . This operation is associative. The semantics of patterns
will be defined as a set of timed traces. Given a real-time pattern P , we say that
a TTS T satisfies the requirement P if all the traces of T hold for P .
In each class, generic patterns may be specialized using one of five scope modifiers
that limit the range of the execution trace over which the pattern must hold:
– Global : the default scope modifier, that does not limit the range of the
pattern. The pattern must hold over the whole timed trace;
– Before R : limit the pattern to the beginning of a time trace, up to the
first occurrence of R;
– After Q : limit the pattern to the events following the first R;
– Between Q and R : limit the pattern to the events occurring between an
event Q and the following occurrence of an event R;
– After Q Until R : similar to the previous scope modifier, except that we
do not require that R must necessarily occur after a Q.
Finally, timed patterns are obtained using one of two possible kind of timing
modifiers that limit the possible dates of events referred in the pattern:
An existence pattern is used to express that, in every trace of the system, some
events must occur.
Present A after B within I
Predicate A must hold between d1 and d2 units of time (u.t) after the first oc-
currence of B. The pattern is also satisfied if B never holds.
Example: present Ventil. after Open1 ∨ Open2 within [0, 10]
mtl def.: (¬B) W (B ∧ True UI A)
fott def.: ∀σ1 , σ2 . (σ = σ1 Bσ2 ∧ B ∈
/ σ1 ) ⇒ ∃σ3 , σ4 . σ2 = σ3 Aσ4 ∧ ∆(σ3 ) ∈ I
pre: foundB pre: foundB ∧¬ foundA
Observer: E2 Start [d1 , d1 ] E1 Error [d2 , d2 ]
act: foundB := true act: flag := true act: if flag then
foundA := true
Absence patterns are used to express that some condition should never occur.
Absent A after B for interval I
Predicate A must never hold between d1 –d2 u.t. after the first occurrence of B.
Comment: This pattern is dual to Present A after B within I (it is not equivalent
to its negation because, in both patterns, B is not required to occur).
Example: absent Open1 ∨ Open2 after Close1 ∨ Close2 for interval [0, 10]
mtl def.: ¬B W (B ∧ @I ¬A)
fott def.: ∀σ1 , σ2 , σ3 , ω . (σ = σ1 Bσ2 ωσ3 ∧ B ∈
/ σ1 ∧ ∆(σ2 ) ∈ I) ⇒ ¬A(ω)
Observer: We use the same observer as for Present A after B within I, but here
Error is the expected behavior.
The associated ltl formula is ♦B ⇒ ♦Error.
Explanation:
Same as the explanation for Present A after B within I.
Absent A before B for duration D
No A can occur less than D u.t. before the first occurrence of B. The pattern
holds if there are no occurrence of B.
Example: absent Open1 before Close1 for duration 3
mtl def.: ♦B ⇒ (A ⇒ (@[0,D] ¬B)) U B
fott def.: ∀σ1 , σ2 , σ3 , ω . (σ = σ1 ωσ2 Bσ3 ∧ B ∈
/ σ1 ωσ2 ∧ ∆(σ2 ) 6 D) ⇒ ¬A(ω)
E2 E1 idle Reset
Observer: [D, D]
act: foundB := true act: bad := true act: bad := false
foundB := false
E2 E3
act: if ¬ foundR then foundA := false act: foundR=true
Avionic Protocol and AADL. Our first example is a network avionic protocol
(NPL) which includes several functions allowing the pilot and ground stations
to receive and send information relative to the plane: weather, speed, . . . AADL
has been used to model the dynamic architecture for this demonstrator [5].
The AADL model includes several threads that exchange information through
shared memory data and amounts to about 8 diagrams and 800 lines of code
(using AADL textual syntax). The AADL code specifies both the hardware
and software architecture of the system and defines the real time properties of
threads, like for instance their dispatch protocol (periodic or sporadic) or their
periods.
We used the AADL2Fiacre plug-in of Topcased to check properties on the
NPL specification. The Fiacre model obtained after transformation takes into
account the complete behavior described in the AADL model but also the whole
language execution model, meaning that our interpretation takes fully into ac-
count the scheduling semantics as specified in the AADL standard. The abstract
state space for the TTS generated from Fiacre has about 120 000 states and
180 000 transitions and can be generated in less than 12s on a typical devel-
opment computer (Intel dual-core processor at 2GHz with 2Gb of RAM). On
examples of this size, our model checker is able to prove formal properties in a
few seconds. We checked a set of 22 requirements that were given together with
the description of the system, all expressed using a natural language description
and, in one case, a scenario based on a UML sequence diagram. Of these 22
requirements, 18 where instances of “untimed patterns”, such as checking the
absence of deadlock or that threads are resettable. The four remaining require-
ments where “response patterns” of the kind A leadsto first B within [0, d]. Using
patterns, we were able to check the 22 patterns in less than 5min.
Finally, using the notation S.init and S.end to refer to a start (resp. end) event
in the service S, we can express that drugs must be delivered within 48 hours
of the medical examination start: MCS.init leadsto PS.sendDrugsOrder within
[0; 48].
The complete scenario is given in [9], where we describe a transformation tool
chain from Timed BPEL processes to Fiacre. For a more complex version of the
health care scenario, with seven different services and more concurrent activities,
the state graph for the TTS generated from Fiacre is quite small, with only 886
states and 2476 transitions. The generation of the Fiacre specification and its
corresponding state space takes less than a second. For examples of this size, the
verification time for checking a requirement is negligible (half a second).
(P2) When the car starts moving, the door must be closed:
(P3) When a passenger select a destination (in the car), a signal should stay
illuminated until the car is arrived:
We can prove that these three patterns are valid on our Fiacre model. Con-
cerning the performances, we are able to generate the complete state space of
the railcar system in 310ms, using 400kB of memory. This gives an upper-bound
to the complexity of checking simple (untimed) reachability properties on the
system, like for instance the absence of deadlocks. The three patterns can all
be checked in under 1.5s. For instance, we observed that checking property
(P1) is not more complex than exploring the complete system: the property is
checked in 450ms, using 780kB of memory. Also, this is roughly the same com-
plexity than checking the corresponding untimed requirement in LTL that is:
@ (Passenger/sendReq ⇒ ♦Control/ackTerm).
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