Timed Automata
Timed Automata
Radek Pelánek
Basic Concepts Theoretical Results Practical Verification Summary
Motivation
Motivation
Motivation
Motivation
Fischer’s Protocol
Motivation
Fischer’s Protocol
id – shared variable, initialized -1
each process has it’s own timer (for delaying)
for correctness it is necessary that K > D
Process i:
while (true) {
<noncritical section>;
while id != -1 do {}
id := i;
delay K;
if (id = i) {
<critical section>;
id := -1;
}
}
Basic Concepts Theoretical Results Practical Verification Summary
Motivation
Motivation
Motivation
Motivation
Motivation
TA Introduction
Timed Automata
TA Introduction
TA Introduction
TA Introduction
TA Introduction
Syntax
Clock Constraints
Syntax
Semantics
Semantics
Clock Valuations
(ν + d)(x) = ν(x) + d
Semantics
Semantics
Examples
Semantics
Semantics
Example
Semantics
Example
clock valuation:
assignment of a real value
to x
initial state (off , 0)
example of a run:
2.4
(off , 0) −→ (off , 2.4) −→
1.5
(light, 0) −→
(light, 1.5) −→
(bright, 1.5) −→ ...
Basic Concepts Theoretical Results Practical Verification Summary
Semantics
Example
Semantics
Semantics: Notes
Verification Problems
Reachability Problem
Reachability Problem
Input: a timed automaton A, a location l of the automaton
Question: does there exists a run of A which ends in l
Verification Problems
Example
How to do it algorithmically?
Basic Concepts Theoretical Results Practical Verification Summary
Verification Problems
Verification Problems
Reachability: Attempt 1
Verification Problems
Reachability: Attempt 2
Verification Problems
Reachability: Attempt 2
Verification Problems
Reachability: Attempt X
Verification Problems
Verification Problems
Verification Problems
Another Approach?
Verification Problems
Another Approach?
Verification Problems
Another Approach?
Verification Problems
Reachability Problem
Theorem
The reachability problem is PSPACE-complete.
Region Construction
Region Construction
Main idea:
some clock valuations are equivalent
work with regions of valuations instead of valuations
finite number of regions
Basic Concepts Theoretical Results Practical Verification Summary
Region Construction
Preliminaries
Region Construction
Region Construction
Condition 1:
Region Construction
Condition 2:
If the value of clock is below its max bound, then either it has
zero fractional part in both ν and ν 0 or in neither of them.
Region Construction
Condition 3:
For two clocks that are below their max bound, the ordering of
fractional parts must be the same in both ν and ν 0 .
ν(x) ≤ cx ∧ ν(y ) ≤ cy ⇒
fr (ν(x)) ≤ fr (ν(y )) ⇔ fr (ν 0 (x)) ≤ fr (ν 0 (y ))
Basic Concepts Theoretical Results Practical Verification Summary
Region Construction
Region Construction
Region Construction
Equivalence: Example 1
Identify cx , cy
Basic Concepts Theoretical Results Practical Verification Summary
Region Construction
Equivalence: Example 2
suppose cx = 4, cy = 5, cz = 1
let (x, y , z) denote valuations, decide:
1 (0, 0.14, 0.3) ∼
= (0.05, 0.1, 0.32) ?
2 (1.9, 4.2, 0.4) ∼
= (2.8, 4.3, 0.7) ?
3 (0.05, 0.1, 0.3) ∼
= (0.2, 0.1, 0.4) ?
4 (0.03, 1.1, 0.3) ∼
= (0.05, 1.2, 0.3) ?
5 ∼
(3.9, 5.3, 0.4) = (3.8, 6.9, 0.8) ?
Basic Concepts Theoretical Results Practical Verification Summary
Region Construction
Regions
Definition (Region)
Classes of equivalence ∼
= are called regions, denoted [ν].
Lemma
The number of regions is at most |X |! · 2|X | ·
Q
x∈X (2cx + 2).
Basic Concepts Theoretical Results Practical Verification Summary
Region Construction
Regions: Example
Region Construction
Regions: Example
Region Construction
Region Graph
Region Construction
Operations on Regions
Region Construction
Example: Automaton
(source: R. Alur)
Basic Concepts Theoretical Results Practical Verification Summary
Region Construction
Zones
Zones
Zones
Zones
Zones: Operations
Zones
Extensions
Extensions
Extensions
(source: R. Alur)
Basic Concepts Theoretical Results Practical Verification Summary
Extensions
Fischer’s Protocol
id – shared variable, initialized -1
assumption: known upper bound D on reading/writing
variable in shared memory, for correctness it is necessary
that K > D
Process i:
while (true) {
<noncritical section>;
while id != -1 do {}
id := i;
delay K;
if (id = i) {
<critical section>;
id := -1;
}
Basic Concepts Theoretical Results Practical Verification Summary
Extensions
Summary