Capacitance of

Forward Biased Diode

• When a diode changes from reverse biased (with little current through it)
to forward biased (with significant current across it) the charge being
stored near and across the junction changes
• Part of the change in charges is due to the change in the width of the
depletion region and therefore the amount of immobile charge stored in it
(
Cj)
• An additional change in the charge storage is necessary to account for the
excess of minority carriers close to the depletion region edges required for
the diffusion current to exists. This component is modeled by another
capacitance, called the diffusion capacitance (
Cd)
• As a diode is turned off (changes from forward biased to reverse biased)
for a short period of time a current will flow in the negative direction until
the minority charge is removed
Charge of Forward Biased Diode
Direction of positive current hole
diffusion

electron immobile charge

diffusion
- -
- - + + + +
+ + + +
- - + + + +
- -
- -

P N
In the P region we have a lot of holes In the N region we have a lot of electrons
that will diffuse toward the N region that will diffuse toward the P region

Depletion Region
 Total Capacitance of
Forward Biased Diode
• It is the sum of the diffusion capacitance Cd and the depletion
capacitance Cj
C total
C d
C j

• For a forward biased diode the junction capacitance is roughly

approximated by:
C j
2
C j0

C j
2
C j0 for V D
0.75
 0

• The approximation is not critical since the diffusion capacitance is
typically much larger than than the depletion capacitance
C d
C j
 Diffusion Capacitance
• To find the diffusion capacitance we first find the minority charge
“close” the depletion edges Qd and then differentiate it with respect
to the voltage applied Vd.

Small signal
diffusion capacitance
C d


d Qd
dVd
VD

T
I d
@ V D

VT

The diffusion capacitance of a forward biased diode

is proportional to the diode current
 Diffusion Charge
excess of minority excess of minority
charge (holes) charge (electrons)
stored in the P region
stored in the N region Q d
Q p
Q n



x'

Q p
q A
n p
x '
dx '
q A
n p
0
e dx '

Lp

0 0

Vd
x' Vd
2

q A
n p0
e
1
e dx '
q A n i Ln V
VT Lp
Q n
e
1
T

0 NA
Vd

x'

q A n p0
e
1

e
VT Lp
dx '

0

x'

2 Vd Vd
n q A n 2i L p V

q A e
1
L p e
e
1
i VT Lp T
0
ND ND
pn(
=0)


x' p n 
p n 
0
e Ln

n p
x ' 
n p
x '
0
e

Lp
np(x'=0)
Vd

Vd VT 0
VT p n0 e
n p0 e pn0
x'
0
np0
x
-xp 0 xn
 Diffusion Charge
• The excess hole charge stored in the N region is given by:
p n
x n 
p n0
e V d
V T

1

Q p
A q
pn
x n 
p n0
L p


A q L p p n0
e
1


V d
V T

qDp
J p
p n0
e V d
V T

1
L 2p L 2p
Lp
A J p
I p
I p
p
Dp Dp
Lp L p

D p
p
p n0
eV
V
1

J p
d T

qDp

• Similarly, the excess electron charge stored in the P region is:

Q n
I n n
 Total Diffusion Charge
• Thus, the total excess minority carrier charge is:
Q d
Q p
Q n
I p  p
I n
n

• Since the diode current is I d
I p
I n it is more convenient

to express the excess charge as:

Q d
T
I d (where
T is called mean transit time )

 Diffusion Capacitance

C d





dQ d
dV d VD


d
T I d

dV d



VD

T
dI d
dV d VD


T
rd

Vd Vd

VT VT
1 dI d d
I s
e
1

I se I d
I s Id






r d dV d VD dV d VD VT VD VT VD VT VD

C d
T



Id
VT VD
 Transition Time
• The general expression for
T is quite cumbersome:

T
C d
r d

2 2 Vd
1 dI d q A Dn n q A Dp n VT
where
with I d
i

i

e
1

rd dV d VD Ln N A Lp ND

2 2 Vd
d Qd q A n L p q A n Ln VT
C d
with Qd
i

i
e
1
dVd VD ND NA
 Transition Time
• In practice, since usually diodes are single sided (i.e. one side will be
much more heavily doped than the other side) the minority charge
storage in the heavily doped side can be ignored

2 Vd 2 Vd
q An Lp q A n i Ln V
Q p

i
e
1
VT
Q n
e
1T

ND NA

• Assuming the P side is more heavily doped than the N side:

N A
N D
Q p
Q n
Q d
Q p
I d
I p

NOTE:
•Holes (Qp) are minority
2
Lp carriers on the N side

T
 p
• Electrons (Qn) are minority
Dp
carriers on the P side
 Single Sided Diodes

• One side of the diode is more heavily doped than the other
• Many of the junctions encountered in integrated circuits are one-
sided junctions with the lightly doped side being the substrate or
the well.
• Foe single sided diodes the depletion region will extend mostly on
the lightly doped side.
• The depletion capacitance is almost independent of the doping
concentration on the heavily doped side
 Single Sided Diodes

• The PN junctions inside CMOS ICs are single-sided

• NMOS transistors have parasitic diodes with the N side more heavily
doped than the P side: N D
N A
• PMOS transistors have parasitic diodes with the P side more heavily
doped than the N side: N A
N D

• NOTE: in general within an MOS transistor, it is undesirable to

have a forward biased junction, it usually means there is a
problem.
 Schottky Diodes
• A different type of diode, can be realized by contacting a metal to a
lightly doped semiconductor region.
• The use of a lightly doped semiconductor, causes a depletion region
to form at the interface between the aluminum anode and the n+
silicon region
 Schottky Diodes

• The voltage drop of a forward biased Schottky diode is smaller. The

value depends on the metal used. For aluminum is approx 0.5 V
• When the diode is forward biased there is no minority charge storage
in the lightly doped n+ region. Thus Cd = 0
• The absence of diffusion capacitance makes the diode much faster.
Diodes realized in CMOS technology

NOTE:
For the case of Fig 14.54(a) the anode is inevitably grounded
Diode SPICE model
 Diode SPICE Modeling





I d
I s exp
Vd
nV T

1
GMIN
V d

Convergence Aid

I d
I s exp

VT

BV
V d

1

BV
VT


IS (BV/VT)

I d
I s
GMIN
V d
MOS physical structure
 Thermal Equilibrium
• Absence of any stimulus to the device
• The populations of electrons and holes are each in equilibrium
and, therefore must have zero current densities
Dn 0 d
0 dn 0
0
q n 0
n E 0
q D n 0
n 0
n
D n
dx dx dx
dp0
0
q n 0
p E 0
q D p
dx

x x
D n dn 0 dn0
d
0


n n 0
d
0
V T
dn0

d
0
V T
n
n0 xR x R
0

0
x
0
x R 
V T ln


n 0
x

n0
x R


 Thermal Equilibrium

0
x
0
x R 
V T ln


n 0
x

n0
x R


By convention the reference for the potential
is chosen to be the point where the carrier
0
x R 
0 when n 0
x R 
ni
concentration is the intrinsic concentration

0
x

n 0
x

 0
x
V T ln n 0
x
n i e VT

ni

NOTE:
for N type silicon since n0 > ni the electrostatic potential at equilibrium is positive
 Thermal Equilibrium
A similar derivation for the hole concentration leads to the following
result:

 0
x

p0
x

 0
x
V T ln p 0
x
n i e VT

ni

NOTE:
for P type silicon since p0 > ni the electrostatic potential at equilibrium is negative
 MOS Capacitor in Thermal
Equilibrium At equilibrium the p-
substrate and the n+
source and drain
form a pn junction.
Therefore a depletion
region exists between
the n+ source and drain
and the p- substrate

Since source and drain are separated by back-to-

back junctions, the resistance between the source
and the drain is very high (> 1012 ohm)

source/drain/bulk
gate
The gate and the substrate of the MOS
transistor form a parallel plate capacitor
with the SiO2 as dielectric
Figure. Using the MOSFET as a capacitor
 MOS structure in
Thermal Equilibrium
VGB = 0

n+
p E0

equilibrium potential in
the silicon (bulk=substrate)


 p
V T ln
NA
ni
equilibrium potential in
the polysilicon (gate)
n +
V T ln



ND
ni

17 -3 19 -3 10 -3
N A
10 cm N D
3
10 cm n i
10 cm
n+
 p
550 mV

420 mV 
970 mV
 MOS in Thermal Equilibrium
VGB = 0

n+
 p970 mV E0

• From the sign of the potential drop across the MOS structure it
follows that the electric field points from gate to bulk.
• Therefore, a positive charge must be present on the polysilicon gate
and there must be a balancing negative charge in the p-type silicon
substrate (the oxide will be considered a charge-free perfect
insulator)
 Charge on the MOS in TE
• Since the gate is highly conductive n+ polysilicon the gate charge QG0 can be
thought as a sheet charge located at the bottom surface of the polysilicon gate
• The charge on the p-type silicon substrate QB0 is formed by the immobile
negatively charged acceptor ions (to a depletion depth of Xd0 ) left behind by
the mobile holes repelled by the positive charge on the gate.

VGB = 0

M O S
 Charge on the MOS in TE
VGB = 0

G0
 B0
q N A X d0
units : C
cm2

Potential across the MOS in TE

Surface Potential


Voltage drop Potential at the SiO2-silicon
across the oxide interface (x=0)

Voltage drop across

M O S the depletion region
In the silicon

Built in Voltage across
BUILT-IN
n+
 p
V ox , 0
V B , 0

the MOS structure
 Potential across the MOS in TE
• The equilibrium potential of a given material is commonly
referred as its Fermi potential

n+
F-gate
V T ln
ND
ni

 p  F-bulk
V T ln
NA
ni

• The Built in voltage across the MOS structure is often
expressed in term of the work function between the gate
material and the bulk silicon

 MS
 F-gate
F-bulk
 n+
 p
 BUILT-IN
V T ln

NDNA
n 2i

NOTE: This term is referred as the metal-to-silicon work function even though the
gate terminal is something other than metal (i.e. polysilicon)
 MOS in TE: “fixing” KVL
VGB = 0

mn+
V ox ,0
V B0
 pm
0 V ox ,0
V B0
 mn+
 pm

 n+
 p 
 BUILT-IN

MOS in TE

NOTE:
for the case of TE the
gate and the bulk metal
contacts are at the same
potential

 n+  p
mn+  pm 
 MOS in TE: Quantitative Analysis
The total excess charge in the region

tox
x
Xd0 is zero (neutrality of charge)

The electric field is confined in the region

tox < x < Xd0

E ox In the oxide (
tox < x < 0) the charge density is zero thus the
field is constant (Eox):
+
E
0
0
dE 
Gauss ' s Law :

dx 

Boundary condition at the oxide/silicon interface (0
x
0+):

3
ox 

ox
E ox
 s
E
0+ 
E
0 + 
E ox
E ox
E
0 +
s

s
ox
 MOS in TE: Quantitative Analysis
E ox
Within the same material the
electric field will not jump !

In the charged region of the silicon oxide/silicon interface (0+
x < Xd0) the charge density is
constant:
E
X do
X do
q N A q N A
dE
x


s
dx

dE
x


s 0+

dx

E
0+

0 q NA

 s E
X d0 
 s E
0 
q N A X d0
+

E
0 

+
X d0

s

s q N A
E ox
E
0 -
E
0 +

X d0

ox
ox
 MOS in TE: Quantitative Analysis
E ox
Within the same material the
electric field will not jump !

• Just for the sake of double-checking the correctness of the

previous result let's also apply the boundary condition at the
interface between gate and oxide and see if we get the same
result
G  B q N A X d0

G
E 
t ox 
G
ox E 
t 
E 
t 

- + +



ox ox

ox
ox
ox

E ox
MOS Potential in TE
E ox

d 0
x

E 0
x

dx

s0
0
0

MOS in TE: Potential in the oxide
M O S
d
0
x
E 0
x
dx

s0
0
0

t ox
x
0 :
x
q N A X d0 x q N A X d0

0
x
 n+


E ox dx

dx

x
t ox


t ox

ox
t
ox ox

Potential in the oxide

q N A X d0
for t ox  x0 : 0  x
n+   xt ox 
ox
MOS in TE: Potential in the oxide
M O S
Potential in the oxide

s0
0
0
for
t ox
x
0 :

q N A X d0

0
x
 n+

x
t ox


ox

Surface Potential (Potential at the oxide/silicon interface)

q N A X d0 q N A X d0 ox
 s0 0 0
 n+  t ox
 n+  with
ox

ox  ox t ox

Voltage drop across the oxide

q N A X d0 G0 with :
V ox ,0
0 
t ox 
0
0
 n+
 s0


G0
 B0
q N A X do

ox
ox

NOTE: VOX,0 is proportional to the charge stored on each side of the oxide
MOS in TE: potential in the depletion
region in the silicon substrate
M O S
 x

dE 0
x
dx
s

depletion region
0
x
X d0 :
E 0
x
x

x

x

qN A q N A x

dE 0
x

 E 0
x
E 0
0 


+
dx

E
0+

0 0+ s 0+
s
s
qN A x q N A X d0 qN A x qN A
E 0  x
E 0 0 
+


 X do x
s s s s
+ q N A X d0
E 0
0 


s
MOS in TE: potential in the depletion
region in the silicon substrate
M O S Electric Field in the Depletion region
for 0
x
X d0 :
qNA
E 0
x

X d0
x


s

d
0
x
E 0
x
dx
charged region
0
x
X d0 :
0
x
x x
qN A

d
0
x


E 0
x
dx
0
x
0
0



X do
x
dx


0
0 0
s

0
x
qN A qN A x qN A x2
 0  x0 0
 X do  dx  x dx
 X do x

s 0 s 0 s 2

2
qN A x

0
x
0
0
X do x


s 2
MOS in TE: potential in the depletion
region in the silicon substrate
M O S
Surface Potential
q N A X d0
 s0 0 0
 n+ 
ox

charged region

2
qN A x
0
x
X d0 :
0
x
0
0
X do x


s 2

Potential in the depletion region in the substrate

for 0
x
X d0 :



0
x

n+

q N A X d0

ox


qN A

s

X do x

x2
2

MOS in TE: potential in the depletion
region in the silicon substrate
M O S
Potential in the depletion region in the substrate

for 0
x
X d0 :

0
x
 n+

q N A X d0

ox


qN A

s

X do x

x2
2

charged region

q N A X d0 qN A 2 This must be the

0  X d0  p
n+   X do voltage drop across
ox 2 s
the charged region of
the silicon substrate

V B 0
Voltage drop across q N A X d0 qN A 2
n+  p
 X do
the MOS structure ox 2 s

Since this is the voltage

drop across the oxide

V ox , 0
 MOS in TE:
Width of the Depletion region
M O S Voltage drop across the MOS structure
q N A X d0 qN A 2
 n+  p
V ox ,0 V B0
 X do
ox 2 s

Voltage drop across the oxide

q N A X d0 G  B
depletion region V ox ,0




ox
ox
ox

Voltage drop across the charged

region of the silicon substrate

qNA 2 q N A X d0 qNA 2
X do    n+  p 
0 V B0
X do
2 s ox 2 s

q N A 2
s 2
s 2
s 2
s
X

2
X d0

 n+
 p 
0 X

2
X d0

 n+
 p 
0
do

ox q N A qNA
do

ox q NA
 MOS in TE:
Width of the Depletion region
2
s 2
s b

b2
4ac
X

2
X d0

 n+
 p 
0 ax
bx
c
0
2
x

do

ox q N A 2a
NOTE: Xd0 can be only positive

2 s
ox 

4 2s
 2ox 8  s
q N An+
 p 

2

X do

2

 s
ox 
s
 ox 2 s
q N A n+  p 

2 2 s
 ox



1
1

2
s
2ox
q N A 2s
 n+  p 


Depletion Width: X do

s

ox

1

2
2ox
q N A
s

 n+
 p 
1

 MOS under Bias
VGB
0

(FLATBAND) – ACCUMULATION – DEPLETION – (THRESHOLD)
INVERSION

 Flatband
• We apply a gate to bulk voltage that is opposite to the built-in
potential. This special voltage bias is called flat-band voltage
NOTICE:
V FB 
BUILT_IN
 n+.0
 p.0
Flat-band Voltage For an MOS structure with
n+ poly-silicon gate and
p-type substrate this
voltage is negative

mn+ V GB
mn+
 pm
V MOS

V MOS V GB
BUILT-IN
V MOS

pm V GB
V FB
V MOS

The bulk metal contact is considered fixed  p
p,0

n+
n+,0 V GB

n+  p
n+,0V GB  p
if V GB
V FB
V MOS
0

n+,0p,0 V GB
V FB V GB
 Flatband
• In flat-band condition (VGB=VFB) there is no internal voltage drop
across the MOS capacitor.

n+,0
V GB

The bulk metal contact

is considered fixed

p =
420 mV (
n+,o = 550 mV)

Thermal Equilibrium

Applying VGB = VFB shifts the gate metal contact

lower by – 970 mV (=VFB)
Flatband
• Since in flat-band condition
(VGB=VFB) there is no internal voltage
drop across the MOS capacitor, as a
result the electric field is zero and the
gate charge density is zero

Q G
V GB
V FB 
0