Huffman Encoder and Decoder Using Verilog
Huffman Encoder and Decoder Using Verilog
International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 7, Issue 2, March - April 2018 ISSN 2278-6856
HUFFMAN ENCODER AND DECODER
USING VERILOG
Abhishek Kumar Jha, Deepak Pathak, Bharat Yadav, Abhishek Bharadwaj, Neerja Singh
ABES Engineering College,
NH-24, Ghaziabad, India
.
Abstract : A binary Huffman encoder has been made using 2. Preliminary
Verilog HDL on tool Xilinx ise14.6 isim simulator. A Huffman decoder is implemented for text. The text
The Huffman encoder has been designed and synthesized using compression involves its encoding; the text decoder
a finite state machine. It basically reduces the repeated messages
contains the Huffman decoder for obtaining the original
and thus contracts the message. So now the repeated messages
will be send only one time. text.
Keywords: Compression, bandwidth, lossless, lossy. Design and Implementation of Huffman Decoder for Text
data Compression.
The Huffman tree used by encoder and decoder is shown
1. Introduction in.The alphabet consists of the uppercase letters and the
Compression is a necessity in the current world of
space. All left branches are labeled 0, and all right branches
technology, which is centered on speed and efficiency.
are labeled1.This tree is based on the following assumed
Consequently, large and bulky pieces of information are
frequencies E 130 T 93 N 78 R 77 I 74 O 74 A 73 S 63 D
abandoned for smaller bits of data, which can be shared
44 H 35 L 35 C 30 F 28 P 27 U 27 M 25 Y 19 G 16 W 16
between peers at faster rates. Data can be broken into
V 13 B 9 X 5 K 3 Q 3 J 2 Z 1 It is assumed that there are
smaller pieces or forcefully compressed by programs that
130 Es and 182 spaces for every 1000 letters. The encoder
are powered by algorithms. The two major types of
retrieves the code for each symbol from a map, and shifts it
compression In algorithms are lossless compression and
out one bit at the time. The decoder is a finite state machine
lossy compression. Lossless compression is used for
whose state transition graph is obtained from the tree by
applications that require an exact reconstruction of the
adding acs from the leaves back to the top of the tree. Each
original data, while lossy compression is used when the
node uses ten bits for its encoding. The code of the root is
user can tolerate some differences between the original and
0. If a state is not a leaf of the tree, and its encoding is n,
reconstructed representations of the data. Lossy
then the encodings of its two children are 2n+1 and 2n+2.
compression techniques involve some loss of information
and data are compressed usinglossy techniques generally
cannot be recovered or reconstructed exactly return for
accepting this distortion in the reconstruction, we can
generally obtain much higher compression ratios than is
possible with lossless compression.
Various lossless data compression algorithms have been
proposed and used. Huffman Coding, Arithmetic Coding,
Shannon Fano Algorithm, Run Length Encoding Algorithm
are some of the techniques in use.
Huffman codes are prefix codes and are optimum for a set
of probabilities. The Huffman code is based on two
observations. First, in an optimum code, symbols that occur
more frequently (have a higher probability of occurrence)
have shorter codewords than symbols that occur less
frequently. Second, in an optimum code, the two symbols Fig. 1 Encoder
that occur least frequently have the same length. The
Huffman procedure is obtained by adding a simple
requirement to these two observations. This requirement is 3. Implementation of Huffman Encoder
that the codewords corresponding to the two lowest The Fig 1 shows the block diagram of encoder and code for
probability symbols differ only in the last bit. each character which comes from the tree stored in the
LUT. Character input which is given to the encoder is
stored inside the LUT. Therefore, the output of the encoder
block will be these stored values inside the LUT.
Volume 7, Issue 2, March – April 2018 Page 79
International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 7, Issue 2, March - April 2018 ISSN 2278-6856
The block diagram for the decoder in which the coded T 93 N 78 R 77 I 74 O 74 A 73 S 63 D 44 H 35 L 35 C 30
value is first stored in the buffer then it is shifted using a F 28 P 27 U 27 M 25 Y 19 G 16 W 16 V 13 B 9 X 5 K 3 Q
LIFO,Theshifted value is then stored in the 9 bit temporary 3 J 2 Z 1 is shown below.
register which is then compared with respective codes
stored in the LUT and finally the character is decoded.
Fig. 5 RTL View of Huffman encoder
RTL View is a Register Transfer Level graphical
representation of your design. This representation (.ngr file
produced by Xilinx Synthesis Technology (XST)) is
generated by the synthesis tool at earlier stages of a
Fig. 2 Flowchart of Coding Process synthesis process when technology mapping is not yet
completed.
The above shown Fig. 5 shows the Register Transistor
Logic (RTL) View of the Huffman encoder. The RTL view
describes the complete circuit into a single block in which
there are multiples transistors used to complete an encoder
circuit.
Fig. 3 Assigning of Codeword
Fig. 6.1 Simulation result
Fig. 4 Binary Tree
4. Simulation Results for Text using the
Proposed Method
A Huffman Encoder and decoder is designed, described in
Verilog and implemented on a Xilinx Virtex 5 FPGA using
ISE 14.7. The design aims to achieve high operating
frequencies using few logical resources. The functional
simulation for the Huffman encoder and decoder block is
carried out using the ISE design suite 14.7 The binary tree
for the characters based on the assumed frequencies E 130 Fig. 6.2 Simulation result
Volume 7, Issue 2, March – April 2018 Page 80
International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 7, Issue 2, March - April 2018 ISSN 2278-6856
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AUTHORS
Abhishek Kumar Jha is pursuing his
Engineering in Electronics and
Communication from ABES Engineering
Fig. 7 Simulation report of Huffman encoder College (2014-2018) batch.
The input signal is a 5-bit input signal which acts as the He is a certified HDL Programmer and has
address to the LUT in the encoder stage which gives worked on multiple projects with his team.
corresponding alphabetical outputs. Encode is the serial
Deepak Pathak is pursuing his Engineering in
output stream which given as input to the decoder. Is the Electronics and Communication from ABES
decoded character output from the decoder. The encoding Engineering College (2014-2018) batch.
and decoding operations are performed for the text He is a certified HDL Programmer and has
HELLO. The simulation results for HELLO text reveal that worked on multiple projects with his team.
only 22 bits are required to store it whereas 40 bits are
required for the original text. Hence original data can be Bharat Yadav is pursuing his Engineering in
Electronics and Communication from ABES
retrieved easily and requires less memory by using the new
Engineering College (2014-2018) batch.
binary tree algorithm method. He is a certified HDL Programmer and has
worked on multiple projects with his team.
5. Conclusion
This research will show that the higher data redundancy Abhishek Bharadwaj is pursuing his
helps to achieve more compression. The presented new Engineering in Electronics and
compression and decompression technique based on Communication from ABES Engineering
College (2015-2018) batch.
Huffman tree for scan testing is used to reduce test data size He has also completed his Diploma from
and test application time. At Present Started with designing Lovely Professional University.
a Huffman encoder and decoder in Verilog platform.
Huffman decoder using Binary tree algorithm was Neerja Singh is an Asst. Professor in the
implemented on Verilog and FPGA platforms. The Department of Electronics and
Architecture implemented by VERILOG Design, using Communication Engineering in ABES
Engineering College, Ghaziabad, Uttar
XIINX 14.7 versions. Future works needs to be carried out
Pradesh, India. She has received her M.Tech.
to improve the area. On comparing with other different in VLSI Design and B. Tech in Electronics and
compression techniques, came to a conclusion that Communication Engineering in the year of 2012 and
Huffman coding is efficient technique for image 2010 respectively. Her main research interests are in Low
compression and decompression to some extent. power VLSI Design for low power Electronics product.
6. References
[1] Sameer palnitkar, Verilog HDL design
[2] BP Lathi, Principles of communication
[3] IEEE Std 1364-2005 – The official standard for Verilog
2005
[4] schawmz series, Data structure
[5] M.V.H Bhaskara Murthy (2011), VLSI
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