Mtech Syllabus 4 DSP
Mtech Syllabus 4 DSP
Unit-1
Linear Algebraic Equation And Eigen Value Problem
System of equations-Solutin by Gauss Jorden and LU decomposition method-Jacobi, Gauss-Seidal it
eration method-Eigen values of a matrix Jacobi and Power method.
Unit-2
Wave Equation
Solution of initial and boundary value problems-Characteristics-D’Alemert’s Solution-Significance of
characteristic curves- Laplace transform solutions for displacement in a long sting under its weight-a
bar with prescribed force on one end –free vibrations of a string.
Unit-3
Special functions
Bessel’s equation-Bessel Functions-Legendre’s equaton-Legender polynomials-Rodrigue’s formula-
Recurrence relations-generating functions and orthogonal property for Bessel’ functions-Legendre
polynomials.
Unit-4
Random variables
One dimensional Random variable-Moments and MGF-Binomial, Poisson, Geometrical, Normal
Distributions-Two dimensional Random variables-Marginal and Conditional Distributions-covariance
and Correlation Coefficient-Functions of Two dimensional random variable.
Unit-5
Queuing Theory
Single and Multiple server Markovian queuing models-Steady state system size probabilities-Little’s
formula-Priority queues-M/G/I queuing system-P.K. formula.
References
1.SANKAR Rao. K. “ Introduction to Partial Differential Equation” PHI,1955
2.Taha.H.A “Operations Research-An Introduction” 6th Edition,PHI,1997
3.Jain M.K.Iyenger,S.R.K.and Jain R.K. “ International Methods for Scientific and Engineering
Computation,” New Age International(P) Ltd, Publishers 2003.
4.Kanpur J.N.andSaxena.H.C. “Mathematical Statistics” ,S.Chand and Co, New Delhi,2003
5.Greweal B.S. Higher Engineering Mathematics , Khanna Publishers,2005
10MEC102 ADVANCED DIGITAL COMMUNICATIONS
4 Hrs /Week
UNIT-1
Digital Modulation Techniques : QPSK, DPSK, FQPSK, QAM, M-QAM, OFDM, Optimum
Receiver for Signal Corrupted by AWGN, Performance of the Optimum Receiver for Memory-less
Modulation, Optimum Receiver for CPM Signals, Optimum Receiver for Signals with Random Phase
in AWGN Channel.
UNIT-2
Coding Techniques : Convolution Codes, Hamming Distance Measures for Convolution Codes ;
Various Good Codes, Maximum Likelihood Decoding of Convolution Codes, Error Probability with
Maximum Likelihood Decoding of Convolution Codes, Sequential Decoding and Feedback Decoding,
trellis Coding with Expanded Signal Sets for Band-limited Channels, Viterbi Decoding.
UNIT-3
Communication through band limited linear filter channels: Optimum receiver for channels with
ISI and AWGN, Linear equalization, decision-feedback equalization, reduced complexity ML
detectors, Iterative equalization and decoding- Turbo equalization.
UNIT-4
Adaptive Equalization: Adaptive linear equalizer, adaptive decision feedback equalizer, adaptive
equalization of Trellis-coded signals, recursive least squares algorithms for adaptive equalization, self
recovering (blind) equalization.
UNIT-5
Spread Spectrum Signals for Digital Communication: Model of Spread Spectrum Digital
Communication System, Direct Sequence Spread Spectrum Signals, Frequency – Hopped Spread
Spectrum Signals, CDMA, time-hopping SS, Synchronization of SS Systems.
UNIT-6
REFERENCE BOOKS:
2. Stephen .G.Wilson, “Digital Modulation and Coding”, Pearson Education (Asia) Pte.Ltd, 2003
5. J Das, P.K. Chatterjee, S.K. Mullik, “Principles of Digital Communication”, New Age International
(p) Limited.
10MECR103 Digital Signal Processing 4hrs/week
Unit 1:
Review
FFT-decimation in time and frequency, z-transform, sampling, quantization, ADC and DAC;
IIR and FIR systems;
Unit 2:
Information Theory
Unit 3:
Effects of finite word length in digital systems
Unit 4:
Implementation of discrete systems
Structures for FIR systems- direct form, cascade form, frequency sampling and lattice
structures; Structures for IIR systems- Direct form, Signal flow graphs and transpose forms,
cascade forms, parallel forms, lattice and lattice-ladder structures; Round off effects in
Digital filter sturctutes;
Unit 5:
Design of Digital Filters
Design of FIR- symmetric and anti-symmetric FIR filters, Linear pahse filters using windows
and frequency sampling; FIR differentiators; Least square method- Pade approximation, FIR
Least Squares Inverse (Wiener) Filter;
Unit 6:
Prediction
Suggested Reading
1. Digital Signal Processing- Proakis, Pearson Education
10MEC104 – INTRODUCTION TO VLSI 4HRS/WEEK
TOPICS
ASIC Design flow: overview of the entire flow from architecture to the fab, introduction to RTL,
functional verification, standard cell approach, standard cell libraries, synthesis, P&R, timing closure,
formal verification, physical verification, tapeout.
Comparison of different types of designs: custom circuits, memories, general purpose and high speed
IOs, analog circuits, programmable logic arrays, field programmable gate arrays.
Basic manufacturing process: silicon wafer, photolithography, process steps, design rules, packaging,
technology trends
CMOS Basics: Diode, MOSFET transistor, static behavior, dynamic behavior, power, energy,
technology scaling, second order effects.
CMOS circuits: Introduction to Static CMOS design, parasitics, sequential circuits (latches, flops,
timing parameters, design tradeoffs).
Multi-million gate SoC Design: Putting it all together - designing a large complex SoC in today’s
world.
Future trends: an exciting future for VLSI engineers, carbon nanotubes, 3D chips, wireless on-chip.
REFERENCE BOOKS
1. “Digital Integrated Circuits” by Jan M. Rabaey, et. al. (Pearson Education (Singapore) Pte. Ltd.,
2007)
2. “Application Specific Integrated Circuits” by Smith (Pearson Education (Singapore) Pte Ltd,
2008)
LAB / PRACTICAL
Lab exercises will give students a hands-on introduction of the VLSI domain. Students will get
exposure to basics of Circuit design, ASIC flow and RTL and Verification. Some basic spice
simulations and hands on exposure to some industry standard VLSI tools will also be given. Labs will
include:
1. Custom schematic creation of basic CMOS combinatorial gates
2. Custom layout of basic CMOS combinatorial gates
3. Spice simulations of basic CMOS combinatorial gates
4. Verilog code for basic logic gates, state machines.
5. A simple testbench to test and verify this.
6. Take a small block from RTL -> gds2 using P&R tools.
LAB REQUIREMENTS
1. Spice Simulator
2. Cadence ICFB schematic capture tool
3. Cadence Virtuoso layout
4. Verilog
5. Synopsys VCS
6. Synopsys P&R tool suite
10MEC107 DSP PROCESSOR ARCHITECTURE AND PROGRAMMING
4hrs/week
UNIT-1
Multiplier and Multiplier accumulator (MAC) – Modified Bus Structures and Memory access in
Programmable DSPs – Multiple access memory – Multi-port memory – VLIW architecture-
Pipelining –
Special Addressing modes in P-DSPs – On chip Peripherals.
UNIT-2
TMS320C3X PROCESSOR
Architecture – Data formats - Addressing modes – Groups of addressing modes- Instruction sets -
Operation – Block Diagram of DSP starter kit – Application Programs for processing real time signals
–
Generating and finding the sum of series, Convolution of two sequences, Filter design
UNIT-3
ADSP PROCESSORS
Architecture of ADSP-21XX and ADSP-210XX series of DSP processors- Addressing modes and
assembly
language instructions – Application programs –Filter design, FFT calculation.
UNIT-4
UNIT-5
.
REFERENCES