MOSFET SWITCHING BEHAVIOURUNDER INFLUENCE OF PCB STRAY JNDUCTANCE

W. Teulings, J.L. Schanen, J. Roudet

Laboratoire d’Electrotechnique de Grenoble, CNRS-INPGIUJF UMR 5529

ENSIEG, B.P. 46, 38402 SMH, Grenoble Cedex, FRANCE

Abstract- An analytical expression is derived for the power been derived from the combination of the stray inductance
MOSFET turn-off overvoltage, including the influence of PCB model and the MOSFET model. In section 5, this expression
interconnects. The entire PCB is modeled by means of the is first verified by comparison with experimental results and
Partial Element Equivalent Circuit (PEEC) method. The PCB then used to separately study the influence of PCB track
mod41 associated with a simple MOSFET model permits to
compute maximum overvoltage with good precision. This
inductance and MOSFET switch-off speed on the
expression can be used to design PCBs and choose a type of overvoltage. The conclusion is contained in section 6 .
MOdFET respecting MOSFET maximum voltage ratings. The
analftical expression has been verified by breadboard
experiments. 11. MOSFET
MODEL

I. INTRODUCTION
The MOSFET under consideration makes part of a Switched
The extremely fast switching speed of the power MOSFET Mode Power Supply usually called chopper.
leads to self-inflicted voltage transients during switching due
to the stray parasites of the interconnects. In power electronics
applications, the interconnects generally consist of Printed
Circvit Board, component leads, cables and wires. The
problems that these interconnects cause are often dominated
by stray inductance rather than by stray capacitance, L load= 250m H
B M 08PI 400
especially in low- and medium voltage Switched Mode Rload = 20 R
Power Supplies.

The aim of this article is to study MOSFET switching

behaviour under influence of stray inductance for a simple IRFP 450
f=100 wz
chopper mounted on a Printed Circuit Board (PCB). This W.41
chopper is the most basic example of a commutating power
conv,erterwhich can be extended to more complex converter
topologies.
Although the MOSFET switching behaviour is influenced Fig. 1. Chopper Crcuit
by stray inductance both at turn-on and turn-off, only the
tum-pff behaviour is studied here because only at turn-off the
drairl-to-source voltage may exceed the. maximum voltage At turn-on of the MOSFET, the drain-source voltage will
rating of the MOSFET. A closed form expression for the drop, and no overvoltage will be produced. This situation is
maximum MOSFET turn-off overvoltage is derived from a not critical, and will therefore not be studied in this article.
simple MOSFET model and an accurate model of the stray Directly after turn-off the load current continues to flow
inductance of its electrical environment. through the MOSFET, but the drain-source voltage starts to
The MOSFET model includes turn-off switching speed, rise. When the voltage across the freewheeling diode rises, an
current amplitude, drain-to-source capacitance (C,,,), lead increasing fraction of the load current will be diverted to it.
inductances and internal drain resistance. The decreasing drain current in which this results then
The stray inductance is computed by means of the Partial generates a negative voltage across the inductance of the
Elenient Equivalent Circuit (PEEC) method [4-71. It is MOSFET drain lead. The internal MOSFET drain voltage
obtained in the form of an electrical equivalent circuit can thereby rise to a value largely superior to the supply
automatically generated by a special purpose CAD tool called voltage, and even above the maximum voltage rating. Many
INCA (INductance CAlculation) [8-111. modem power MOSFETS are designed so that the body-
drain diode junction provides a controlled avalanche
The expression can be used to analyze the influence of capability within the device itself, but otherwise an external
di/dt, stray inductance and type of MOSFET on the zener diode must be connected as closely as possible to the
overvoltage. This can help designers to meet maximum transistor to prevent it from suffering an overvoltage.
voltqge ratings and evaluate PCB layout designs. It may also be unacceptable from an EMC point of view to
The ‘paper is organized as follows. In section 2, the simple have an overvoltage above a certain value, because the ever
MOSFET model used in this paper is presented, and its present parasitic capacitance between the drain and ground
relationship with other MOSFET models. Stray inductance will result in Common Mode currents [l I].
modeling with the PEEC method is discussed in section 3. In fig. 2 , a typical MOSFET turn-off voltage waveform is
In section 4, an analytical expression for the overvoltage has displayed.

0-7803-3544-9196 $5.00 0 1996 IEEE 1449

 LD
Drain myS, ,

-
f
‘2 20 4
II
VDS

Source
i ci
4LI
R DLS
Tsink

Fig. 3. MOSFET model for turn-off

In fig. 3, L d m i n and LSOuree

represent the lead inductances [9].
CO,, is obtained from datasheets at maximum Drain-Source
Fig.2.Typical MOSFET turn-off voltage voltage. The current source in parallel with CO,,represents the
turned-off current. Its parameters are the amplitude of this
current and the turn-off switching time TSlnk.In series with
CO,, a resistor RD is included in order to represent damping of
the voltage ring. Its value is not very critical, but must be
Once the Drain-Source voltage has reached the supply taken between 0 and RgateQ, Rgatebeing the gate drive
voltage (V=120 V in fig. 2), an oscillation is set up between resistance. In [1,2], the phase during which the drain current
the drain-to-source junction capacitance CO,,and the stray decreases and the phase after which the drain current has
inductance (ringing effect). The maximum overvoltage occurs become zero are studied separately. The phase of decreasing
at the first peak of the ringing phase. drain current is called interval 3, and the phase during which
the drain current is completely OFF interval 4. During
interval 3, $,, contributes to the discharge of the so called
‘Miller’ capacity of the MOSFET. This capacity is
incorporated in C,,,. During interval 4 however, the
In order to derive an analytical expression for the MOSFET is completely decoupled from Rgate,and an
overvoltage produced at tum-off, a simple MOSFET model is oscillation is set up between CO,,and the stray inductance.
needed that must include essential design-parameters such as The MOSFET model of fig. 3 relies in fact on a
turn-off speed, current amplitude, drain-to-source capacitance combination of the models of interval 3 and 4 such as
CO,,and lead inductances Ldrain and L,,,. proposed by [ 1,2].
Several MOSFET models have been proposed in literature
which have in common that both the turn-on and turn-off 111. STRAY MODEL
INDUCTANCE
proces are subdivided into a number of separate intervals for
which different constraints and conditions apply. The end- The stray inductance of the underlying chopper has two
condtions for one interval become the starting conditions for contributions : one from the PCB tracks and one from the
the next [ 1,2]. In order to know the drain current and voltage component leads. In order to model stray inductance, several
at the end of tum-off, all preceeding phases have to be solved. methods exist, each one with its specific field of applications
In [3], the MOSFET is represented by an electrical equivalent PI.
circuit the topology of which varies over the turn-off phase. The Partial Element Equivalent Ciruit (PEEC) method
Therefore, these models can not be used to obtain a simple [4,5,6,7]attributes to each part of a conductive structure a
MOSFET tum-off model. certain amount of self partial inductance and resistance,
uniquely determined by the geometry of that particular part.
The case of uniform current distribution across the
conductor’s cross-section will be treated first.
The self partial inductance can directly be computed from
In practice, it can be observed that at turn-off, the drain its geometrical dimensions. The presence of other conductors
current only starts to drop after the moment at which the is taken into account by means of mutual partial inductances.
drain-to-source voltage has risen to the complete supply If the distance between two particular conductors is modified,
voltage. This implies that the junction capacitance CO,, is only their mutual partial inductance has to be recomputed,
already charged at the supply voltage before current tum-off. and not their self partial inductance. Furthermore, if these two
The value of CO,,is strongly voltage dependent at low drain- conductors make part of a loop, only the mutual inductances
to-source voltages, but quickly decreases towards a constant of these two conductors with the others have to be
value above 25 V for most power MOSFETS [2]. From this recomputed, but not the self- and mutual inductances of the
observation it can be concluded that during the whole ringing other conductors.
phase, Cossremainsconstant at a value that can be obtained
from datasheets. Since overvoltage always occurs within the Each part of the conductive structure is also represented by
ringing phase, it is possible to employ the relatively simple a series connection of an inductor L and a resistor R, coupled
MOSFET model of fig. 3. to the other parts by means of mutual inductors M. The

1450
value3 of these self - and mutual partial inductances are At the left side of the PCB of fig. 4, decoupling - and input
obtained from exact analytical expressions. In [121, exact filter capacitors with low Equivalent Series Inductance have
expressions for the self- and mutual partial inductances been mounted to by-pass the stray inductance of the power
between two rectangular bars are given. These expressions are supply wires.
valid under quasi-static conditions, and suppose uniform In fig. 5 , the electrical equivalent circuit as obtained by
current flow across the bar’s cross-section. They remain valid Inca is displayed.
when the length of the bars becomes short compared to their
other dimensions, contrary to the expression for inductance
used by the Transmission Line method that represents the
per-unit-length inductance [5].
With the PEEC method, non-uniform current distributions
over the conductor’s cross section are handled by partitioning
the conductor into smaller subconductors. Each subconductor
is then represented by means of its own L-R series
connection. The L-R series connections of all subconductors
can be put in parallel to compute the effective inductance of
that conductor. Since the ‘sw’inductances within the
conductor are also internally coupled, the frequency effects are
in fact taken into account by the conductor’s internal cross-
talk.

C A D tool I n c a (Inductance Calculation) is an

implementation of the PEEC method. It permits the 3D
modeling of interconnections as encountered in power
electTonics applications. Skin- and proximity effects are
accounted for by the above mentioned subdivision process.
The self- and mutual partial inductances can be grouped
together in one single inductor when the corresponding 0.62nH
conductors are connected in series. This can be useful for the 8 . 6 - 1 3.7m
~ n 0.42 m R
study of commutating current loops as often encountered in
power electronics applications.
The partial inductors and resistors can also be
autoniatically put in a netlist readable by SPICE. In this Fig. 5. Electrical Equivalent Circuit of the PCB
way, it is possible to perform simulations of power converters
that idclude the influence of the interconnections. Due to the presence of the groundplane, most mutual partial
inductances between the tracks are negligible.
It is expected that at MOSFET turn-off, oscillations up to
IV. OVERVOLTAGE
COMPUTATION
lOOMHz will occur. Since at these frequencies, the skin-effect
By cambination of the MOSFET model of section 2 with the has fully developped, all tracks have been subdivided in 10
stray inductance model of section 3, an analytical expression subconductors. Further subdivision does not substantially
for the MOSFET overvoltage at turn-off can be derived. decrease the value of track inductances.
The chopper of fig. 1 has been mounted on a PCB with The tracks undergoing a rapid current transition are
groundplane, displayed in fig. 4. The upper track length is 9 identified, and their self and mutual partial inductances are
cm, the track width is 1 cm and the groundplane (not combined into Limp, These tracks are marked in light-gray in
displayed) is situated at a distance of 1.5 mm from the tracks. fig. 4. Due to the presence of the groundplane, the total track
inductance only slightly varies with frequency
(Lloop= 23.6 nH at 0 Hz and Lloop= 22.7 nH at 100MHz).
Limp together with the lead inductances of the MOSFET and
the Diode constitute the total stray inductance. Note that in
fig. 5, the center inductances of 1,6 nH are coupled by means
of a mutual partial inductor of 0.12 nH (M=120 pH), because
the corresponding tracks have been defined in the same
direction. The resistance is found by adding up all partial
resistors of the loop tracks into Rlmp.
The inductances of the MOSFET drain- and source leads
have been evaluated elsewhere [9] and are taken as follows :
L, = 5 nH, L, = 15 nH. For the diode leads L,,,,, and
LKAmODE has been found : LA=LK= 10 nH.

By combination of the MOSFET model developped in

section 2 with the stray inductances, the electrical equivalent
circuit of fig. 6 is obtained. For the purpose of overvoltage
computation, it is possible to represent the tum-off process by
Fig.4. Printed Circuit Board for the Chopper. this equivalent circuit.

1451
 with 6= -F
Rt C
2 L'
wo= -
"
and I+V= arc cos(^)

With (4), maximum overvoltage can be predicted from design

parameters and PCB dimensions.

v EXPERIMENTAL
RESULTS AND APPLICATIONS

Fig. 6 . Model of the tum-off process. A. Experimental Results

From fig. 6, it is found that for AVDs(s), the MOSFET's For the chopper configuration of fig. 1 mounted on the PCB
external overvoltage, holds: of fig. 4, the following parameters apply : LloOp= 22.7 nH,
CO,,= 105 pF, RD= 1.75 Rloop=10.15 ma, I o = 4.5 A, a,
T s i n k= 13 ns. Equation (4) then yields :
A VD,(T,,,,k) = 27.48V.
[I+ M S ]
By inverse Laplace transformation of (2), the theoretical
AVos(s) = Rl
L overvoltage is obtained that can be compared to breadboard
measurements. In Fig. 7, the overvoltage computed from (2)
Iboop Iboop x i n k
(dashed line) is compared to the overvoltage measured across
. [(I - e - Tsink
~ XI+ -)- the MOSFET leads (solid line).
Ls L

In which : L = L,,,,+L,+L,+LD+L,, C = CO,,,and

R, = Rloop+RD.
In practical situations, this expression can be
simplified to :

r 1

This is just the sum of two responses of a second order

system ; one starting at t=O and one starting at t=Tsink.For
fast switching, the maximum overvoltage occurs before the
moment at which the current is completely OFF. In that case, I
-20 -I
Tpeak,the time instant at which maximum overvoltage is o c
o
n
o
-
0c 0
n 8 ~ 0 0 0
produced, can be found from (2) by only taking the first term,
time (ns)
applying the identity f(t) es F(s)-f(o'), and setting the
time-derivative to zero. In this way, it is found that for Tpak
approximately holds : Fig.7. Measured and Computed MOSFET Overvoltage.

I).

(3) The maximum measured overvoltage is about 28 V, which

is in good agreement with the computed value of 27.48 V.
The theoretical oscillation frequency fo= 63MHz is also in
good agreement with the measured frequency of 64.8MNz.
After inverse Laplace transformation of (Z), and substituting
(3) for Tpeak,it is found that for the MOSFET maximum
overvoltage at tum-off approximately holds : B. Application of the Expressionfor Overvoltage

Io (Lioop+LA + L K ) In order to separately study the influence of stray inductance

A VDS(Tpeak) = and switch-off speed on the overvoltage, (2) can be used
zink again.
r 1
In fig. 8, overvoltage is displayed as a function of the track
inductance, taking the same lead inductances as before and a
switch-off time Tsink = 13 ns.

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 MOSFET turn-off overvoltage Increasing the turn-off speed (decreasing Tsink) increases the
MOSFET turn-off overvoltage. This could be expected since
overvoltage depends on di/dt. From fig. 9 it can also be seen
that Tpeakis independent of the Tsink,since all maxima of the
overvoltages occur at the same time instant.

CONCLUSION

An analytical expression for the power MOSFET turn-off

overvoltage has been derived. The model includes essential
design parameters of the MOSFET itself as well as an
accurate model of the stray inductance of its environment.
The expression has been applied to an elementary chopper
502-0 configuration, the stray inductance of which is constituted by
L (nH) 40 0 time (ns)
a Printed Circuit Board. Comparison with breadboard
measurements indicate a satisfying precision. The expression
can be a valuable tool for power circuit designers wishing to
include stray inductance as a parameter in their design.
Fig. 8. Overvoltage as a function of stray inductance.

Increasing the track inductance clearly increases the maximum

overvoltage, and decreases the oscillation frequency. It is REFERENCES
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1995
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