LOGIC FAMILIES

The two basic classes of logic gates are TTL gates based on bipolar transistors and CMOS logic
gates based on MOSFET transistors. Within these classes, however, there are logic families.
The chips within each logic family offer mostly all the same digital logic functions as identified
by their standardized 74xxx part numbers, and all use the same standardized chip pinouts. The
logic families differ from each other primarily in output current capability, power dissipation,
propagation delay time, and operating power supply voltage.

A list of most of the currently available logic families and their key specifications is given
below:

There are common meanings to some of the letters in these logic family name acronyms:
A means advanced F means fast
H means high speed S means Schottky technology
C means CMOS L means low power and/or low voltage

Logic families that use Schottky technology (like LS and ALS) have a Schottky diode inserted
between the collector and base of their transistors:

The Schottky diode, with its low 0.3V turn-on voltage, prevents the transistor from going too far
into saturation. This greatly reduces the turn-off time of the transistor, thereby improving the
speed of the circuit.

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As chip-making technology improved, new logic families were introduced with improved
specifications, obsolescing some of the older families. The chart below provides a timeline
showing the order in which newer families were introduced:

Note that some of the newer families combine bipolar and CMOS transistors on the same chip
(BiCMOS). Also, most of the newest logic families are low voltage chips that require power
supplies of 3.3V or less and hence have very low power dissipation. This is in response to the
increasing demand for portable digital devices like cell phones and iPods that must run on
batteries.
One of the primary tradeoffs in designing the chips in the various logic families is between
power dissipation and speed (propagation delay time). The allowable power dissipation in turn
limits the output current capabilities of the chip. Thus a useful comparison between families can
be made by plotting the families on a graph of output current versus speed:

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The power dissipation of CMOS chips is a bit difficult to pin down because they dissipate
virtually no power in their quiescent state when the input and output logic levels aren’t being
switched. However, the power dissipation rises rapidly and the switching rate increases, and can
even exceed the power dissipation of bipolar chips at very high switching frequencies:

A further complicating factor is that CMOS gate power dissipation depends critically on the
number of other inputs an output is driving. Although the DC input current of a CMOS gate is
zero, it looks like a capacitance, which must be charged or discharged every time the logic level
switches, thus drawing AC current.

INTERCONNECTING LOGIC FAMILIES

If necessary, chips from any of the 5V bipolar TTL logic families can be mixed in the same
circuit, and the same is true for the 5V CMOS logic families. Mixing CMOS and TTL logic
chips in the same circuit requires some care, however. The problem is that the threshold voltage
for switching logic levels is different for bipolar and CMOS circuits:

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 While going from a CMOS output to a TTL input is no problem, the lower logic level switching
threshold of TTL outputs is a problem for CMOS inputs. To a large extent this problem can be
alleviated by adding a pullup resistor between the TTL output and the CMOS input, but this adds
components and draws extra current.

A better approach when CMOS and TTL logic is mixed in the same circuit is to use CMOS chips
from the ACT or HCT families. These are CMOS chips with inputs that have the TTL
compatible switching thresholds.

A handy table showing what can be mixed with what is shown below:

A – use pullup resistor to +5V

Two logic families that haven’t yet been discussed are shown here, the CD4000B family and the
74Cxxx family. The CD4000B series are very low power CMOS logic chips that can operate on a
power supply voltage of anywhere from +3V to +18V, and thus are widely used in battery powered
applications. The 74Cxxx family has nearly identical specifications, but the chip pinouts conform to
those of all the other 74xxx logic families, while the CD4000B series don’t.

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 SEQUENTIAL (CLOCKED) LOGIC

The digital logic devices and circuits considered so far have all been asynchronous
(combinational) circuits, which means that when the input logic states change, the output logic
states change immediately (except for propagation delays), and the circuits have no memory of
any previous state.

In principle, you can build up arbitrarily complex logic circuits using combinatorial logic.
However, in practice you run into huge problems from glitches (very short unwanted pulses on
logic circuit inputs or outputs). This is due to the fact that a logic gate’s output can change
depending on the relative arrival time of logic level transitions at its inputs, and the arrival times
depend on the propagation delay times of preceding gates, which will vary from one sample of a
gate to another.

Furthermore, immediately after a gate changes its output, noise spikes and glitches with
amplitudes of a volt or more can appear on the output due to crosstalk from adjacent signals, and
reflections returning from the ends of long wires. If the gates driven by this output also change
immediately, they may briefly see an incorrect logic level.

The cure for the problems with asynchronous logic circuitry is to use sequential or clocked logic.
In these circuits, changes in logic gate outputs are not allowed to propagate unconstrained
throughout the entire circuit. Instead, logic level changes can only progress through the circuitry
one stage at a time under control of a clock (a square wave oscillator circuit that produces
regular, equally spaced pulses). Between the clock pulses that cause changes to take place, the
temporary state of the system is stored in memory elements called flip-flops.

With clocked logic, the gates in the system all change their outputs at the same time, with the
changes depending only on the state of the gate inputs just before each clock pulse. . This allows
the gate outputs to settle down between clock pulses so that only valid logic levels are present
when the next clock pulse comes along.

The use of clocked logic produces circuits that have high noise immunity and that operate with
incredible reliability.

In order to create digital logic circuits that have memory, we need a device that can store bits
(binary digits, 0’s or 1’s) as logic levels, and allow those values to be read out at a later time.
The basic type of circuit that can do this and thus provide memory is the latch or flip-flop.

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 SR LATCHES

A latch is a digital logic device that can store one bit as a high or low output. The most basic
variety is the set-reset (SR) latch. It can be made from a pair of logic gates whose outputs are
cross-coupled as shown below:

To see how the device works, suppose that the Set input is momentarily pulled low (while
Reset remains high). The Q output from the upper gate is then forced high (because the output
goes high if either input 1 or input 2 goes low). Since the Reset input to the lower gate is high
also, neither input of the lower gate is low and hence the Q output is low. This forces the
second input of the upper gate low so that its output remains high even when the Set input
returns to a logic high.

Thus the Q output of the latch stays high (and the inverted Q output, Q , remains low). When
the latch is in this state it's said to be set. The latch can be placed in the cleared or reset state by
momentarily pulling the Reset input low (while Set remains high). This forces the lower gate's
output to be high, causing the upper gate's output (and hence Q ) to be low.

SR latches are commonly used to debounce mechanical switches. We often want to use a
mechanical switch as an on-off digital input signal. The problem is that the pole of a
mechanical switch is a flexible metal leaf, and when it’s closed to make contact with the throw, it
bounces, making and breaking contact several times over a period of about a millisecond.

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We can solve this problem by connecting an SR latch to the switch:

Now the first time the pole makes contact with the throw, the latch is set or reset, and subsequent
bounces have no effect. Note that in this circuit diagram the gates making up the latch are shown
using positive logic.

TRANSPARENT LATCHES

The simple SR latch is a useable memory device, but it doesn’t qualify as a proper clocked logic
memory element because it only responds to input pulses, and doesn’t by itself store input logic
levels. In addition, if both Set and Reset are low at the same time, a disallowed state in which
the output is indeterminate occurs. However, the addition of two NAND gates and an inverter
will fix those deficiencies:

This configuration is called a transparent latch and it is now a proper memory element because it
will store the logic level of the D line and do so only when a positive clock pulse occurs.

Transparent latches are useful for a number of purposes and are available in several versions,
such as the 74375 which has four latches in a single package. However, for many applications,
the transparent latch has the drawback that its outputs follow the state of the D input line during
the entire time the clock line is high. While this period can be made quite brief, the ideal would
be to have a clocked logic element whose output can change only at a single, known instant of
time.

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 FLIP-FLOPS

D-type flip-flops approach the ideal memory element behavior. These devices store the state of
the data line at the instant the clock signal makes a transition from high to low (or low to high)
and ignore it otherwise.

To get this behavior, the output of a transparent latch circuit is connected to a second latch in a
master-slave arrangement.

When the clock pulse goes high, the state of the D line is stored in the master latch. If the state
of the D line changes during the time the clock pulse is high, the state of the master latch will
follow, but at the instant when the clock goes back low, whatever state the master latch is in will
be captured in the slave latch, and that state cannot change again until the next falling clock
edge.

This master-slave arrangement is called a D-type flip-flop.

The most common flip-flop design is that of the 7474 edge-triggered D-type flip-flop, whose
circuit diagram is shown below:

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Here direct Set and Clear inputs have been added that override the D and CLOCK inputs to
instantly set or clear the flip-flop. Also, in this particular circuit arrangement, it’s the
rising edge of the clock that stores the state of the D line in the slave latch.

The truth table for an edge-tiggered D-type flip-flop like the 7474 is

The standard mode of operation for a D-type flip-flop is to have the Set and Clear inputs high
(not active), so that a rising edge of the clock input stores the value of D into Q , and its inverse
into Q . The clock transition is required; D can do anything it wants to, but nothing happens to
Q and Q until a positive edge occurs on the clock line.

The direct Set and Clear inputs behave just like the Set and Reset lines of a simple SR latch.
They're typically used to place the flip-flop into a known state at times such as when the power is
turned on.

Flip-flops are so widely used that they have been given their own circuit symbol. If there is a
little triangle at the clock input, it means that the flip-flop is edge-triggered.

Flip-flops, along with tristate output circuits are arguably the two most important elements in
modern digital logic systems. Without them, reliable, clocked logic systems such as
microprocessors would be virtually impossible to build.

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Arrays of flip-flops are used in many places in computer systems. They form the heart of CPU
registers, static RAM memory, and parallel output ports. Flip-flop arrays are also available as
digital logic ICs, such as the 74374:

Another common variety of flip-flop is the JK flip-flop, which has two data input lines.

If J and K are both low, the output is held constant, but if either J or K is high, a rising clock
edge will set or clear the flip-flop. The unique feature of this flip-flop is that if J and K are both
held high, the output will toggle back and forth between high and low on every rising clock edge.

FREQUENCY DIVIDERS

Since the output of a D-type flip-flop only changes on the rising edges of the clock input,
connecting Q back to the D input causes a square wave of frequency f at the clock input to
produce a square wave of frequency f/2 at the Q output.

A JK flip-flop will produce the same behavior if it’s put into its toggle mode by pulling the J and
K inputs both high.

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If two or more flip-flops wired as shown above are connected by wiring each Q output to the
clock input of the following flip-flop, we can create a frequency divider whose output frequency
is f/4, f/8, f/16, …

By adding appropriate logic between the flip-flops, we can also make frequency dividers that
produce frequencies of f/N, where N is any integer. For example, the circuit below divides the
input frequency by a factor of 3:

COUNTERS

One of the most useful applications of a set of flip-flops wired together as a frequency divider is
to make a counter.

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The circuit above is a counter that counts the number of clock pulses coming into the CLK input,
and makes the count available as a 4-bit binary number Q Q Q Q on the output lines. When
3 2 1 0
the counter reaches its maximum count value of 11112 (=1510), the count rolls over to 0000.

The counter circuit shown above is called a ripple counter because changes at the output of the
first flip-flop must ripple through to subsequent flip-flops. For example, when the count
increases from 0111 to 1000, it will take three flip-flop propagation delay times for all four flip-
flops to be properly updated. As a result, there are brief times when the count value on the
Q Q Q Q output lines is incorrect.
3 2 1 0

The invalid count problems of ripple counters can be cured by adding extra circuitry that
performs carry-lookahead. This logic causes all the flip-flops to be updated at the same time
whenever there is a carry bit that must be propagated to subsequent flip-flops. Counters
designed in this manner are called synchronous counters:

By adding still more logic around a counter’s flip-flops, they can be made to count up or count
down. The 74193 is such a device. It has carry and borrow outputs so that it can be cascaded to
form 8-bit or larger counters, and the flip-flops can be loaded with a 4-bit value at any time using
4 data input lines and a load signal.

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The latter feature allows the 74193 to be used as an f/N frequency divider. For example, to get a
divide-by-13 circuit, connect the Carry output to the Load input and hardwire the data inputs
to load the counter with 0010 when the Carry signal occurs.

SHIFT REGISTERS

By connecting the Q outputs to the D inputs of several D-type flip-flops, and driving them with a
common clock signal, we can make a shift register.

With this circuit, the 0 or 1 stored in each flip-flop gets transferred to its neighboring flip-flop on
the right each time a rising clock edge occurs.

Shift registers can be used to generate time delays that are N clock periods long, where N is the
number of flip-flops in the shift register—a rising edge at the D input will appear N periods
0
later at the output.

The most commonly available shift registers are either serial-in/parallel-out shift registers or
parallel-in/serial-out. In the first type, provision is made to allow a binary number that has been
shifted into the flip-flops one bit at a time to be read out of the flip-flops in parallel:

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A parallel-in/serial-out shift register does the reverse process. A binary number that has loaded
in parallel into the flip-flops is shifted out of the serial output line one bit at a time by clock
pulses:

Together, these two types of shift registers form the heart of a serial communications link. The
transmitting device loads binary data into a parallel-in/serial-out shift register, and transmits it
one bit at a time down a wire to some other device. The receiving device shifts the data bits into
a serial-in//parallel-out shift register as they arrive, and reads the binary data out in parallel.

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 ONE-SHOTS

There are a number of digital circuits in which we need to generate pulses of a fixed length to
create time delays or to gate other signals. A digital circuit that can do this is the one-shot, more
formally known as a monostable multivibrator.

The heart of a one-shot is an RC circuit whose output goes to a comparator:

In this simple circuit an AND gate is being used as a comparator.

Commercial ICs such as the 74121 implement this idea properly and provide several different
inputs that can be used to trigger the output pulse.

Some one-shots are also re-triggerable, meaning that if a new trigger signal occurs while the pulse
from a previous trigger is still high, the output pulse will be extended in length by another pulse
width beyond the time of the second trigger signal.

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 PROGRAMMABLE LOGIC

All the various digital integrated circuits discussed above have been single function devices—
they’re multiplexers, decoders, adders, counters, one-shots, etc. Although these ICs can be put
together to create virtually any desired complex digital circuit, including even a computer’s CPU
(central processing unit), the final result may require many chips and a lot of circuit board space.
It would be much more efficient to just write down a description of the functions that the
circuitry is supposed to perform (by specifying what outputs are to be produced for any set of
input conditions) and then be able to produce a custom chip or set of chips that implements those
functions. By using PLDs (programmable logic devices) you can actually do this.
To understand how a general purpose PLD can be made, consider first the problem of how to
make a programmable circuit that can be used to build any arbitrary combinational logic circuit
(i.e., one for which a truth table can be written).
The surprising fact that makes general purpose programmable logic circuits possible is this:
Given any truth table for a combinational circuit with an arbitrary number of inputs A, B, C, …,
one can always write down a Boolean algebra equation equivalent to the truth table having the
form of a sum-of-products, i.e., having a form that looks like
Y=(A • B • C) + (A • B • C) + (A • B • C)
To create a sum-of-products equation, just find the rows in the truth table for which Y is H (or
1), write the product (AND) of the variables in each such row, and then write the sum (OR) of all
the product terms.

If there is more than one output, there will be one sum-of-products equation for each output Yi.
To clarify what's meant by this general logic equation, consider a
simple example. Suppose we need a circuit that implements the truth table shown below:

We can immediately write down the Boolean algebra equations for the circuit by looking at the
rows of the truth table and just reading off which ANDed products of the inputs produce a true
(high) value for the output. For example, from the third row of the table we see that output Y1
will be high if A is low and B is high and C is low (i.e., A • B • C ). If we OR together similar
results from each row in the table where a given output is high we get the complete set of logic
equations for the circuit:

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The fact that we can describe the output of any combinatorial circuit in a sum-of-products form
tells us that we can implement any combinatorial logic function by feeding the inputs (and
inverted copies of the inputs) into a set of AND gates followed by a set of OR gates.

This is exactly what is done in PLDs. They contain one or more sets of AND gates that feed into
a set of OR gates. Each AND gate input is connected to the signal driving it through a
programmable connection whose construction is described below.

Because the gates in PLDs have many inputs, a new notation to represent them is used:

In this notation, an input is represented by an intersection between a vertical input line and the
single horizontal line going into the gate. An "X" at this intersection means that the connection
is turned on, and the absence of an "X" means the connection is turned off (disconnected). Note
that the horizontal line going into the AND gate does not represent a physical wire. Each
intersection is a separate input into the gate.

To see how programmable connections can create a desired logic function, suppose we want to
implement the logic functions shown in the truth table above, using a pair of 4×3 AND-OR
arrays. To create the desired logic, the programmable connections would be set up as this way:

Each input line goes into a buffer, called a phase splitter, which produces both the input signal
X and its complement X . To leave an AND gate unused, you just connect both its input signals
and their complements to the gate so that its output is always low.

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 FLOATING GATE TRANSISTORS

In early PLDs, the programmable connections were fuses which could be blown by sending
high-current pulses through them. Such devices are programmable only once.

In current programmable logic devices, the fuses have been replaced by floating gate MOS
transistors. There are many variations of these ingenious devices, but the basic idea behind them
is shown below:

The device looks much like an NMOS transistor, but with the addition of thin floating gate
between the usual gate and the substrate. The floating gate has oxide layers on both sides of it,
which isolates it electrically from its surroundings.
In its erased condition, the floating gate is uncharged, and a positive voltage on the select gate
turns the transistor on so that logic signals pass through it.
To program the transistor so that it becomes an open circuit, electrons are injected into the
floating gate by applying a high programming voltage that generates hot electrons able to tunnel
through the thin oxide layer between the source and the floating gate.
As a result, electrons accumulate in the floating gate, giving it a negative charge and thus turning
the transistor off. The transistor stays turned off
when the programming voltage is removed, because the insulating oxide prevents the
accumulated electrons from leaking away (for a time period of decades!).
Some floating gate transistor versions must be erased (i.e., have the floating gate’s negative
charge removed) by exposing them to UV light for several minutes. The drawback of this
approach is that the IC must have a transparent quartz window covering the chip.
Other floating gate transistors can be electrically erased by applying a programming voltage to
the transistor's source with the select gate grounded. This allows the electrons in the floating gate
to tunnel through the thin oxide layer out to the source. New electrons aren’t injected from the
select gate because the oxide layer below it is thicker.
Floating gate transistors are also the basis for the flash memories used in your memory sticks and
MP3 players.

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 PROGRAMMABLE ARRAY LOGIC

In principle, programmable connections for both AND gate and OR gate arrays are needed to
implement arbitrarily complex logic functions, such flexibility is seldom needed in practice.
Instead, the most popular variety of PLD is the PAL, an acronym for programmable array logic.
In a PAL, the AND gate array inputs are programmable, but not the OR gate inputs.

In the simplest PALs, the OR gate output is just fed to a tristate output
buffer that can be enabled by an AND gate driven by a programmable
combination of PAL inputs. Shown below is one section of a 16L8 PAL (the part number
indicates that it has eight AND-OR array sections using 16-input AND gates with the “L”
indicating an inverter on the output ).

An obvious limitation of simple PALs like the 16L8 is that it doesn’t contain any flip-flops,
which are needed to construct the clocked logic systems. For this purpose, registered PALs are
made in which a D-type flip-flop is placed the OR gate, and a clock signal input common to all
the flip-flops is added. These PALs have part numbers such as 20R8, where the "R" means
"registered".

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The vast majority of current PALs are more flexible yet. The AND-OR array outputs are fed
into programmable output logic macrocells.

By programming the state of the two select lines S0 and S1 you can use the 4-input multiplexer
to chose a combinational or a registered output as well as to control the input/feedback
multiplexer. If the output buffer is tristated, the external I/O pin can be used as an input when S1
is high.

An example of a popular PAL containing output logic macrocells is the 22V10 (the "V" indicates
the presence of output logic macrocells). In this chip each of the 22 input lines goes to a phase
splitter, resulting in 44 inputs to each AND gate. The AND gate outputs feed 10 OR gates which
have 8, 10, 14, or 16 of the 44-input AND gates each as inputs
(for a total of 132 44-input AND gates). There are also common clock, set, and clear inputs for
the macrocell flip-flops.

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21
To program a PAL such as a 22V10 you must specify which of the approximately 6000
programmable connections must be turned on or off, which is obviously quite impractical to do
manually. Instead, PAL programming tools allow you to enter either logic equations or truth
tables, and they will then automatically determine how to program the necessary connections.

For more complex problems where flip-flop outputs need to be fed back to the inputs, the PAL
programming tools also support finite state machine models (see the PLA discussion below).

Higher circuit densities than those achievable with individual PLDs can
be obtained by using complex PLDs (known as CPLDs). These are larger ICs with 100-300 pins
that contain the circuitry for 4 to 32 individual PLDs (such as 22V10s) together with
programmable routing circuitry that allows you to interconnect those individual PLDs within the
chip.

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 PROGRAMMABLE READ-ONLY MEMORY

There are also PLDs which have fixed AND arrays and programmable OR arrays. These devices
are called programmable read-only memories or PROMs. At first glance, this seems very
strange! Why is a general purpose programmable logic device called a memory?

The answer is that the only really useful configuration for a fixed array of AND gates is to wire
them up as address decoders. In other words, the AND gates are set up so that for any given set
of input line logic states, one and only one AND gate output goes high. This is the same
circuitry used to select a memory location within a memory chip.

In a PROM, the AND gate decoder outputs are fed into OR gates by a set of programmable
connections. A simple example of a PROM is shown below:

Here that the three input lines A,B,C form a 3-bit address and are connected to eight 6-input
AND gates so that they form a 3-line to 8-line decoder. Each AND gate output has
programmable connections to a pair of OR gates such that where a connection is made, the OR
gate output will be high when the AND gate output is high. In the circuit above, the connections
are programmed to provide the same logic function shown earlier for a PAL, namely

Wherever there's a output high in a row of the truth table, we connect the corresponding AND
gate output to an OR gate input.

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From another point of view, however, a PROM is in fact nothing other than a memory. The 3-bit
address given by inputs A,B,C selects one of eight 2-bit wide memory locations, and the contents
of the selected 2-bit location appears on the two output lines.

However, unlike RAM memory based on flip-flops, PROM memory is read-only, and the only
way to change the memory contents is to reprogram the entire chip.

A major limitation of PROMs as logic elements is the fact that the number of memory locations
needed grows exponentially with the number of inputs. For N inputs you need 2N memory
locations. Thus they're generally practical only for implementing logic functions in which the
number of inputs is fairly small. In practice, the main use of PROMs is for read-only computer
memories.

PROGRAMMABLE LOGIC ARRAYS

There is, of course, a third possibility for programmable logic devices,

The use of PLAs is largely confined to situations where you need to implement complex finite
state machines. A finite state machine is a simply a block of logic containing both combinatorial
logic and flip-flops whose contents (zeros and ones) are referred to as the state variables. Taken
together, the state variables define the current state of the state machine, and the flip-flop outputs
are combined with any inputs using combinatorial logic to determine the state machine's outputs
and next state:

As the inputs change, the state variables (and hence the machine’s state and its outputs) change
in a manner determined by a set of transition rules.

The state variables and transition rules can be expressed in several different ways. A common
way that’s useful for human comprehension is the use of a directed graph in which the state
variables are represented by vertices, and the transition rules by directed lines that are labeled
with inputs and/or outputs.

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For example, consider a state machine description of what happens when you receive a telephone
call. The states are:
W – waiting for a call
A – answering the phone
T – talking (conversing with the caller)
M – taking a message
G – getting someone else to come to the phone
F – finishing the call

The transition rules are represented by the labels on the lines:

For use in programming a PLA, the transition rules are typically put in the form of if-then
statements. For example, we might have a statement that says: If the current state is 0,1,0 and if
input A changes from high to low while inputs B and C remain high, then go to state 1,0,0.

Listing a complete set of transition rules is sufficient to determine the hardware connections
needed to implement the state machine, and PLD programming software has the ability to
automatically convert transition rules into PLD hardware connections. PLAs are sometimes
called programmable logic sequencers.
State machines can be built using registered PALs, but when they are complex, they can often be
more efficiently built using the completely programmable AND-OR array in a PLA whose OR
gate outputs drive flip-flops, with provision for the flip-flop outputs to be fed back to the array
inputs.

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