UNIT-3

Classification of Logic Families

Logic families can be broadly categorized as per the following diagram

Unipolar Logic Families

Unipolar means having a single type of charge carrier. This logic family uses transistors that
have either electrons or holes(not both) as charge carriers. The most commonly used
technology is Metal-Oxide-Semiconductor(MOS). A common example is Complementary
MOS (CMOS) logic.

1) NMOS transistors conduct when a positive charge is applied to the gate terminal.
A nChannel Metal-oxide-semiconductor(MOS) transistor is one in which n-type
dopants are used in the gate region(channels). A positive voltage on the gate turns the
device ON.

2) PMOS (P-channel Metal Oxide Semiconductor Battery-Powered)

PMOS transistors conduct when a negative charge is applied to the gate terminal. A
p-channel Metal-oxide-semiconductor(MOS) transistor is one in which p-type
dopants are used in the gate region(channels). A negative voltage on the gate turns the
device ON.

3) CMOS(Complementary MOS)
In CMOS technology, both n-type and p-type transistors are used to design logical
functions. The same signal which turns ON one transistor is used to turn OFF the
other transistor.

Bipolar Logic Families

In bipolar devices, the conduction happens due to both charge carriers – electrons and holes.
Bipolar logic families use semiconductor diodes and bipolar junction transistors as the basic
building blocks of logic circuits. The simplest bipolar logic elements use diodes and resistors
to perform logic operations; this is called diode logic.

1) Saturated
In this logic, the bipolar junction transistors(BJTs) used are operated in saturated regions. This
means that both the emitter-base and collector-base junctions are forward-biased, allowing
maximum current flow through the transistor.
 i) Transistor-Transistor Logic (TTL)
Transistor-transistor logic (TTL) is a digital logic family employing bipolar junction
transistors (BJTs) to uphold logic states and facilitate switching operations.

ii) Diode Transistor Logic (DTL)

In Diode Transistor Logic, diodes are used for AND and OR operations while
transistors are used for logical inversion and amplification.

iii) Resistor Transistor Logic (RTL)

Being the pioneering logic family adopted in integrated circuits, RTL (Resistor-
Transistor Logic) circuits consist of resistors and transistors, with resistors positioned
at the inputs and transistors at the output.

2) Non-saturated
In non-saturated bipolar logic, the bipolar junction transistors (BJTs) are operated in the active
or linear region and not in the saturation region. In other words, the collector-base junction is
reverse-biased, limiting the current flow through the transistor.

i) Emitter Coupled Logic (ECL) family

Emitter-coupled logic (ECL) is a bipolar transistor logic family that is considered to
be the fastest logic available.

ii) Schottky TTL

Schottky TTL employs an internal architecture akin to standard TTL, with the notable
inclusion of Schottky transistors.

Positive Logic:

In digital electronic systems, if the high value of signal (voltage or current) is used to represent
the logic 1 and the low value of signal (voltage or current) is used to represent the logic 0, then it
is called a positive logic system.

The pulse waveform representation of a positive logic is shown in Figure-1. In the case of
positive logic, the voltage at 0 volts level represents the logic 0 (Logic LOW), and the voltage at
+VCC volts level represents the logic 1 (Logic HIGH).

Negative Logic:
In digital electronic systems, if the high value of signal (voltage or current) is used to represent
the logic 0 and the low value of signal (voltage or current) is used to represent the logic 1, then it
is called a negative logic system.

The pulse waveform representation of a negative logic is shown in Figure-2. In the case of
negative logic, the voltage at -VCC volts level represents the logic 0 (Logic LOW), and the
voltage at 0 volts level represents the logic 1 (Logic HIGH).

FlipFlop:

A flip-flop is a sequential digital electronic circuit having two stable states that can be used to
store one bit of binary data. Flip-flops are the fundamental building blocks of all memory
devices.

Basic Principle of operation of a Flip-Flop:

Flip flops are fundamental building blocks of digital circuitry that play a pivotal role in storing
and transmitting binary information. It operates with two stable states, often referred to as “set”
and “reset,” which determine its output. Flip flops play a vital role in sequential logic circuits,
memory elements, and counters, enabling the storage and manipulation of digital data.

Latch:

A Latch is a special type of logical circuit. The latches have low and high two stable states. Due
to these states, latches also refer to as bistable-multivibrators. A latch is a storage device that
holds the data using the feedback lane. The latch stores 1 -bit until the device set to 1. The latch
changes the stored data and constantly trials the inputs when the enable input set to 1.

Based on the enable signal, the circuit works in two states. When the enable input is high, then
both the inputs are low, and when the enable input is low, both the inputs are high.

NAND LATCH:

The SR latch is a sequential circuit that is used in digital logic and electronics. The SR latch has
two stable states and can store a single bit of information; the two stable states are known as set
and reset, hence the name SR. The latch also provides two outputs, namely Q and Q-bar (the
inverse of Q).
The circuit diagram

Below, we can see the circuit diagram for the SR latch.

SR latch circuit diagram

As we see in the diagram, the SR latch comprises two cross-coupled NAND gates, where the
output of one gate is connected to the input of the other and vice versa. The latch takes two
binary inputs, S and R, and produces two binary outputs, Q and Q-bar.

Formation of the truth table

Now that we have looked at the circuit diagram for the SR latch, we will not look at how the
truth table is formed by looking at the different input values of S and R.

Case 1: When S = 1 and R = 0 (SET)

The set state

The NAND gates provide an output of 1 whenever there is an 0 in the input to the logic gate. In
the case of S = 1 and R = 0, the logic gate connected to the reset input receives a 1, so it will
output a 0. That 0 will then propagate to the NAND gate connected to the set input, providing an
output of 0 as 1 NAND with 1 is 0.

So the Q values will be 1, and the value of Q-bar will be 0 showing that we set the value of the
output Q as 1.

Case 2: When S = 0 and R = 1 (RESET)

The reset state

This is the reverse of Case 1 we went through above; over here, we have reversed the inputs S
and R to be 1 and 0; hence our output for Q would then be 0, and Q-bar would be 1 showing that
we have reset the output bit Q.

Case 3: When S = 0 and R = 0 (INVALID)

The invalid state

In this case, we see that one of the inputs to both NAND gates is 0; this means that the output of
both gates will always be 1 regardless of the 2nd input to the NAND gates. Since the value of Q
and Q-bar is the same, we call this SR latch state invalid.

Case 4: When S = 1 and R = 1 (HOLD)

The hold state

This case is a bit tricky to solve as none of the inputs is 0, which means that the output depends
on the 2nd input to the NAND gates. We will try to solve this using boolean algebra, as seen in
the diagram. We see that there will be no change in already stored bits for Q and Q-bar upon
solving the equation; hence we call this state the hold state since none of the values of the output
change.

Truth table

Now that we have gone through all the different states of an SR latch, we can see the final truth
table below that shows the values of Q and Q-bar against the input bits S and R.
NOR latch

Latches are basic storage elements that operate with signal levels (rather than signal transitions).
Latches controlled by a clock transition are flip-flops. Latches are edge-sensitive devices.
Latches are useful for the design of the asynchronous sequential circuit.

SR (Set-Reset) Latch – SR Latch is a circuit with:

(i) 2 cross-coupled NOR gates or 2 cross-coupled NAND gates.

(ii) 2 inputs S for SET and R for RESET.
(iii) 2 outputs Q, Q.

The SR Latch using NOR gate is shown below with its truth table:

Figure-1:Logic Symbol of NOR gate latch

Figure-2:Truth Table of NOR gate latch

While the R and S inputs are both low, feedback maintains the Q and Q outputs in a constant
state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the
Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while
S is held low, then the Q output is forced low, and stays low when R returns to low.The R = S =
1 combination is called a restricted combination or a forbidden state because, as both NOR gates
then output zeros, it breaks the logical equation Q = Q. The combination is also inappropriate in
circuits where both inputs may go low simultaneously (i.e. a transition from restricted to keep).
The output would lock at either 1 or 0 depending on the propagation time relations between the
gates (a race condition).
 Figure-3:Timing Diagram of NOR gate latch

Difference Between Flip Flop and Latch

Flip Flop Latch

The flip-flop alters its output only when the Latch alters the output based on the changes
clock pulse is activated along with the input in input constantly.
change.

As clock signals synchronise operations of the In the absence of clocks, latches operate
flip-flop, it operates synchronously. asynchronously.

In comparison, flip-flops must have an In latches, since the output is only dependent
additional clock to ensure their operation. on the input signal applied, they do not
require the external input clock.

The need for power to allow the circuit to The need for power to allow the circuit to
work is much lower in the flip-flops, because work is much lower in the instance of latches.
there is a clock signal present.

In comparison, flip-flops, in addition to Latches work on both present/past input and

working with past and present input and output values.
output, also considers clock signals.

The analysis of circuits for flip-flops is a bit The analysis of circuits for latches is a bit
simpler than latches. more difficult.
 Flip-flops are edge triggered and thus are Latches are level triggered and thus get an
activated when the clock signal changes from activation whenever the input shifts from one
low to high or high to low. level of binary to the next.

Flip-flops consist of a latch and a clock Latches are created with logic gates.
together as one unit.

Triggering:

Triggering in digital electronics is the process of activating a switch in response to an input

signal, such as a voltage level, current change, or timing signal. When the trigger activates, it
performs an action, such as starting or stopping a process, sending a pulse, or changing the
output state.

Types of Triggering:

There are two types of Triggering.

1) Edge Triggering

2) Level Triggering

Edge Triggering Method

When the flip-flop is triggered to update its output state on the rising or falling edge of the clock
pulse, then it is called edge triggering method. If the flip-flop is triggered when the clock pulse
goes from low to high (positive edge), then it is called positive edge-triggering method. If the
flip-flop is triggered to update its output when the clock pulse goes from high to low (negative
edge), then it is called negative edge- triggering method.
Level Triggering Method
In the level triggering method, the flip-flop responds to the inputs and updates its output state
when the clock pulse is in either high level or low level. When the flip-flop is triggered to update
its output state when the clock pulse is in the logic high level, then it is called positive level
triggering. When the flip-flop is triggered to update the output state when the clock pulse is in
the logic low level, then it is called negative level triggering.

SR Flip-flop:
It is a Flip Flop with two inputs, one is S and the other is R. S here stands for Set and R here
stands for Reset. Set basically indicates set the flip flop which means output 1 and reset
indicates resetting the flip flop which means output 0. Here, a clock pulse is supplied to
operate this flip-flop, hence it is a clocked flip-flop.

The memory size of SR flip flop is one bit. The S (Set) and R (Reset) are the input states for the
SR flip-flop. The Q and Q’ represents the output states of the flip-flop.

We are constructing the SR flip flop using NAND gate which is as below,
Working of SR Flip Flop
 Case 1: Let’s say, S=0 and R=0, then output of both AND gates will be 0 and the value of
Q and Q’ will be same as their previous value, i.e, Hold state.
 Case 2: Let’s say, S=0 and R=1, then output of both AND gates will be 1 and 0,
correspondingly the value of Q will be 0 as one of input is 1 and it is a NOR gate so it will
ultimately gives 0, hence Q gets 0 value, similarly Q’ will be 1.
 Case 3: Let’s say, S=1 and R=0, then output of both AND gates will be 0 and 1,
correspondingly the value of Q’ will be 0 as one of input to NOR gate is 1, so output will
be 0 ultimately and this 0 value will go as input to upper NOR gate, and hence Q will
become 1.
 Case 4: Let’s say, S=1 and R=1, then output of both AND gates will be 1 and 1 which is
invalid, as the outputs should be complement of each other.

Here, S is the Set input, R is the reset input,Qn+1 is the next state and State tells in which
state it enters

Truth Table of SR Flip Flop

Given Below is the Truth Table of SR Flip Flop

According to the table, based on the inputs, the output changes its state. But, the important thing
to consider is all these can occur only in the presence of the clock signal.
D Flip Flop
In SR NAND Gate Bistable circuit, the undefined input condition of SET = "0" and RESET =
"0" is forbidden. It is the drawback of the SR flip flop. This state:

We need an inverter to prevent this from happening. We connect the inverter between the Set
and Reset inputs for producing another type of flip flop circuit called D flip flop, Delay flip flop,
D-type Bistable, D-type flip flop.

The D flip flop is the most important flip flop from other clocked types. It ensures that at the
same time, both the inputs, i.e., S and R, are never equal to 1. The Delay flip-flop is designed
using a gated SR flip-flop with an inverter connected between the inputs allowing for a single
input D(Data).

This single data input, which is labeled as "D" used in place of the "Set" input and for the
complementary "Reset" input, the inverter is used. Thus, the level-sensitive D-type or D flip flop
is constructed from a level-sensitive SR flip flop.

Block Diagram

Circuit Diagram

We know that the SR flip-flop requires two inputs, i.e., one to "SET" the output and another to
"RESET" the output. By using an inverter, we can set and reset the outputs with only one input
as now the two input signals complement each other. In SR flip flop, when both the inputs are 0,
that state is no longer possible. It is an ambiguity that is removed by the complement in D-flip
flop.

In D flip flop, the single input "D" is referred to as the "Data" input. When the data input is set to
1, the flip flop would be set, and when it is set to 0, the flip flop would change and become reset.
However, this would be pointless since the output of the flip flop would always change on every
pulse applied to this data input.

The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from the flip
flop's latching circuitry. When the clock input is set to true, the D input condition is only copied
to the output Q. This forms the basis of another sequential device referred to as D Flip Flop.

When the clock input is set to 1, the "set" and "reset" inputs of the flip-flop are both set to 1. So
it will not change the state and store the data present on its output before the clock transition
occurred. In simple words, the output is "latched" at either 0 or 1.

Truth Table for the D-type Flip Flop

Symbols ↓ and ↑ indicates the direction of the clock pulse. D-type flip flop assumed these
symbols as edge-triggers.

JK Flip Flop
The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it has the following
switching problems:

o When Set 'S' and Reset 'R' inputs are set to 0, this condition is always avoided.
o When the Set or Reset input changes their state while the enable input is 1, the incorrect
latching action occurs.
The JK Flip Flop removes these two drawbacks of SR Flip Flop.

The JK flip flop is one of the most used flip flops in digital circuits. The JK flip flop is a
universal flip flop having two inputs 'J' and 'K'. In SR flip flop, the 'S' and 'R' are the shortened
abbreviated letters for Set and Reset, but J and K are not. The J and K are themselves
autonomous letters which are chosen to distinguish the flip flop design from other types.

The JK flip flop work in the same way as the SR flip flop work. The JK flip flop has 'J' and 'K'
flip flop instead of 'S' and 'R'. The only difference between JK flip flop and SR flip flop is that
when both inputs of SR flip flop is set to 1, the circuit produces the invalid states as outputs, but
in case of JK flip flop, there are no invalid states even if both 'J' and 'K' flip flops are set to 1.

The JK Flip Flop is a gated SR flip-flop having the addition of a clock input circuitry. The
invalid or illegal output condition occurs when both of the inputs are set to 1 and are prevented
by the addition of a clock input circuit. So, the JK flip-flop has four possible input combinations,
i.e., 1, 0, "no change" and "toggle". The symbol of JK flip flop is the same as SR Bistable
Latch except for the addition of a clock input.

Block Diagram:

Circuit Diagram:

In SR flip flop, both the inputs 'S' and 'R' are replaced by two inputs J and K. It means the J and
K input equates to S and R, respectively.

The two 2-input AND gates are replaced by two 3-input NAND gates. The third input of each
gate is connected to the outputs at Q and Q'. The cross-coupling of the SR flip-flop permits the
previous invalid condition of (S = "1", R = "1") to be used to produce the "toggle action" as the
two inputs are now interlocked.

If the circuit is "set", the J input is interrupted from the "0" position of Q' through the lower
NAND gate. If the circuit is "RESET", K input is interrupted from 0 positions of Q through the
upper NAND gate. Since Q and Q' are always different, we can use them to control the input.
When both inputs 'J' and 'K' are set to 1, the JK toggles the flip flop as per the given truth table.
Truth Table:

When both of the inputs of JK flip flop are set to 1 and clock input is also pulse "High" then
from the SET state to a RESET state, the circuit will be toggled. The JK flip flop work as a T-
type toggle flip flop when both of its inputs are set to 1.

The JK flip flop is an improved clocked SR flip flop. But it still suffers from
the "race" problem. This problem occurs when the state of the output Q is changed before the
clock input's timing pulse has time to go "Off". We have to keep short timing plus period (T) for
avoiding this period.

T Flip Flop
In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a single input
called "Toggle" or "Trigger" input to avoid an intermediate state occurrence. Now, this flip-flop
work as a Toggle switch. The next output state is changed with the complement of the present
state output. This process is known as "Toggling"'.

We can construct the "T Flip Flop" by making changes in the "JK Flip Flop". The "T Flip Flop"
has only one input, which is constructed by connecting the input of JK flip flop. This single input
is called T. In simple words, we can construct the "T Flip Flop" by converting a "JK Flip Flop".
Sometimes the "T Flip Flop" is referred to as single input "JK Flip Flop".

Block diagram of the "T-Flip Flop" is given where T defines the "Toggle input", and CLK
defines the clock signal input.
T Flip Flop Circuit

Below is the logical circuit of the T Flip Flop" which is formed from the "JK Flip Flop":

Truth Table of T Flip Flop

The upper NAND gate is enabled, and the lower NAND gate is disabled when the output Q To is
set to 0. make the flip flop in "set state(Q=1)", the trigger passes the S input in the flip flop.

The upper NAND gate is disabled, and the lower NAND gate is enabled when the output Q is set
to 1. The trigger passes the R input in the flip flop to make the flip flop in the reset state(Q=0).

Operations of T-Flip Flop

o The next sate of the T flip flop is similar to the current state when the T input is set to
false or If toggle input is set to 0 and the present state is also 0, the next state will be 0.
 o If toggle input is set to 0 and the present state is 1, the next state will be 1.
The next state of the flip flop is opposite to the current state when the toggle input is set to 1.

o If toggle input is set to 1 and the present state is 0, the next state will be 1.
o If toggle input is set to 1 and the present state is 1, the next state will be 0.
The "T Flip Flop" is toggled when the set and reset inputs alternatively changed by the incoming
trigger. The "T Flip Flop" requires two triggers to complete a full cycle of the output waveform.
The frequency of the output produced by the "T Flip Flop" is half of the input frequency. The "T
Flip Flop" works as the "Frequency Divider Circuit."

In "T Flip Flop", the state at an applied trigger pulse is defined only when the previous state is
defined. It is the main drawback of the "T Flip Flop".

The "T flip flop" can be designed from "JK Flip Flop", "SR Flip Flop", and "D Flip Flop"
because the "T Flip Flop" is not available as ICs. The block diagram of "T Flip Flop" using "JK
Flip Flop" is given below:

Distinguish between synchronous and asynchronous inputs:

S.NO Synchronous inputs Asynchronous inputs

1 Synchronous inputs are activated by the clock Asynchronous inputs are not directly
signal connected or linked to the clock signal
2 The flip-flop’s state changes happens at They can trigger a change in the flip-flop’s
particular moments that are synchronized state at any time, regardless of the clock
with the clock signal signal
3 The flip-flop changes its state at the same When an asynchronous input is activated, it
time as the clock signal, making sure that promptly induces a change in the flip-flop’s
these changes occur at specific and well state, without needing to wait for the next
defined moments. clock edge.
4 Synchronous inputs are applied when the Asynchronous
clock pulse is high
5 Synchronous inputs will not override the Asynchronous inputs override the normal
normal clock-controlled operation. clock-controlled operation when needed.
6 Example: The inputs R,S,J,K,D,T are Example: The Clear (CLR) and Set (SET)
synchronous inputs. They synchronize with inputs in a flip-flop are usually asynchronous.
the clock signal. State changes happens When you use them, they can ignore the clock
precisely at the rising or falling edge of the signal and directly cause an ihnstant chane in
clock signal. the output.
 Need of Master-Slave Flip-Flop:

Master-slave flip-flops are used in digital systems for a number of reasons, including:

 Reliable: Master-slave flip-flops improve the reliability of digital circuits.

 Edge-triggered: Master-slave flip-flops are edge-triggered, which makes them easier to use in
larger circuits.
 Noise immunity: Master-slave flip-flops improve noise immunity.
 Sequential signal processing: Master-slave flip-flops are essential for synchronized, sequential
signal processing.
 Timing control: Master-slave flip-flops provide better timing control in complex digital systems.

Master-Slave JK Flip Flop

In "JK Flip Flop", when both the inputs and CLK set to 1 for a long time, then Q output toggle
until the CLK is 1. Thus, the uncertain or unreliable output produces. This problem is referred to
as a race-round condition in JK flip-flop and avoided by ensuring that the CLK set to 1 only for a
very short time.

Explanation

The master-slave flip flop is constructed by combining two JK flip flops. These flip flops are
connected in a series configuration. In these two flip flops, the 1st flip flop work as "master",
called the master flip flop, and the 2nd work as a "slave", called slave flip flop. The master-slave
flip flop is designed in such a way that the output of the "master" flip flop is passed to both the
inputs of the "slave" flip flop. The output of the "slave" flip flop is passed to inputs of the master
flip flop.

In "master-slave flip flop", apart from these two flip flops, an inverter or NOT gate is also used.
For passing the inverted clock pulse to the "slave" flip flop, the inverter is connected to the
clock's pulse. In simple words, when CP set to false for "master", then CP is set to true for
"slave", and when CP set to true for "master", then CP is set to false for "slave".
Working:

o When the clock pulse is true, the slave flip flop will be in the isolated state, and the
system's state may be affected by the J and K inputs. The "slave" remains isolated until
the CP is 1. When the CP set to 0, the master flip-flop passes the information to the slave
flip flop to obtain the output.
o The master flip flop responds first from the slave because the master flip flop is the
positive level trigger, and the slave flip flop is the negative level trigger.
o The output Q'=1 of the master flip flop is passed to the slave flip flop as an input K when
the input J set to 0 and K set to 1. The clock forces the slave flip flop to work as reset,
and then the slave copies the master flip flop.
o When J=1, and K=0, the output Q=1 is passed to the J input of the slave. The clock's
negative transition sets the slave and copies the master.
o The master flip flop toggles on the clock's positive transition when the inputs J and K set
to 1. At that time, the slave flip flop toggles on the clock's negative transition.
o The flip flop will be disabled, and Q remains unchanged when both the inputs of the JK
flip flop set to 0.

Timing Diagram of a Master Flip Flop:

o When the clock pulse set to 1, the output of the master flip flop will be one until the clock
input remains 0.
o When the clock pulse becomes high again, then the master's output is 0, which will be set
to 1 when the clock becomes one again.
o The master flip flop is operational when the clock pulse is 1. The slave's output remains 0
until the clock is not set to 0 because the slave flip flop is not operational.
o The slave flip flop is operational when the clock pulse is 0. The output of the master
remains one until the clock is not set to 0 again.
o Toggling occurs during the entire process because the output changes once in the cycle.