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SV Test-1

This document contains a list of 34 questions about system verification concepts in systemverilog. The questions cover topics such as the difference between initial and final blocks, simulation phases, array types, avoiding race conditions, program blocks, data types, virtual interfaces, randomization, testbenches, queues, and more. The document assigns a total of 50 marks and asks students to answer the questions as part of a system verification assignment.

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Evancy Grace N
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154 views2 pages

SV Test-1

This document contains a list of 34 questions about system verification concepts in systemverilog. The questions cover topics such as the difference between initial and final blocks, simulation phases, array types, avoiding race conditions, program blocks, data types, virtual interfaces, randomization, testbenches, queues, and more. The document assigns a total of 50 marks and asks students to answer the questions as part of a system verification assignment.

Uploaded by

Evancy Grace N
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Technospirit

Verification (System Verification) Assignment-1


50 Marks

1. What is the difference between initial and final block of systemverilog? 1m


2. Explain simulation phases of systemverilog verification? 1m
3. What is the Difference between system verilog packed and unpacked array?
2m
4. What is "This" keyword in systemverilog? 1m
5. In systemverilog which array type is preferred for memory declaration and why?
1m
6. How to avoid race round condition between DUT and test bench in systemverilog
verification? 2m
7. What are the advantages of systemverilog program block? 1m
8. What is the difference between logic and bit in systemverilog ? 1m
9. What is the difference between data type logic and wire? 1m
10. What is virtual interface? 1m
11. What is abstract class? 1m
12. What is the difference between $random and $urandom? 2m
13. What is the difference between == and ===? Explain with example? 1m
14. How to generate array without randomisation? 1m
15. What is the difference between always_comb() and always@(*) ? 2m
16. What is the difference between overriding and overloading? 2m
17. Explain the difference between deep copy and shallow copy? 1m
18. What are the basic testbench components? 2m
19. Explain the difference between new( ) and new[ ] ? 1m
20. Explain difference between fork-join, fork-join_none, and fork- join_any? 2m
21. What are the difference between mailbox and queues? 1m
22. What is circular dependency? 1m
23. What is “super“ keyword ? 1m
24. What is input skew and output skew in clocking block? 1m
25. What are in line constraints? 1m
26. What is the difference between rand and randc? 1m
27. What is the difference between $display,$strobe,$monitor ? 2m
28. Logic Variables can have multiple drivers? True /False 1m
29. What will be the output of the code? 1m

Module test;
bit[31:0] abc[*]
initial begin
abc[500]=40;
$display(“size of abc=%d”, abc.num());
end
end module

30. array[4][8] => this is array declaration of which type?


Compact declaration/Verbose declaration 1m
31. Declaration of Queue? 1m
32. Write TB Architecture? Draw and explain? 5m
33. Write the code for Full Subtractor in verilog and system verilog (using randomization)
5m
34. What is the Difference between param and typedef? 1m

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