September 22th, 2014

ESSDERC Tutorial
Venice - Italy

Future of Logic Nano CMOS

Technology

Hiroshi Iwai

Frontier Research Center, Tokyo Institute of Technology

1
 Outline

1. Brief history of logic device technology

2. Importance of downsizing
3. Current status of Si-CMOS device technologies
4. Major problems for downsizing
5. Increase of leakage current when downsizing
6. Degradation of on-current when downsizing
7.Emerging technologies
8.Sumamry and conclusions
Acknowledgement
Appendices 2
1. Brief history of logic
device technology

3
1900 “Electronics” started.

4
 Electronic Circuits started by the
invention of vacuum tube
(Triode) in 1906

Thermal electrons from cathode

controlled by grid bias
Lee De Forest

Cathode Anode
(heated) Grid (Positive bias)

Same mechanism as that of transistor

1900 “Electronics” started.
Device: Vacuum tube
Device feature size: 10 cm
Major Appl.: Amplifier (Radio, TV, Wireless etc.)
Technology Revolution
because there had been no electronics before
(Vacuum tube new device, new application)

6
First Computer Eniac: made of huge number of vacuum tubes 1946
Big size, huge power, short life time filament
 dreamed of replacing vacuum tube with solid-state device

Today's smart phone

made of semiconductor
has much higher
performance with
extremely low power
consumption

7
 1960: First MOSFET
by D. Kahng and M. Atalla
G
Surface Gate electrode
Gate Oxd

Channel Drain
Source
S D
Electron flow
Top View

Al
SiO2
Si
Si/SiO2 Interface is
extraordinarily good 8
1970 “Micro-Electronics” started.

9
 1970,71: 1st generation of LSIs (Si-MOSFETs)

1k bit DRAM Intel 1103 MPU Intel 4004

(Clock 750 KHz)

10
1970 “Micro-Electronics” started.
Device: Si MOS integrated circuits
Device feature size: 10 mm
Major Appl.: Digital (Computer, PC, etc.)
Technology Revolution
because there had been no micro-electronics before
(MOS IC new device, new application)

11
2000 “Nano-Electronics” started.

12
2000 “Nano-Electronics” started.

180 nm

Intel Pentium 4 : Clock 1 ~ 2 GHz

13
2000 “Nano-Electronics” started.
Device: Still, Si CMOS integrated circuits
Device feature size: 180 nm
Major Appl.: Digital (m-processor, cell phone, etc.)

Technology Revolution??
Maybe, just evolution or innovation!
(MOS IC, the same device, similar application)

But very important so many innovations

by reducing the size!

Downsizing increases performance and

decreases the cost and power consumption.
14
Now, 2014 “Nano-Electronics” continued.
Device: Still, Si CMOS integrated circuits
Device feature size: a few 10 nm
Major Appl.: Still Digital (m-processor, cell phone, etc.)

Still evolution and innovation are going on.

Broadwell SoC (Intel)

http://download.intel.com/newsroom/kits/14nm/pdfs/Intel_14nm_New_uArch.pdf 15
Downsizing of the components has been
the driving force for circuit evolution
1900 1950 1960 1970 2000 2014

Vacuum Transistor IC LSI VLSI VLSI

Tube

10 cm cm mm 10 mm 100 nm 14 nm
10-1m 10-2m 10-3m 10-5m 10-7m 10-8m

In 100 years, the size reduced by one million times.

There have been many devices from stone age.
We have never experienced such a tremendous
reduction of devices in human history. 16
 Feature Size / Technology Node
(1970) 10 μm  8 μm  6 μm  4 μm  3 μm  2 μm  1.2 μm

0.8 μm  0.5 μm  0.35 μm  0.25 μm  180 nm  130 nm 

90 nm  65 nm  45 nm  32 nm  (28 nm ) 22 nm(2012)

 14 nm (2014)

From 1970 to 2013 (Last year)

43 years 1 generation
18 generations 2.5 years
Line width: 1/450 Line width: 1/1.43 = 0.70
Area: 1/200,000 Area: 1/2 = 0.5
17
2. Importance of downsizing

18
 Downsizing
Important for
- Decreasing cost,
and power consumption
- Increasing performance

This is true still for today’s 14 nm !

19
Merit for downsizing to 14 nm
(Intel case)
http://download.intel.com/newsroom/kits/14nm/pdfs/
Intel_14nm_New_uArch.pdf

Merit for cost, power consumption,

and performance

20
In 2012
Most Recent SD Card

128GB (Bite)
= 128G X 8bit
= 1T(Tera)bit

1T = 1012 = １Trillion

World Population：7 Billion

Brain Cell：10～100 Billion
Stars in Galaxy：100 Billion
21
In 2014
Most Recent SD Card

256GB (Bite)
= 256G X 8bit
= 2T(Tera)bit

2T = 1012 = 2Trillion

World Population：7 Billion

Brain Cell：10～100 Billion
Stars in Galaxy：100 Billion
22
128 GB = 1Tbit
2.4cm X 3.2cm X 0.21cm

Volume：1. 6cm³ Weight：2g

Voltage：2.7 - 3.6V

Old Vacuum Tube：

5cm X 5cm X 10cm, 100g, 50W

What are volume, weight, power

consumption for 1Tbit

23
 Old Vacuum Tube： 1Tbit = 10,000 X 10,000 X 10,000 bit
5cm X 5cm X 10cm Volume = (5cm X 10,000) X (5cm X 10,000)
X (10cm X 10,000)
= 0.5km X 0.5km X 1km
Burji Khalifa 500 m
Pingan Intenational Indian Tower Dubai, UAE
Finance Center Mumbai, India (Year 2010)
Shanghai, China (Year 2016)
(Year 2016)

1,000 m
828 m
700 m
700 m

1Tbit

24
Old Vacuum Tube： 1Tbit = 1012bit
50W/tube (assuming)
Power = 0.05kWX1012=50 TW
Nuclear Power Generator
1MkW=1BW We need 50,000 Nuclear Power Plant for
just one 128 GB memory

In Japan we have only 54

Nuclear Power Generator

Tokyo Electric Power Company

(TEPCO) can supply only
55BW.

We need 1000 TEPCO just one

128 GB memory
Imagine how many memories
25
are used in the world!
So progress of integrated
circuits by downsizing is
extremely important for
power saving.

26
Various semiconductor devices
Brain is very important
Brain: Integrated Circuits
Ear, Eye：Sensor
Mouth：RF/Opto device

Stomach：PV device

Hands, Legs：Power device

27
Near future smart-society has to treat huge
data.
Demand to high-performance and low power
CMOS become much more stronger.

28
3. Current status of Si-CMOS
device technologies

29
 More Moore to More More Moore
Technology node Now Future
65nm 45nm 32nm 22nm 14nm 10nm, 7nm, 5nm, 3.5nm

Lg 35nm Lg 30nm

Main stream
(Fin,Tri, Nanowire)

Planar Tri-Gate Alternative

Si Si channel

(FDSOI)
FD: Fully Depleted
Si is still main stream for future !!
M. Bohr, pp.1, IEDM2011 (Intel) Alternative (III-V/Ge)
P. Packan, pp.659, IEDM2009 (Intel)
C. Auth et al., pp.131, VLSI2012 (Intel)
Others Channel FinFET

T. B. Hook, pp.115, IEDM2011 (IBM) Emerging 30

S. Bangsaruntip et al., pp.297, IEDM2009 (IBM) Devices
 High-k gate dielectrics
Hf-based oxides
45nm 32nm 22nm 14nm 10nm, 7nm, 5nm, 3.5nm,
EOT:1nm EOT:0.95nm EOT:0.9nm EOT:0.?nm
SiO2 IL (Interfacial Layer)
is used at Si interface to Technology for direct contact of
realize good mobility high-k and Si is necessary
TiN
EOT=0.52 nm
Remote SiO2-IL
EOT=0.9nm HfO2 scavenging
HfO2/SiO2 SiO2
HfO2 (IBM)
(IBM) Si
EOT=0.37nm EOT=0.40nm EOT=0.48nm
Continued research MG

and development
La-silicate
K. Mistry, et al., p.247, IEDM 2007, (Intel)
T.C. Chen, et al., p.8, VLSI 2009, (IBM)
T. Ando, et al., p.423, IEDM2009, (IBM)
T. Kawanago, et al., T-ED, vol. 59, no. Si
0.48 → 0.37nm Increase of Id at 30%
2, p. 269, 2012 (Tokyo Tech.)
K. Kakushima, et al., p.8, IWDTF 2008, 31
Direct contact with La-silicate (Tokyo.Tech)
(Tokyo Tech.)
High-k is very important, however
very difficult.
Thickness (EOT) decreased only
0.05 nm (or 0.5 Å, or 1 atom
layer) for every generation.

32
 Benchmark of device characteristics
Intel Intel Toshiba IBM Samsung IBM STMicro. Tokyo Tech
(IEDM2007, 2009) (VLSI2012) (VLSI2012) (IEDM2012) (IEDM2012) (IEDM2009) (VLSI2008) (ESSDERC2010)

Bulk Planar Tri-Gate

Structure Tri-Gate NW ETSOI Bulk Planar GAA NW GAA NW -gate NW
45nm 32nm 22nm

35/25 22/30
Lg (nm) 35 30 30 14 22 20 65
(nFET/pFET) (nFET/pFET)

Gate
Hf-based Hf-based SiO2 HfO2 HfO2 ? Hf-based HfZrO2 SiO2
Dielectrics

EOT (nm) 1 0.95 0.9 3 ~1 - 1.5 - 3

Vth (V) ~0.4 ~0.3 ~0.2 -0.15 (nFET) 0.3~0.4 ~0.3 0.3~0.4 ~0.5 -0.2 (nFET)

VDD (V) 1 1 0.8 1 0.9 0.9 1 1.1 1

ION (mA/um)
1.36/1.07 1.53/1.23 1.26/1.1 0.83 (nFET) 0.59/0.62 (Ieff) 1.2/1.05 0.83/0.95 2.05/1.5 1.32 (nFET)
nFET/pFET

DIBL
(mV/V) ~150 ~200 46/50 <50 - 104/115 65/105 56/9 62
nFET/pFET

SS
- ~100 ~70 <80 - 87 85 <80 70
(mV/dec)

33
 ION and IOFF benchmark until 2012
NMOS Supply voltage affects significantly! PMOS
10000 10000
Intel [1] Intel [1] Intel [2] Intel [1] Intel [2] Intel [1]
Bulk 32nm Tri-Gate 22nm Bulk 45nm Bulk 32nm Bulk 45nm Tri-Gate 22nm
VDD=0.8V VDD=0.8V VDD=1V VDD=0.8V VDD=1V VDD=0.8V
Samsung [3]
1000 Bulk 20nm 1000 IBM [10] IBM [7]
VDD=0.9V ETSOI ETSOI
Tokyo Tech. [9] VDD=0.9V VDD=0.9V IBM [7]
IOFF [nA/mm]

IOFF [nA/mm]
IBM [10] -gate NW Ieff ETSOI
ETSOI VDD=1V VDD=1V
VDD=0.9V Samsung [3]
IBM [7] Bulk 20nm
100 Ieff ETSOI 100
Toshiba [4] VDD=0.9V
IBM [7] VDD=1V
Tri-Gate NW ETSOI
VDD=1V
IBM [6] VDD=0.9V IBM [6]
FinFET 25nm FinFET 25nm
10 STMicro. [8] 10
VDD=1V VDD=1V
GAA NW STMicro. [8]
STMicro. [8]
IBM [5] VDD=1.1V GAA NW
GAA NW IBM [5]
GAA NW VDD=1.1V
VDD=0.9V GAA NW
VDD=1V
VDD=1V
1 1
0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
ION [mA/mm] ION [mA/mm]
[1] C. Auth et al., pp.131, VLSI2012 (Intel). [6] T. Yamashita et al., pp.14, VLSI2011 (IBM).
[2] K. Mistry et al., pp.247, IEDM2007 (Intel). [7] A. Khakifirooz et al., pp.117, VLSI2012 (IBM).
[3] H.-J. Cho et al., pp.350, IEDM2011 (Samsung). [8] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics). 34
[4] S. Saitoh et al., pp.11, VLSI2012 (Toshiba). [9] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)
[5] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM). [10] K. Cheng et al., pp.419, IEDM2012 (IBM)
 ION and IOFF benchmark updating
Lower supply voltage degrades the ratio.
NMOS PMOS
10000 10000
ST [2] Intel [1] ST [2] Intel [1]
ETSOI 14nm Tri-Gate 22nm ETSOI 14nm Tri-Gate 22nm
VDD=0.75V VDD=0.8V VDD=0.75V VDD=0.8V

1000 1000 IBM [7]

ETSOI
Tokyo Tech. [9] VDD=0.9V IBM [7]
IOFF [nA/mm]

IOFF [nA/mm]
-gate NW ETSOI
VDD=1V VDD=1V
IBM [3] IBM [7]
100 GAA NW ETSOI
100
VDD=1V IBM [7] VDD=1V
ETSOI
IBM [6] VDD=0.9V IBM [6]
FinFET 25nm FinFET 25nm
10 10
VDD=1V STMicro. [8] VDD=1V
Toshiba [4] STMicro. [8]
STMicro. [8] GAA NW
Tri-Gate NW GAA NW
GAA NW VDD=1.1V IBM [5]
VDD=1V VDD=1.1V
VDD=0.9V GAA NW
VDD=1V
1 1
0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
ION [mA/mm] ION [mA/mm]
[1] C. Auth et al., pp.131, VLSI2012 (Intel). [6] T. Yamashita et al., pp.14, VLSI2011 (IBM).
[2] Q. Liu et al., pp.228, IEDM2013 (ST). [7] A. Khakifirooz et al., pp.117, VLSI2012 (IBM).
[3] S. Bangsaruntip et al., pp.526, IEDM2013 (IBM). [8] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics). 35
[4] S. Saitoh et al., pp.11, VLSI2012 (Toshiba). [9] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)
[5] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM).
Examples of the state of the art
Current status of Si-CMOS device
technologies

Fin, Tri gate FET

36
 Multi-gate structures

G G G G
G
G

Fin Tri-gate Tri-gate -gate All-around

(Variation)

37
How far can we go for production?

Rather than Ioff value, Ion/Ioff ratio is

important.

Now, Ion/Ioff ratio is typically 106.

However, it degrades significantly
with decrease in Vsupply.

38
 ION and IOFF benchmark
NMOS PMOS
10000 10000
Intel [a] Intel [a] Intel [b] Intel [a] Intel [b] Intel [a]
Bulk 32nm Tri-Gate 22nm Bulk 45nm Bulk 32nm Bulk 45nm Tri-Gate 22nm
VDD=0.8V VDD=0.8V VDD=1V VDD=0.8V VDD=1V VDD=0.8V
Samsung [c]
1000 Bulk 20nm 1000 IBM [j] IBM [g]
VDD=0.9V ETSOI ETSOI
Tokyo Tech. [i] VDD=0.9V VDD=0.9V IBM [g]
IOFF [nA/mm]

IOFF [nA/mm]
IBM [j] -gate NW Ieff ETSOI
ETSOI VDD=1V VDD=1V
VDD=0.9V Samsung [c]
IBM [g] Bulk 20nm
100 Ieff ETSOI 100
Toshiba [d] VDD=0.9V
IBM [g] VDD=1V
Tri-Gate NW ETSOI
VDD=1V
IBM [g] VDD=0.9V IBM [f]
FinFET 25nm FinFET 25nm
10 STMicro. [h] 10
VDD=1V VDD=1V
GAA NW STMicro. [h]
STMicro. [h]
IBM [5] VDD=1.1V GAA NW
GAA NW IBM [e]
GAA NW VDD=1.1V
VDD=0.9V GAA NW
VDD=1V
VDD=1V
1 1
0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
ION [mA/mm] ION [mA/mm]
[a] C. Auth et al., pp.131, VLSI2012 (Intel). [f] T. Yamashita et al., pp.14, VLSI2011 (IBM).
[b] K. Mistry et al., pp.247, IEDM2007 (Intel). [g] A. Khakifirooz et al., pp.117, VLSI2012 (IBM).
[c] H.-J. Cho et al., pp.350, IEDM2011 (Samsung). [h] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics). 39
[d] S. Saitoh et al., pp.11, VLSI2012 (Toshiba). [i] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)
[e] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM). [j] K. Cheng et al., pp.419, IEDM2012 (IBM)
 22 nm Tri-gate (Intel)
C. Auth et al., pp.131, VLSI2012 (Intel)

HP MP SP
Tri-gate has been implemented
TOX,E (nm) 0.9 0.9 0.9
since 22nm node, enabling
LGATE (nm) 30 34 34 further scaling
IOFF (nA/um) 20-100 5-20 1-5 40
 22 nmTri-gate (Intel)
C. Auth et al., pp.131, VLSI2012 (Intel)

Intel’s fin is triangle shape!

PMOS channel S/D region showing

under the gate the SiGe epitaxy

A fin width of 8nm to balance SCE and Rext

A fin height of 34nm to balance
41
drive current vs. capacitance
 22 nmTri-gate (Intel)
C.-H. Jan et al ., pp.44, IEDM2012 (Intel)

Very good Vth control!

・SS of 71 and 72 mV/dec for HP NMOS and PMOS, respectively

・DIBL of 30 and 35 mV/V for NMOS and PMOS, respectively
・Vth of 22 nm is about 0.1 ~0.2 V lower than that of 32nm 42
Low Vccmin16nm node FinFETs (TSMC)
S. Wu et al., pp.224, IEDM2013 (TSMC)

 Fin patterning and formation on bulk

with 48 nm fin pitch (pitch-splitting
technique)
 Poly-silicon deposition and gate
patterning with (gate pitch of 90 nm)
 High-k/Metal gate RPG process
 Raised source/drain with dual epitaxy

Static noise margin of 0.07 um2 high

density SRAM cell at 0.8 V and 0.6 V

Low leakage (SVt : purple)

- Lg = 34 nm
- SS < 65 mV/dec.
- DIBL < 30 mV/V
- Idsat = 520/525 uA/um at 0.75 V
- Ioff = 30 pA/um
43
 Advanced RMG for 14 nm FinFETs (GF)
M. Togo et al., pp.112, VLSI2014 (GF) * No information about Lgate

 STI oxide extra recess during replacement

metal gate (RMG) module increases Ion
 Dummy gate removal
 W selective etch improves AC
 STI oxide extra recess
performance and gate-contact short yield
 WF adjust treatment
 W selective etch  Combination of novel work function adjust
 Contact formation with treatment and WFM provides Vt turning
SAC

44
Intel 14nm Technology by Mark Bohr, August 11. 2014
http://download.intel.com/newsroom/kits/14nm/pdfs/Intel_14nm_New_uArch.pdf

Interconnects

SRAM Cell

45
10 nm FinFETs with Multi WF Gate Stack (IBM)
K. –I. Seo et al., pp.12, VLSI2014 (IBM)
DIBL ~ 40 - 50 mV for N/PFET for Lg =
20 nm
=> Controlled short channel effect

I-V performance
 Lg = 20 nm
 SS = 70 mV/dec

SRAM performance
 SNM = 140 mV at 0.75V
 SNM = 120 mV at 0.55 V

46
Examples of the state of the art
Si-CMOS device technologies

FD SOI FET

47
Dual STI for Multi-Vt at 20 nm Node (CEA-LETI)
L. Grenouillet et al., pp.64, IEDM2012 (CEA-LETI)

 Wider back bias (BB)

tunability with dual STI
(shallow & deep)

 Successive performance
boost and leakage current
control by BB
48
 Extremely Thin SOI (ETSOI) (IBM)
K. Cheng et al., pp.419, IEDM2012 (IBM)
Also, ET-SOI works very good!
・Hybrid CMOS
Si Channel nFET
Strained SiGe Channel pFET
・RO delay improvement over
FinFET with FO = 2

49
 Material Selection and RSD for 14 nm FDSOI (ST)
Q. Liu et al., pp.228, IEDM2013 (STMicroelectronics)

nMOS => Si channel/SiC RSD

pMOS => SiGe channel/SiGe RSD

50
14 nm FDSOI Technology (STMicroelectronics)
O. Weber et al., pp.14, VLSI2014 (STMicroelectronics)

New Front-End process elements

 Dual SOI/SiGeOI N/P channel
 Dual workfunction gate-first HKMG
integration scheme
 Dual in-situ doped Si:CP/SiGeB N/P
RSD

 30% speed boost at the same power

 55% power reduction at the same speed
51
Silicon-on-Thin-Buried Oxide CMOS (LEAP)
S. Kamohara et al., pp.154, VLSI2014 (LEAP)

 Very small Vth and Ion variability was

demonstrated for one million transistors.
 High performance due to less S/D doping
and back bias controlling.
 Confirmed 6-T SRAM operation (2 Mbit) at
less than 0.4 V with a 5.5-ps access time.
 Demonstrated that the minimum operating
voltage can be controlled at <0.4 V by
back-bias against temperature variation.
52
 Strain Engineered Extremely Thin SOI (IBM)
A. Khakifirooz et al., pp.117, VLSI2012 (IBM)

nFET - Strained SOI (SSDOI) t ~ 6 nm

pFET – SiGe-on-insulator (SGOI) Channel

53
Examples of the state of the art
Current status of Si-CMOS device
technologies
Nanowire FET

54
 Multi-gate structures

G G G G
G
G

Fin Tri-gate Tri-gate -gate All-around

(Variation)

55
Gate All Around Nanowire (GAA NW) (IBM)
S. Bangsaruntip et al., pp.297, IEDM2009 (IBM)

・Lg = 25~35nm GAA NW

・Hydrogen anneal provide
smooth channel surface
・Competitive with conventional
CMOS technologies
・Scaling the dimensions of NW
leads to suppressed SCE 56
 Gate All Around Nanowire (GAA NW)
G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics)

SiN
NiPtSi HM
Top
Gate
Channel
Bottom
Gate

・Gate all around structure

・Lg of 22~30nm
・Bulk wafer-based integration
・High drive currents by special stress
and channel orientation design 57
 Back gate control Tri-Gate Nanowire
S. Saitoh et al., pp.11, VLSI2012 (Toshiba)

・Lg = 14nm Tri-Gate NW

・High SCE immunity at Lg of 14nm Vsub
・Vth tuning by applying Vsub with
thin BOX of 20nm

Vth control by
58
back-gate bias
 -gate Si Nanowire (TIT)
S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.) Lg=65nm
10 -3
1.E-03

Drain Current (A)

-4 Vd=-1V Vd=1V
Poly-Si 10
1.E-04

SiO2 12 nm 10 -5
1.E-05
NW -6
1.E-06
10 Vd=-50mV Vd=50mV
10 -7
1.E-07

SiN SiN pFET nFET

19 nm 10 -8
1.E-08

SiO2 -9
1.E-09
10
-10
1.E-10
10
-11
1.E-11
10
-12
1.E-12
10
-1.5 -1.0 -0.5 0.0 0.5 1.0
Gate Voltage (V)
・Conventional CMOS process
・High drive current
(1.32 mA/mm @ IOFF=117 nA/mm)
Lg=65nm
0 0.5 1 1.5 2 ・DIBL of 62mV/V and SS of 70mV/dec
59
ION (mA/mm) for nFET
Examples of the state of the art
Current status of Si-CMOS device
technologies

Planar Bulk FET

60
Low Power Planar 20 nm CMOS Bulk (IBM)
H. Shang et al., pp.129, VLSI2012 (IBM)

NFET PFET

 Isolation (wells, Vt)

 IO EG gate growth
 Dummy gate patterning
 Logic SG, IO, SRAM extension/halo
 Spacer dep/patterning
 eSiGe formation
 Raised source/drain formation


Advanced gate stack formation
Tungsten stud (TS) contact formation
 Lgate = 20 nm
 CA/CB Tungsten contacts  0.55X density scaling


M1 double patterning
Self Aligned V0
 N/P DIBL = 121/126 mV
 BEOL  SS = 90/86 mV/dec.
 SNM = 160mV at 0.9V 61
Process technologies for
State of the art CMOS

Appendix 1

62
4. Major problems for downsizing

63
1. Lithography of sub-10 nm pattern
- Delay in EUV development.
- Process step increase for double, triple, quadruple
patterning as alternate

2. Increase of leakage current

3. Decrease of on-current

4. Interconnect problems Explained in

- Increase of R and C
this tutorial
5. Variability, reliability, yield.
64
5. Increase of leakage current
when downsizing

65
Leakage components

1. Punch through current between S and D

2. Subthreshold current between S and D
3. Direct-tunneling current between S and D
4. Gate leakage current between G and S/B/D

66
 1. Punch-through between S and D
Region governed Region governed DL touch with S
by gate bias 0V By drain bias Region (DL) 0V
Gate metal Large IOFF Vdd
1V 1V
0V Gate oxide No tox. Vdd 0V
Source Drain thinning
0V
0V < Vdep＜1V 0V < Vdep＜1V
Channel Large IOFF
(Electron current) 0V
0V
Substrate 0V Depletion Vdd
0V
Region (DL) 0.5V
by Drain Bias 0V

tox and Vdd have to be decreased for better channel

potential control  IOFF Suppression 67
 1. Punch-through between S and D

There are 3 solutions to suppress the depletion layer

A. Decrease supply voltage  Very difficult

as explained later
B. Decrease tox to enhance the channel potential
controllability by gate bias
C. Gate/channel configuration change to enhance
the channel potential controllability by gate bias
Also, decrease tSi
Fin-FET, ET-SOI, etc. 68
B.Decrease tox
A. Toriumi (Tokyo Univ), IEDM 2006, Short Course
(
tox (

69
C. Configuration change for channel and
gate structures for better control of
channel potential.
Also, decrease tSi

Fin-FET, ET-SOI, etc.

70
 Extremely Thin (or Fully-Depleted) SOI
- Make Si layer thin (decrease tSi)
- Control channel potential also from the bottom

Drain bias
0V 0V
induced
depletion
G
0V 1V 0V 1V Extremely
G
thin Si
S 0V D
S
SiO2
0V ＜V＜1V
Si
G
0V

0V
71
Planar ET (or FD) SOI
 Surrounding gate structure (Multiple gates)

- Make Si layer thin(decrease tSi)

- Control channel potential also by multiple gates
not only from top & bottom but maybe also
from side
0V Drain bias
0V
induced
G depletion
0V G 1V 0V 1V Si fin or
nanowire
S S 0V D

0V ＜V＜1V
G
0V
0V 72
Planar
Multi gate
 Multi-gate structures

G G G G
G
G

Fin Tri-gate Tri-gate -gate All-around

(Variation)

73
Multi-gate MOSFETs have advantage
not only suppressing Ioff, but also for
increasing Ion over planer MOSFETs

1. Because of higher mobility due to

lower vertical electric field and low
dopant concentration in the channel

2. Because of higher carrier density at

the round corner 74
75
 Electron Density
電子濃度(x1019cm-3)
6
6.E+19

角の部分
5
5.E+19 Edge portion
4
4.E+19

3
3.E+19 平らな部分
Flat portion
2
2.E+19

1
1.E+19

0
0.E+00

0 2 4 6 8
Distance from SiNW Surface (nm)

76
2. Direct-tunneling between S and D

Wave function of electron penetrates the

channel potential barriers by quantum
mechanical physics, when the channel length
is around 3 nm.

77
Built-in potential When transistor is at off state
between Source 3 nm Tunneling

Energy or Potential
and Channel pn distance
junction < 0.7 V

for Electron
Direct-tunnel
current

Channel
Source Drain
There is no solutions!

Downsizing limit is @ Lg 3 nm.

78
 3.Subtheshold leakage current of MOSFET

Id

Ion
OFF ON
Subthreshould
Leakage Current

Vg
Vg=0V
Subthreshold Vth
region (Threshold Voltage) 79
 Subthreshold leakage current
Id (A/mm)
Ion
Electron Energy
Boltzmann statics
10-5
Exp (qV/kT)
Vd
10-7
0.5 V 1.0 V Lg  1/2
Vth
Vd, Vg  1/2
Ioff 10-9
Vth  1/2
0.15 V 0.3 V

10-11 However
Ioff  103 in this example
0 0.5 1
Vg (V)
Because of
log-linear dependence
80
 Subtheshold leakage current of MOSFET

Id
Subthreshold Current
Ion Is OK at Single Tr. level
OFF ON
Subthreshould But not OK
Leakage Current For Billions of Trs.

Vg
Vg=0V
Subthreshold Vth
region (Threshold Voltage) 81
3. Subthreshold current between S and D
Solution: however very difficult
Keep Vth as high as possible
- Do not decrease supply voltage, Vd
 However, punchthough enhanced
- Suppress variability in Vth

Thus, subthreshold current will limit the

downsizing, especially for mobile devices
82
 4. Gate leakage current
Probably OK using high-k, until EOT=0.4 nm
See Appendix 2
Gate Leakage current
1.E+04
ITRS requirement
1.E+03
Jg at 1 V (A/cm2)

1.E+02

1.E+01

1.E+00

1.E-01
La silicate
Gate dielectrics
1.E-02
0.3 0.4 0.5 0.6 0.7 0.8
EOT (nm) 83

H. Iwai, SBMicro 2013

 Our Work at TIT: High-k

Our result at TIT EOT=0.40nm

140

Electron Mobility [cm2/Vsec]

1.0

120
L/W = 5/20mm Vg= 1.0V
T = 300K
0.8

100
Drain Current (mA)

Nsub = 3×1016cm-3 Vg= 0.8V

80
0.6

EOT = 0.40nm
Vg= 0.6V 60
L/W = 5/20mm
0.4

40
T = 300K
Vg= 0.4V
20 Nsub = 3×1016cm-3
0.2

Vg= 0.2V
0
Vg= 0 V 0 0.5 1 1.5 2 2.5
0 0.2 0.4 0.6 0.8 1.0
Eeff [MV/cm]
Drain Voltage (V) 84
All the 4 leakage components increase, when downsizing

1. Punch through current between S and D

Solution: Enhance gate bias control to channel potential
 Decrease tox (EOT) for gate oxide, and tSi for SOI & Fin FETs

2. Subthreshold current between S and D

Solution: Keep as high Vth as possible
 Keep as high Vsupply as possible, but difficult
 This will limit the downsizing depending on application
before Lg = ~ 3 nm

3. Direct-tunneling current between S and D

No solution. Limit the downsizing at Lg = ~ 3 nm

4. Gate leakage current between G and S/B/D

85
Solution. Introduction of new material for higher k and band offset
The limit is deferent depending on application
100
e)
Operation Frequency (a.u.)

10

Subthreshold Leakage (A/mm)

86
Source: 2007 ITRS Winter Public Conf.
 How far can we go for production?
Past
10mm  8mm  6mm  4mm  3mm  2mm  1.2mm  0.8mm  0.5mm 
0.35mm  0.25mm  180nm  130nm  90nm  65nm  45nm  32nm

Limit depending Fundamental

on applications limit
Subthreshold
Direct-tunnel
Now Future punchthrough

(28nm)  22nm  14nm  10 nm  7nm  5nm?  3.5nm?  2.5 nm? 

Intermediate
node
87
 However, careful about the commercial name of technology!

Recently,
Gate length (Lg) is much larger than the Technology name

22 nm Technology by Intel

Lg (Gate length) = 30 nm (HP), 34 nm (MP), 34 nm or larger (SP)

IEDM 2012, VLSI 2013

14 nm Technology by Global
Lg (Gate length) = 25 nm Euro SOI 2014
10 nm Technology by Leti (FD-SOI)
Lg (Gate length) = 15 nm ECS Fall 2013
88
 ITRS 2013 (Just published in April 2014)

Year 2013 Year 2027

Commercial name (nm) X 0.70 / 2 years 14 (nm) 1.3 (nm)
Metal half pitch (nm) X 0.80 / 2 years 40 (nm) 8 (nm)
Lg (nm) X 0.83 / 2 years 20.2 (nm) 5.6 (nm)
Vdd (V) X 0.96 / 2 years 0.86 (nm) 0.65 (nm)
EOT (nm) X 0.91 / 2 years 0.80 (nm) 0.43 (nm)
TSi (nm) X 0.84 / 2 years 7.4 (nm) 2.0 (nm)

Only the commercial names decreases X0.7/ 2 years 1.3 nm technology!

but HP = 8nm
Difference between the commercial name and Lg = 5.6 nm
physical parameters becomes larger

Recently, companies become not to disclose Lg values at conferences

89
 ITRS 2013 (Just published in April 2014)
Year 2013 2015 2017 2019 2021 2023 2025 2027
Commercial name (nm) 14 10 7 5 3.5 2.5 1.8 1.3
Metal half pitch (HP) (nm) 40 32 25.3 20 15.9 12.6 10 8

Lg (nm) 20.2 16.8 14.0 11.7 9.7 8.1 6.7 5.6

(Lg for ITRS 2007) (13) (10) (8) (6) (5) (4.5 in 2022)

Lg for low stand by power (nm) 23 19 16 13.3 11.1 9.3 7.7 6.4
Vdd (V) 0.86 0.83 0.80 0.77 0.74 0.71 0.68 0.65
(Vdd (V) for ITRS 2007) (0.90) (0.80) (0.70) (0.70) (0.65)(0.65 in 2022)
EOT (nm) 0.80 0.73 0.67 0.61 0.56 0.51 0.47 0.43
(EOT (nm) for ITRS 2007) (0.60) (0.60) (0.55) (0.50) (0.50)(0.50 in 2022)
TSi (nm) 7.4 6.1 5.1 4.3 3.6 3.0 2.5 2.0
(TSi (nm) for ITRS 2007) (6.0) (6.0) (4.5) (3.8) (3.2) (3.0 in 2022)

Before, HP: X 0.70 / 2 years, Lg: X 0.70 / 2 years

Now, HP: X 0.80 / 2 years, Lg: X 0.83 / 2 years

 Thus, now more generations and more years until reaching limit
90
 Shrink rate

Intel kept X ~0.7 for pitch

until 14 nm technology,
but it is not certain for future
SRAM area

Logic area

http://download.intel.com/newsroom/kits/1 91
4nm/pdfs/Intel_14nm_New_uArch.pdf
6. Degradation of on-current
when downsizing

92
When downsizing

1.Mobility degradation

2.Carrier density decrease

1, 2  decrease of on-current

93
m(mobility) degradation tSi d

Strong interaction between

tox d carriers and Si surface (or interface)

Strong interaction between m

carriers and metal/oxide interface
d
m tSi Si Si surface
d
SOI
tSi tSi
Gate electrode
d d d
d d
tox Gate oxide d Metal/ d Si
Oxide d d
Si channel interface d d Si

Gate stack Nano-wire Fin / Tri 94

 ITRS 2013
Year 2013 2015 2017 2019 2021 2023 2025 2027
Commercial name (nm) 14 10 7 5 3.5 2.5 1.8 1.3
EOT (nm) 0.80 0.73 0.67 0.61 0.56 0.51 0.47 0.43
TSi (nm) 7.4 6.1 5.1 4.3 3.6 3.0 2.5 2.0

tox m tSi m
300
at 1 MV/cm
250
Mobility (cm2/Vsec)

200

150

100

50
Solid : La-silicate oxide
Open : Hf-based oxides
0
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
EOT (nm)

T. Kawanago, et al., (Tokyo Tech.) T-ED, 2012 K. Uchida et al., pp.47, IEDM2002 (Toshiba)
L.-Å. Ragnarsson, et al., (IMEC) Microelectron. Eng,. 2011. 95
T. Ando, et al., (IBM) IEDM 2009
Carrier density decrease
ITRS 2013
Year 2013 2015 2017 2019 2021 2023 2025 2027
Commercial name (nm) 14 10 7 5 3.5 2.5 1.8 1.3
TSi (nm) 7.4 6.1 5.1 4.3 3.6 3.0 2.5 2.0

tSi Volume DOS Carrier density

Diameter 1 nm 2 nm 3 nm 4 nm 6 nm

Si nanowire
band structure

Iwata et al., Journal of Computational Physics 229 (2010) 2339–2363

96
7. Emerging technologies

97
7.1 Alternative channel
technologies

98
Current status
Good research results aiming for low voltage
(= 0.5V) operation.
In general good mobility, but poor S-factor.
CMOS inverter results at primitive stage.

Production starting year predicted at 2018 by

ITRS 2011 and 13, but premature to be ready for
the today’s scale microprocessor production.

No or very few reports for circuits, large wafer,

yield, variability, reliability, production cost etc.
99
 Device Structures in III-V
J. Lin, IEDM’12 S.H. Kim, IEDM’11 M. Radosavljevic,
IEDM’11

InAs QW MOSFET III-V-OI MOSFET Tri-gate

Recently various device structures have been demonstrated

on InGaAs platform for achieving higher performance at lower
power supply.

Improvement in high-k/III-V interface and III-V growth technology

has been a key factor. 100
 Low Voltage CMOS

Source: S. Takagi
101
 Multi-gate III-V and Si benchmark
InGaAs GAA, Lch=50nm, Dielectric: 10nm Al2O3
nMOS VDS=0.5V (Purdue Uni.)
J. J. Gu et al., pp.769, IEDM2011 (Purdue).
1.E-05 InGaAs Tri-gate, Lg=60 nm,EOT 12A
VDS=0.5V (Intel)
M. Radosavljevic et al., pp.765, IEDM201(Intel).
InGaAs FinFET, Lch=130nm EOT 3.8nm
VDS=0.5V (NUS)
1.E-06 0.5V H. –C. Chin et al., EDL 32, 2 (2011) (NUS)
VDS=0.5V 0.5V InGaAs Nanowire, Lg= 200nm, Tox 14.8nm
IOFF (A/mm)

Si-FinFET 32nm VDS=0.5V(Hokkaido Uni.)

Intel VDD=0.8V [1] K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni).
0.5V 0.5V Metal S/D InGaAs-OI, Lch= 55nm, EOT 3.5nm
1.E-07 VDS=0.5V(Tokyo Uni.)
Si-FinFET 22nm S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni)
0.5V 0.5V Intel VDD=0.8V [1] 0.5V
InAs Surface channel MOSFET, Lch=130nm,
Dielectric: high-k VDS=0.5V (TSMC)
0.5V S. W. Chang, et al., (TSMC) IEDM2013, p.417.
1.E-08
Si-bulk 45nm InGaAs QW Tri-gate, Lch=60nm,
0.5V Intel VDD=1V[2] Dielectric: Al2O3/HfO2 VDS=0.5V (Sematech)
0.5V T. W. Kim, et al., (Sematech) IEDM2013, p.425.
In0.7Ga0.3As FinFET, Lch=120nm,
Dielectric: Al2O3/HfO2 VDS=0.5V (Penn State Uni.)
1.E-09 Arun VT, et al., (Penn State Uni.) VLSI2014, p.72.
0 0.4 0.8 1.2
Recessed Channel Ge nMOSFET, Lch=60nm,
ION (mA/mm) Dielectric: Al2O3 VDS=0.5V (Purdue Uni.)
H. Wu, et al., (Purdue Uni.) VLSI2014, p.82.
[1] C. Auth et al., pp.131, VLSI2012 (Intel). LP InGaAs QW MOSFET, Lch=100nm, Regrown S/D In0.7Ga0.3As, Lch=40nm,
[2] K. Mistry et al., pp.247, Dielectric: Al2O3 VDS=0.5V (IMEC) 102
Dielectric: Al2O3/HfO2 VDS=0.5V (Sematech)
IEDM2007 (Intel). X. Zhou, et al., (IMEC) VLSI2014, p.166. C. –S. Shin, et al., (KANC, Sematch) VLSI2014, p.31.
Multi-gate III-V and Si benchmark(~2012)
1.E-05 1.E-05
nMOS pMOS
InGaAs GAA
Lch=50nm, Dielectric: 10nm Al2O3 GOI Tri-gate
VDS=0.5V (Purdue Uni.) [1] Lg: 65nm. EOT 3.0nm Si-FinFET 22nm
Si-FinFET 32nm VD=-1V (AIST Tsukuba)[6] Intel VDD=0.8V [10]
1.E-06 Intel VDD=0.8V [10] 1.E-06
InGaAs Tri-gate
Ge FinFET
Lg=60 nm,EOT 12A Si-FinFET 32nm
Lg=4.5 mm,
IOFF (A/mm)

VDS=0.5V (Intel) [2]

Dielectric: SiON, VDS=-1V Intel VDD=0.8V [10]
Si-FinFET 22nm (Stanford Uni.)[7]
InGaAs FinFET Intel VDD=0.8V [10]
1.E-07 Lch=130nm 1.E-07
EOT 3.8nm Si-bulk 45nm
VDS=0.5V (NUS)[3] Intel VDD=1V[11]
Ge GAA Lg= 300nm,
InGaAs Nanowire dielectric: GeO2(7nm)-HfO2(10nm)
Lg= 200nm, Tox 14.8nm VD= -0.8V (ASTAR Singapore)[8]
1.E-08 VDS=0.5V(Hokkaido Uni.)[4] 1.E-08
Metal S/D InGaAs-OI
Lch= 55nm, EOT 3.5nm
VDS=0.5V(Tokyo Uni.)[5] Ge Tri-gate Si-bulk 45nm
Lg=183nm, EOT 5.5nm Intel VDD=1V
VD=-1V (NNDL Taiwan)[9]
1.E-09 1.E-09
0 0.4 0.8 1.2 0 0.4 0.8 1.2
ION (mA/mm) ION (mA/mm)
[1] J. J. Gu et al., pp.769, IEDM2011 (Purdue). [6] K. Ikeda et al., pp.165, VLSI2012 (AIST, Tsukuba). [11] K. Mistry et al., pp.247,
[2] M. Radosavljevic et al., pp.765, IEDM201(Intel). [7] J. Feng et al., IEEE EDL 28(2007)637 (Stanford Uni) IEDM2007 (Intel).
[3] H. –C. Chin et al., EDL 32, 2 (2011) (NUS) [8] J. Peng et al., pp.931, IEDM2009 (ASTAR Singapore) 103
[4] K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni). [9] S. Hsu et al., pp.825, IEDM2011 (NNDL Taiwan)
[5] S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni) [10] C. Auth et al., pp.131, VLSI2012 (Intel).
III-V/Ge benchmark for various structures
(2013 and 2014)
ION DIBL Gm-max Peak Mobility
SS (mV/dec) Lch (nm) Dielectric/EOT Vdd (V)
(mA/μm) (mV/V) (μS/μm) (cm2/Vs)
ETB InGaAs-OI Al2O3 1500
0.2 187 5μm 1 - -
Tokyo Uni. 2013 10nm (VDS=0.5V)
Planar InAs 2700
0.6 85 130 - 0.5 40 7100
TSMC 2013 (VDS=0.5V)
Tri-Gate InGaAs Al2O3/HfO2 1500
0.5 77 60 0.5 10 760
SEMATECH 2013 0.7nm/1.6nm (VDS=0.5V)
QW FinFET InGaAs/InP HfO2/Al2O3 450
0.36 190 50 0.5 - -
IMEC 2014 EOT=1.9nm (VDS=0.5V)
Regrown S/D In0.7Ga0.3As HfO2/Al2O3 2000
1 105 40 0.5 150 5500
SEMATECH 2014 3nm/0.7nm (VDS=0.5V)
FinFET InGaAs (In 70%) HfO2/Al2O3 1900
1.16 236 120 0.5 119 3000
Penn State Uni. 2014 3nm/1nm (VDS=0.5V)
Recessed channel Ge Al2O3 600
0.55 - 60 0.5 - -
Purdue Uni. 2014 8nm (VDS=0.5V)
QW MOSFET InGaAs Al2O3 2000
0.55 82 100 0.5 - -
IMEC 2014 EOT=1.1nm (VDS=0.5V)
CMOS InGaAs-OI Al2O3
0.05 80 10μm 1 - - 1200
GNC 2014 7.8nm
CMOS SGOI HfO2
0.02 115 10μm -1 - - 200
GNC 2014 4.5nm
CMOS La2O3/GaAs nFET La2O3/Al2O3
0.15 74 1μm 2 - - 1150
Purdue Uni. 2014 8nm/6nm
CMOS La2O3/GaAs pFET La2O3/Al2O3
0.015 270 1μm -2 - - 104
180
Purdue Uni. 2014 8nm/6nm
III-V/Ge benchmark for various structures
(2011 and 2012)
Planar Gate-all-around
FinFET Tri-gate Nanowire
(metal S/D, Strain, Buffer…) MOSFET

material InGaAs Ge InGaSn InGaAs Ge InGaAs Ge InGaAs Ge InGaAs Ge

(multishell)

7.6 Ao 5.5 nm 10nm-

Dieletric Al2O3/ 5nm ALD 5nm ALD
ALD
HfO2: HfAlO 3.0 nm
HfO2+ SiON 1.2 nm (Al2O3+
/EOT 3.5 nm Al2O3+GeO2
Al2O3 Al2O3 GeO2) Al2O3 11nm 14.8 nm (ALD Al2O3)

Ns: 5e12
~600 e: 200 ~700 701 ~500 ~850
Mobility - - - - -
(cm2/Vs) h: 400 (mS/mm) (mS/mm) (mS/mm) (cm2/Vs)
(cm2/Vs)

W/L=
Lch (nm) 55 50 mm 100 4.5 mm 60 183 50 200 200 65
30/5 mm

DIBL
84 - - 180 - ~50 - 210 - - -
(mV/V)

150K
SS 61pMOS
105 - 145 750 90 130 150 160 - -
(mV/dec) 33nMOS
120K

ION 278 3 4 (n,p) -

10 400 235 180 604 100 731
(mA/mm) (VD=0.5V) (VD=-0.2V) (VD=0.5V) (VD=0.5V) (VD=0.5V) (VD=-1V) (VD=0.5V) (VD=-0.5V) (VD=0.5V) (VD=-1V)

ASTAR
Stanford Purdue Stanford Intel NNDL Purdue Hokkaido AIST
Research Tokyo Uni Tokyo Uni Singapore
Uni VLSI Uni IEDM Uni ELD IEDM Taiwan Uni IEDM Uni, IEDM 105
Tsukuba
Group VLSI 2012 VLSI 2012 IEDM
2012 2009 2007 2011 IEDM 2011 2011 2011 VLSI 2012
2009
7.2 T-FET technologies
(T: Tunnel)

106
 Current status
Very small S-factor (21mV/dec) can be realized depending on the condition.

Very small Ion (on-current) at low Vd (~ 0.5 V) is a big problem.

High Ion can be obtained at high Vd (~ 1 V) , but s-factor was more than 60
mV/dec.

Current problems/concerns
Large variation of Vth is expected, because tunneling current is very
sensitive to the small change of the size and structure of the junction.
Trap assisted tunneling would decreases the range of small s-factor region
in Vg.
Change of Dit (Interface state density) and Qfix (fixed charge) during long
time operation would affect the characteristics  reliability concern.
Difficulty to realize idea structure in experiment, such as abrupt junction etc.

Expect improvement in future and more research reports. 107

 Tunnel FET
A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)

OFF ON
Vg = 0V Vg = 1V

Band to band tunneling

Low IOFF, Low VDD, SS<60mV/decade 108

 Tunnel FET (III-V)
K. Tomioka et al., pp.47, VLSI2012 (Hokkaido University)

SS=21mV/dec SS=110mV/dec
VDS=1V

HfAlOx
Gate
Conventional FET limit
SS= 60 mV/dec

VDS= 1V

NW Diameter= 30nm
SS of TFET is function of VG due to Zener tunnel current
Minimum SS= 21 mV/dec is reached due to optimized
series resistance of contact, undoped InAs and InAs/Si
ION/IOFF~106 at VDS= 1.0V (ION= 1Am/mm) 109
 ION and IOFF of TFETs
A.M. Ionescu, IEDM2013 Short Course (EPFL) L. Knoll et al., pp. 100, IEDM2013 (Jülich)
Q. Liu et al., pp.228, IEDM2013 (ST). A. Villalon et al., pp. 66, VLSI2014 (CEA-LETI)
Y. Morita et al., pp. 236, VLSI2013 (AIST) C. Auth et al., pp.131, VLSI2012 (Intel).
0.05 < VDS < 0.6 V 0.3 < VDS < 0.5 V
Si, Ge TFET 0.9 < VDS < 1.2 V III-V TFET 1.0 < VDS < 1.5 V
104 104
SOI 14nm node (Lg=20nm) VDD=0.75V (ST) Tri-gate 22nm node SOI 14nm node (Lg=20nm)
Tri-gate 22nm node (Lg=30nm) (Lg=30nm) VDD=0.75V (ST)
103 VDD=0.8V (Intel) VDD=0.8V (Intel)
Leonelli 2011
Villalon 2014
103 Zhou 2012 Dey 2012
Mohata 2012
102 Jeon 2011 Si Si, silicides S/D
Ion (mA/mm)

InAs/GaSb GaSb/InAsSb

Ion (mA/mm)
SiGe NW tri-gate GaAsSb/InGaAs
Ghandi 2011
Knoll 2013
101 Si NW
Knoll 2012 strained Si 102 Zhou 2012
Chang 2013 Si Zhao 2011 Li 2012
strained Si NW GAA InGaAs/InP
InGaAs AlGaSb/InAs
100 NW tri-gate
Morita 2013 Si Fin Q. Huang 2011 Si 101 Moseiund (IBM) Mookerjea 2009 InGaAs
2012 Si/InAs
10-1 Krishnamohan 2009 GOI Dewey (Intel) 2011 InGaAs
Moselund 2011
10-2 Si NW
Q. Huang 2012 Si
100 Tomioka 2012 Si/InAs
Mayer 2008 Si Schmid (IBM) Tomioka 2011 Si/InAs
2011 Si/InAs
10-3 10-1
10-2 10-1 100 101 102 103 104
10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101
Ioff (pA/mm) Ioff (mA/mm)
Si TFETs show the low Ioff, while Ion enhancement is still challenge.
Strain is efficient for Ion enhancement in Si and Ge TFETs.
110
III-V provide high Ion, however, suffer from unacceptably high Ioff.
 Strained SiGe nanowire TFETs
A. Villalon et al., pp. 66, VLSI2014 (CEA-LETI)

Ion enhancement up to 760mA/mm.

Low bandgap of SiGe increase BTBT.

SS lower than 60 mV/dec is

still challenge to be addressed.
111
7.3 2D channel material
technologies

112
 Why 2D channels?
 High-drivability FinFET  Mobility degradation in
 Large Weff/Wfootprint thin Si < 10 nm for both
 Taller Fin electron & hole.
 Narrow Fin pitch High-mobility
 Thinner Fin 2D channels

K. Uchida, et. al., IEDM, 23.1, 2008. S. Kobayashi, et. al., J. Appl. Phys. 106, 024511 (2009).
113
 Family of 2D materials
Vacuum Graphene Oxide Transition metal
0
family family dichalcogenide (TMD)
family
-1 MX2
M: Cr, Mo, W, etc.
Energy [eV]

-2 X: S, Se, Te, etc.

WSe2
MoSe2
-3
TiO2 RuO2
Graphene
-4
1.2 1.6 0.4
1.1 ~ 5.9 1.6 1.4
-5 1.8
~ 3 2.7
Silicene WTe2
-6 MoTe2
Si
WS2
MoS2
-7 h-BN
114
 Exfoliated single-layer MoS2 nMISFET
 217 cm2/Vs,  Depletion mode
electron

B. Radisavljevic et al., Nature Nanotech. 6, 147 (2011)

115
7.4 Other emerging
technologies

116
 Other Emerging technologies
Carbon-based FET J. P. Colinge et al., Nature Nano. 5(2010)225

Carbon nanotube Graphene Junctionless Transistor

L. Liao, et al., Nature ,Vol.467 p.305.

A. D. Franklin et al., pp.525, IEDM2011 (IBM)

GaAs mHEMT
(20nm) SiMOSFET GaAs pHEMT
Cut-off frequency ( GHz)

1000
(29nm) (100nm) All-spin logic device
100 CNT
Graphene
10
J. P. Colinge et al., Nature Nano. 5(2010)266

10 100 1000 Input and output related via

117
Gate length (nm) Spin-coherent channel
F. Schwlerz, Nature Nano ,Vol.5 p.487. M. Lemme, Nanotech workshop ,2012
8. Summary and
conclusions

118
 Summary and conclusions

Si-MOSFET is the main component nano-CMOS devices

and will be so in future.

While the shrink rate of commercial node name will keep

0.7 for 2 years, the shrink rates of HP, Lg, Vd, tox, tSi are
expected to be 0.80, 0.83. 0.96, 91 and 0.84, respectively,
according to ITRS. Because of many reasons, the rate of
physical shrinking will be smaller as the downsizing reach
near the limit.

Increase of the Ioff due to subthreshhold leakage and

degradation of Ion due to EOT and tSi reduction would limit
the gate length scaling before Lg reaches its limit of direct-
tunneling (@ Lg = ~3nm).
119
 Summary and conclusions (continued)

Problems and cost of the lithography and interconnects

would also limit the downsizing.

There have been good challenges for the emerging

technologies such as alternative channel, T-FET, 2D
material and others. However, none of those technologies
has yet reached the level for the industry to start R&D
assuming mass production, such as yield, variability,
reliability, large wafer production.

120
Acknowledgement

I would like to express appreciation to the following

people for the great support for preparing the
materials for the tutorial.

Slides for the 2D materials were made by Prof.

Hitoshi Wakabayashi, Tokyo Institute of Technology.

Many slides except for the 2D materials were made

by Dr. Takamasa Kawanago, Dr. Darius Zade, and
Mr. Tomoya Shoji of Tokyo Institute of Technology,
and Mr. Jing Neng Yao of National Chio Tung
University.
121
Appendices

122
Appendices

Appendix 1. Process technologies for state of the art CMOS

Appendix 2. Alternative channel technologies

Appendix 3. T-FET technologies

Appendix 4. 2D channel material technologies

Appendix 5. Other emerging technologies

123
Appendix1. Process technologies for
state of the art CMOS

- Source/Drain formation
- Strain
- Gate Stack
- Others

124
- Source/Drain formation

125
 Analysis of Implantation to Fin (Panasonic)
T. Noda et al., pp.140, IEDM2013 (Panasonic)
Boron-Interstitial (BnIm)

Kinetic Monte Carlo (KMC) simulation

 Implant temperature has an impact on

amorphization

 Residual defects and dopant-defect

complexes are formed at top-of-Fin
and edge-of-Fin-side after Solid Phase
Epitaxial Regrowth (SPER)
126
 Ion Assisted Deposition and Doping (IADD) (IMEC)
Y. Sasaki et al., pp.542, IEDM2013 (IMEC)

 Knock-in Doping Process => Reduce amorphization/damage to Fins

 Deposition layer thickness important

 A single As ion can provide about 6 knocked-

in As atoms for a 3keV 25 IADD process

 Sidewall doping by simultaneous deposition

and knock-in with small angle implant is the
key of the ION boost
127
 Heated Implantation with a-C mask (IMEC)
M. Togo et al., pp.T196, VLSI2013 (IMEC)

 RT implantation (Upper)
 Forms amorphous layer
 Residue twin defects at the
corner after RTA

 Heated implantation (Lower)

 a-Carbon mask (for high temp.)
 No damage to fins after a-C
implantation

128
Channel Doping to FinFETs for 22 nm (IBM)
C. -H. Lin et al., pp.15, VLSI2012 (IBM)

 Channel doping
 1018 cm-3
Retain a variability
advantage over
planar technology
129
In situ Doped Source Drain Epitaxy for GAA (IBM)
S. Bangsaruntip et al., pp.526, IEDM2013 (IBM)

(e) NW formation (f) Gate formation (g) Spacer formation

Previous (S. Bangsaruntip et al., (h) in situ doped (PH3) S/D epitaxy
IEDM Tech. Dig., p.297,(2009))

 Dopants placed right next to the spacer

60 nm pitch
LG ~ 15 nm  Equal diffusion distance of dopants to both
DNW 8.1 nm the top and bottom of the NW
 Reduced variation
 ~30% enhanced performance
130
- Strain

131
Layout-Induced Stress Effects in FinFETs (IMEC)
M. G. Bardon et al., pp.T114, VLSI2013 (IMEC)

Mobility (cm2/Vs)
Sxx (Mpa)

Number of gate per fin Number of gate per fin

 A strong degradation of the S/D stressors

Sxx (Mpa)

efficiency in reduced fin length

 Compressive STI keeps the performance
variation

Number of gate per fin

132
Through Silicon Via Induced Mechanical Stress (IMEC)
W. Guo et al., pp.431, IEDM2012 (IMEC)

Cu

4-point bending experiments

 Unlike planar device, the n-FinFET drive

current is also affected by mechanical
stress

 TSV build-in stress affect both n and p-

133
 Epitaxial P-SiC Source/Drain Stressor (IMEC)
M. Togo et al., pp.423, IEDM2012 (IMEC)

 Epitaxial Phosphorus doped SiC S/D stressor

 Narrower Fins and SiGe epitaxial growth on the Fins
increase mobility 134
- Gate Stack

135
 High-k/Metal Gate Stacks (IBM)
M. M. Frank et al., pp.213, ECS Transactions 2014 (IBM)

Remote oxygen scavenging

 SiO2 interfacial layer helps

optimize high-k/Si or high-
k/SiGe interface quality.

 Interfacial layer thickness

can be reduced by remote
oxygen scavenging.

136
Simple Gate Metal Anneal Stack (SIGMA) (IBM)
T. Ando et al., pp.44, VLSI2014 (IBM) Positively charged oxygen
nFinFET vacancies (Vo) are generated only
when TiN  Tcrit

Optimized
 Metal (TiN)
thickness
 WF-setting
annealing

 9nm more Lg scaling with matched gate resistance

 Aggressive Lg scaling toward the 14 nm node and beyond 137
 Work Function Engineering (IMEC)
A. Veloso et al., pp.T194, VLSI2013 (IMEC)

 VT modulation and minimized (Rgate) using

ultra-thin TiN/TaN layers, grown for optimum
Al diffusion control properties on HfO2 and
CoxAly fill-metal

 >500mV VT enabled low-VT FinFET NMOS

with improved mobility, noise and reliability
138
EOT-Scaling with Cubic-phase HfO2 (IMEC)
L. Ragnarsson et al., pp.27, VLSI2012 (IMEC)
35

 Doped the HfO2 by alternating ALD cycles

of HfO2 and metal oxides (MOx)
 EOT-scaling by increasing k-value

 Reduced Jg by 2 to 3 orders of magnitude

at the cost of mobility reduction, however.
139
Low Resistance Co-Al Gate Fill for 20 nm node (IBM)
U. Kwon et al., pp.29, VLSI2012 (IBM)

Co-Al Gate Fill

(Al- Blue, Co-Pink)

Low resistance gate formation

at smaller than Lgate = 25 nm
140
 Conduction band offset vs. Dielectric Constant
Leakage Current by Tunneling
Oxide

Band Discontinuity [eV]

SiO 2 4
Band
offset
2
Si
0
-2
-4
-6
0 10 20 30 40 50
Dielectric Constant
XPS measurement by Prof. T. Hattori, INFOS 2003
141
 Direct high-k/Si by silicate reaction
HfO2 case La2O3 case Our approach
Low PO2 High PO2 Low PO2 High PO2
IO IO
VO VO
HfO2 IO IO
VO
VO La2O3 IO
VO IO VO
VO IO silicate
La-rich Si-rich
SiO2-IL LaSix
HfSix
(k~4)
SiO2-IL
Si substrate Si substrate (k~4)
Direct contact can be achieved with La2O3 by forming silicate at interface
Control of oxygen partial pressure is the key for processing.

PO2: Partial pressure of O2 during

high temperature annealing
142
K. Kakushima, et al., VLSI2010, p.69
 SiOx-IL growth at HfO2/Si Interface
TEM image500 oC 30min

XPS Si1s spectrum W

Intensity (a.u)

o
500 C
SiO2
Hf Silicate
HfO2k=16
Si sub.
SiOx-IL
1846 1843 1840 1837
k=4
Binding energy (eV)
1 nm
Phase separator
HfO2 + Si + O2 → HfO2 + Si + 2O*→HfO2+SiO2
H. Shimizu, JJAP, 44, pp. 6131

Oxygen supplied from W gate electrode

D.J.Lichtenwalner, Tans. ECS 11, 319
SiOx-IL is formed after annealing
143
Oxygen control is required for optimizing the reaction
 La-Silicate Reaction at La2O3/Si
Direct contact high-k/Si is possible
XPS Si1s spectra
TEM image 500 oC, 30 min
as depo. La-silicate

Si sub. W
Intensity (a.u)

300 oC La2O3 k=23

La-silicate
k=8~14
500 oC
1 nm

1846 1843 1840 1837 La2O3 + Si + nO2

Binding energy (eV)
→ La2SiO5, La2Si2O7,
La9.33Si6O26, La10(SiO4)6O3, etc.
144
La2O3 can achieve direct contact of high-k/Si
 Physical mechanisms for small Dit
① silicate-reaction-formed ② stress relaxation at interface
fresh interface by glass type structure of La
silicate.

La atom
metal metal
La-O-Si bonding
La2O3 La-silicate
Si Si SiO4
tetrahedron
network
Si sub. Si sub.
Si sub.

Fresh interface with FGA800oC is necessary to

silicate reaction reduce the interfacial stress

J. S. Jur, et al., Appl. Phys. Lett., 145Lett.,

S. D. Kosowsky, et al., Appl. Phys.
Vol. 87, No. 10, (2007) p. 102908 Vol. 70, No. 23, (1997) pp. 3119
 However, high-temperature anneal is necessary
for the good interfacial property

FGA500oC 30min FGA700oC 30min FGA800oC 30min

2 2 1.5 2
2 2
20 x 20mm 20 x 20mm 20 x 20mm
10kHz 10kHz 10kHz
Capacitance [mF/cm ]

Capacitance [mF/cm ]

Capacitance [mF/cm ]
100kHz 100kHz 100kHz
2

2
1.5 1.5
1MHz 1MHz 1MHz
1

1 1

0.5
0.5 0.5

0 0 0
-1 -0.5 0 0.5 1 -1.5 -1 -0.5 0 0.5 -1.5 -1 -0.5 0 0.5
Gate Voltage [V] Gate Voltage [V] Gate Voltage [V]

A fairly nice La-silicate/Si interface can be obtained

with high temperature annealing. (800oC) 146
 Our Work at TIT: High-k

Our result at TIT EOT=0.40nm

140

Electron Mobility [cm2/Vsec]

1.0

120
L/W = 5/20mm Vg= 1.0V
T = 300K
0.8

100
Drain Current (mA)

Nsub = 3×1016cm-3 Vg= 0.8V

80
0.6

EOT = 0.40nm
Vg= 0.6V 60
L/W = 5/20mm
0.4

40
T = 300K
Vg= 0.4V
20 Nsub = 3×1016cm-3
0.2

Vg= 0.2V
0
Vg= 0 V 0 0.5 1 1.5 2 2.5
0 0.2 0.4 0.6 0.8 1.0
Eeff [MV/cm]
Drain Voltage (V) 147
 Benchmark of La-silicate dielectrics
Gate Leakage current Effective Mobility
1.E+04 300
ITRS requirement at 1 MV/cm
1.E+03 250
Solid circle: Our data

Mobility (cm2/Vsec)
Jg at 1 V (A/cm2)

1.E+02 200 La-silicate gate oxide

1.E+01 150

1.E+00 100

1.E-01 50
Our data: La-silicate gate oxide Open square : Hf-based oxides
1.E-02 0
0.3 0.4 0.5 0.6 0.7 0.8 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
EOT (nm) EOT (nm)
L.-Å. Ragnarsson, et al., (IMEC) Microelectron. Eng, vol. 88, no. 7, pp. 1317–1322, 2011.
T. Ando, et al., (IBM) IEDM 2009, p.423

148
 Issues in high-k/metal gate stack
Oxygen concentration control Suppression of gate Reliability: PBTI,
for prevention of EOT increase leakage current NBTI, TDDB
and oxygen vacancy
Endurance for high
formation in high-k
temperature process
Oxygen diffusion control for
Flat metal/high-k O prevention of EOT increase
interface for better
and oxygen vacancy
mobility
formation in high-k

Suppression of Workfunction engineering for

metal diffusion Metal Vth control

Suppression of Suppression of FLP

oxygen vacancy
formation Interface dipole control
High-k
for Vth tuning
Small interfacial state
density at high-k/Si
SiO2-IL Remove contamination
introduced by CVD

Control of interface reaction Si-sub.

and Si diffusion to high-k Thinning or removal of
149 SiO2-IL for small EOT
- Others

150
Variability and Parameter Correlations in FinFETs (GF)
A. Paul et al., pp.361, IEDM2013 (GF)

Ieff variability is captured by the independent variations in Vtlin, Rext and Gm

Rext: External Resistance
Gmmax: Maximum
Transconductance
Vtlin: Threshold Voltage

Increase in Ieff variability

Effects on Ieff varitation

 Vtlin: more dominant in nFETs > pFETs
 Gm: Major contributor
=> Improve surface properties (e.g. H2 bake)
1X 12X  Rext: Increases in larger Nfin
NFins => Improve S/D contacts 151
 Self-Heating Effect in GAA-Si Nanowire FETs (ETH)
R. Rhyner and M. Luisier, pp.790, IEDM2013 (ETH)

The ballisticity, self-heating, and temperature profiles of ultra-scaled Si

NWFETs have been computed through coupled electro-thermal transport
simulation

Large temperature increase at

drain side => Current decrease
1.4
Energy (eV)

0.8
0 x (nm) 40
152
Self Heating in Dielectric Isolated Devices (IBM)
S. Lee et al., pp.T248, VLSI2013 (IBM) Vgs = 0 to 1 V

Vgs = 0.4 to 1.1 V

Heat flow

 The time constant for self heating is

much longer than characteristic switching
times of CMOS logic and memory

 In special cases (e.g. analog I/O, ESD),

the same design practices as used with
planar devices can be applied 153
RTN in High-k/Metal Gate ETSOI (Hitachi)
H. Miki et al., pp.137, VLSI2012 (Hitachi)

 Cumulative Vt map of RTN Shows that

RTN in high-k/metal gate nFETs tends to
be capture limited at normal supply voltage

 Thermal barrier of capture/emission shows

little correlation to Vg coupling

154
Appendix 2

Alternative channel
technologies

155
Ge,III-V bulk properties

156
S. Takagi., IEDM2011, Short course (Tokyo Uni)
 Low Voltage CMOS

Source: S. Takagi
157
 ITRS 2011 for III-V/Ge
http://www.itrs.net/Links/2011ITRS/Home2011.htm

Year of Production 2018 2020 2022 2024 2026

Lg (nm) 14 11.7 9.3 7.4 5.8

Vdd (V) 0.63 0.61 0.58 0.56 0.54
EOT (nm) 0.68 0.62 0.56 0.50 0.45
Mobility enhancement III-V
factor due to
8 8 8 8 8
channel material Ge 4 4 4 4 4
Cg Ideal III-V 0.28 0.24 0.20 0.16 0.13
(fF/mm) Ge 0.41 0.36 0.30 0.25 0.21
III-V 229 230 238 245 251
Vt,sat (mV) Ge 230 231 241 249 254
III-V 0.13 0.11 0.09 0.07 0.06
CV/I (ps)
Ge 0.21 0.17 0.13 0.10 0.08

Manufacturing solutions
are NOT known
158
 ITRS 2011 for III-V/Ge,Contd
http://www.itrs.net/Links/2011ITRS/Home2011.htm

Year of Production 2018 2020 2022 2024 2026

Lg (nm) 14 11.7 9.3 7.4 5.8

Equivalent III-V
Injection velocity
4.29 4.58 5.32 5.93 6.64
Vinj (107 cm/s) Ge 2.26 2.44 2.86 3.19 3.63
Id,sat III-V 2.200 2.343 2.523 2.703 2.884
(mA/mm) Ge 1.769 1.932 2.121 2.330 2.555
Isd,leak (nA/mm) 100 100 100 100 100
Rsd III-V 131 113 96 82 70
(Ω-mm) Ge 149 126 105 85 72
CV2 III-V 0.18 0.15 0.13 0.11 0.09
(fJ/mm) Ge 0.23 0.20 0.16 0.14 0.11

Manufacturing solutions
are NOT known
159
ITRS 2013 for HP logic technology III-V/Ge
http://www.itrs.net/Links/2013ITRS/Home2013.htm

Year of Production 2018 2020 2022 2024 2026

Lg (nm) 14 11.7 9.3 7.4 5.8

Vdd (V) 0.63 0.61 0.58 0.56 0.54
EOT (nm) 0.68 0.62 0.56 0.50 0.45
Mobility enhancement III-V
factor due to
8 8 8 8 8
channel material Ge 4 4 4 4 4
Cg Ideal III-V 0.28 0.24 0.20 0.16 0.13
(fF/mm) Ge 0.41 0.36 0.30 0.25 0.21
III-V 229 230 238 245 251
Vt,sat (mV) Ge 230 231 241 249 254
III-V 0.13 0.11 0.09 0.07 0.06
CV/I (ps)
Ge 0.21 0.17 0.13 0.10 0.08

Manufacturing solutions Manufacturing solutions Manufacturing solutions

exists or being optimized are known are NOT known
160
 ITRS 2013 for III-V/Ge
http://www.itrs.net/Links/2013ITRS/Home2013.htm

Year of Production 2018 2020 2022 2024 2026

Lg (nm) 14 11.7 9.3 7.4 5.8

Equivalent III-V
Injection velocity
4.29 4.58 5.32 5.93 6.64
Vinj (107 cm/s) Ge 2.26 2.44 2.86 3.19 3.63
Id,sat III-V 2.200 2.343 2.523 2.703 2.884
(mA/mm) Ge 1.769 1.932 2.121 2.330 2.555
Isd,leak (nA/mm) 100 100 100 100 100
Rsd III-V 131 113 96 82 70
(Ω-mm) Ge 149 126 105 85 72
CV2 III-V 0.18 0.15 0.13 0.11 0.09
(fJ/mm) Ge 0.23 0.20 0.16 0.14 0.11
Manufacturing solutions Manufacturing solutions Manufacturing solutions
exists or being optimized are known are NOT known

In span of two years (compared to ITRS 2011)

significant improvements in alternative channel
161
device performance has been achieved and
III-V/Ge benchmark for various structures
(2013 and 2014)
ION DIBL Gm-max Peak Mobility
SS (mV/dec) Lch (nm) Dielectric/EOT Vdd (V)
(mA/μm) (mV/V) (μS/μm) (cm2/Vs)
ETB InGaAs-OI Al2O3 1500
0.2 187 5μm 1 - -
Tokyo Uni. 2013 10nm (VDS=0.5V)
Planar InAs 2700
0.6 85 130 - 0.5 40 7100
TSMC 2013 (VDS=0.5V)
Tri-Gate InGaAs Al2O3/HfO2 1500
0.5 77 60 0.5 10 760
SEMATECH 2013 0.7nm/1.6nm (VDS=0.5V)
QW FinFET InGaAs/InP HfO2/Al2O3 450
0.36 190 50 0.5 - -
IMEC 2014 EOT=1.9nm (VDS=0.5V)
Regrown S/D In0.7Ga0.3As HfO2/Al2O3 2000
1 105 40 0.5 150 5500
SEMATECH 2014 3nm/0.7nm (VDS=0.5V)
FinFET InGaAs (In 70%) HfO2/Al2O3 1900
1.16 236 120 0.5 119 3000
Penn State Uni. 2014 3nm/1nm (VDS=0.5V)
Recessed channel Ge Al2O3 600
0.55 - 60 0.5 - -
Purdue Uni. 2014 8nm (VDS=0.5V)
QW MOSFET InGaAs Al2O3 2000
0.55 82 100 0.5 - -
IMEC 2014 EOT=1.1nm (VDS=0.5V)
CMOS InGaAs-OI Al2O3
0.05 80 10μm 1 - - 1200
GNC 2014 7.8nm
CMOS SGOI HfO2
0.02 115 10μm -1 - - 200
GNC 2014 4.5nm
CMOS La2O3/GaAs nFET La2O3/Al2O3
0.15 74 1μm 2 - - 1150
Purdue Uni. 2014 8nm/6nm
CMOS La2O3/GaAs pFET La2O3/Al2O3
0.015 270 1μm -2 - - 162
180
Purdue Uni. 2014 8nm/6nm
III-V/Ge benchmark for various structures
(2011 and 2012)
Planar Gate-all-around
FinFET Tri-gate Nanowire
(metal S/D, Strain, Buffer…) MOSFET

material InGaAs Ge InGaSn InGaAs Ge InGaAs Ge InGaAs Ge InGaAs Ge

(multishell)

7.6 Ao 5.5 nm 10nm-

Dieletric Al2O3/ 5nm ALD 5nm ALD
ALD
HfO2: HfAlO 3.0 nm
HfO2+ SiON 1.2 nm (Al2O3+
/EOT 3.5 nm Al2O3+GeO2
Al2O3 Al2O3 GeO2) Al2O3 11nm 14.8 nm (ALD Al2O3)

Ns: 5e12
~600 e: 200 ~700 701 ~500 ~850
Mobility - - - - -
(cm2/Vs) h: 400 (mS/mm) (mS/mm) (mS/mm) (cm2/Vs)
(cm2/Vs)

W/L=
Lch (nm) 55 50 mm 100 4.5 mm 60 183 50 200 200 65
30/5 mm

DIBL
84 - - 180 - ~50 - 210 - - -
(mV/V)

150K
SS 61pMOS
105 - 145 750 90 130 150 160 - -
(mV/dec) 33nMOS
120K

ION 278 3 4 (n,p) -

10 400 235 180 604 100 731
(mA/mm) (VD=0.5V) (VD=-0.2V) (VD=0.5V) (VD=0.5V) (VD=0.5V) (VD=-1V) (VD=0.5V) (VD=-0.5V) (VD=0.5V) (VD=-1V)

ASTAR
Stanford Purdue Stanford Intel NNDL Purdue Hokkaido AIST
Research Tokyo Uni Tokyo Uni Singapore
Uni VLSI Uni IEDM Uni ELD IEDM Taiwan Uni IEDM Uni, IEDM 163
Tsukuba
Group VLSI 2012 VLSI 2012 IEDM
2012 2009 2007 2011 IEDM 2011 2011 2011 VLSI 2012
2009
 Multi-gate III-V and Si benchmark
InGaAs GAA, Lch=50nm, Dielectric: 10nm Al2O3
nMOS VDS=0.5V (Purdue Uni.)
J. J. Gu et al., pp.769, IEDM2011 (Purdue).
1.E-05 InGaAs Tri-gate, Lg=60 nm,EOT 12A
VDS=0.5V (Intel)
M. Radosavljevic et al., pp.765, IEDM201(Intel).
InGaAs FinFET, Lch=130nm EOT 3.8nm
VDS=0.5V (NUS)
1.E-06 0.5V H. –C. Chin et al., EDL 32, 2 (2011) (NUS)
VDS=0.5V 0.5V InGaAs Nanowire, Lg= 200nm, Tox 14.8nm
IOFF (A/mm)

Si-FinFET 32nm VDS=0.5V(Hokkaido Uni.)

Intel VDD=0.8V [1] K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni).
0.5V 0.5V Metal S/D InGaAs-OI, Lch= 55nm, EOT 3.5nm
1.E-07 VDS=0.5V(Tokyo Uni.)
Si-FinFET 22nm S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni)
0.5V 0.5V Intel VDD=0.8V [1] 0.5V
InAs Surface channel MOSFET, Lch=130nm,
Dielectric: high-k VDS=0.5V (TSMC)
0.5V S. W. Chang, et al., (TSMC) IEDM2013, p.417.
1.E-08
Si-bulk 45nm InGaAs QW Tri-gate, Lch=60nm,
0.5V Intel VDD=1V[2] Dielectric: Al2O3/HfO2 VDS=0.5V (Sematech)
0.5V T. W. Kim, et al., (Sematech) IEDM2013, p.425.
In0.7Ga0.3As FinFET, Lch=120nm,
Dielectric: Al2O3/HfO2 VDS=0.5V (Penn State Uni.)
1.E-09 Arun VT, et al., (Penn State Uni.) VLSI2014, p.72.
0 0.4 0.8 1.2
Recessed Channel Ge nMOSFET, Lch=60nm,
ION (mA/mm) Dielectric: Al2O3 VDS=0.5V (Purdue Uni.)
H. Wu, et al., (Purdue Uni.) VLSI2014, p.82.
[1] C. Auth et al., pp.131, VLSI2012 (Intel). LP InGaAs QW MOSFET, Lch=100nm, Regrown S/D In0.7Ga0.3As, Lch=40nm,
[2] K. Mistry et al., pp.247, Dielectric: Al2O3 VDS=0.5V (IMEC) 164
Dielectric: Al2O3/HfO2 VDS=0.5V (Sematech)
IEDM2007 (Intel). X. Zhou, et al., (IMEC) VLSI2014, p.166. C. –S. Shin, et al., (KANC, Sematch) VLSI2014, p.31.
Multi-gate III-V and Si benchmark(~2012)
1.E-05 1.E-05
nMOS pMOS
InGaAs GAA
Lch=50nm, Dielectric: 10nm Al2O3 GOI Tri-gate
VDS=0.5V (Purdue Uni.) [1] Lg: 65nm. EOT 3.0nm Si-FinFET 22nm
Si-FinFET 32nm VD=-1V (AIST Tsukuba)[6] Intel VDD=0.8V [10]
1.E-06 Intel VDD=0.8V [10] 1.E-06
InGaAs Tri-gate
Ge FinFET
Lg=60 nm,EOT 12A Si-FinFET 32nm
Lg=4.5 mm,
IOFF (A/mm)

VDS=0.5V (Intel) [2]

Dielectric: SiON, VDS=-1V Intel VDD=0.8V [10]
Si-FinFET 22nm (Stanford Uni.)[7]
InGaAs FinFET Intel VDD=0.8V [10]
1.E-07 Lch=130nm 1.E-07
EOT 3.8nm Si-bulk 45nm
VDS=0.5V (NUS)[3] Intel VDD=1V[11]
Ge GAA Lg= 300nm,
InGaAs Nanowire dielectric: GeO2(7nm)-HfO2(10nm)
Lg= 200nm, Tox 14.8nm VD= -0.8V (ASTAR Singapore)[8]
1.E-08 VDS=0.5V(Hokkaido Uni.)[4] 1.E-08
Metal S/D InGaAs-OI
Lch= 55nm, EOT 3.5nm
VDS=0.5V(Tokyo Uni.)[5] Ge Tri-gate Si-bulk 45nm
Lg=183nm, EOT 5.5nm Intel VDD=1V
VD=-1V (NNDL Taiwan)[9]
1.E-09 1.E-09
0 0.4 0.8 1.2 0 0.4 0.8 1.2
ION (mA/mm) ION (mA/mm)
[1] J. J. Gu et al., pp.769, IEDM2011 (Purdue). [6] K. Ikeda et al., pp.165, VLSI2012 (AIST, Tsukuba). [11] K. Mistry et al., pp.247,
[2] M. Radosavljevic et al., pp.765, IEDM201(Intel). [7] J. Feng et al., IEEE EDL 28(2007)637 (Stanford Uni) IEDM2007 (Intel).
[3] H. –C. Chin et al., EDL 32, 2 (2011) (NUS) [8] J. Peng et al., pp.931, IEDM2009 (ASTAR Singapore) 165
[4] K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni). [9] S. Hsu et al., pp.825, IEDM2011 (NNDL Taiwan)
[5] S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni) [10] C. Auth et al., pp.131, VLSI2012 (Intel).
 Device Structures in III-V
J. Lin, IEDM’12 S.H. Kim, IEDM’11 M. Radosavljevic,
IEDM’11

InAs QW MOSFET III-V-OI MOSFET Tri-gate

Recently various device structures have been demonstrated

on InGaAs platform for achieving higher performance at lower
power supply.

Improvement in high-k/III-V interface and III-V growth technology

has been a key factor. 166
 Outline
Alternative channel n-FETs
- Gate Stack
- On Insulator(OI) MOSFETs
- Fin, Tri-Gate, Nanowire (GAA) MOSFET

Ge channel p-FETs
- Planar MOSFET
- Tri-Gate, Nanowire, Recessed Channel

Hybrid CMOS
167
 Outline
Alternative channel n-FETs
- Gate Stack
- On Insulator(OI) MOSFETs
- Fin, Tri-Gate, Nanowire (GAA) MOSFET

Ge channel p-FETs
- Planar MOSFET
- Tri-Gate, Nanowire, Recessed Channel

Hybrid CMOS
168
Implementing high-k material to III-V,Ge
III-V (InGaAs, InAs,InGaSb,…)
ALD-Al2O3 is most commonly used as gate dielectric in planar or Multi-gate
HfO2-only stacks have high Dit (combination of Al2O3 or Al or Si is used)

Al2O3 Si-HfO2 Al2O3+HfO2 HfAlOx TaSiOx

3.4 nm
1.2 nm
In0.7Ga0.3As In0.53Ga0.47As
NUS, VLSI 2012 L. Chu, et al.,APL99, 042908 Hokkaido Uni, IEDM 2011 Intel, IEDM 2010
E. Kim, et al.,
APL96, 012906

Ge
By controlling the
formation of GeOx
at the interface,
HfO2 and Al2O3
show good results. 169
R. Zhang et al., VLSI2012,p161
 Outline
Alternative channel n-FETs
- Gate Stack
- On Insulator(OI) MOSFETs
- Fin, Tri-Gate, Nanowire (GAA) MOSFET

Ge channel p-FETs
- Planar MOSFET
- Tri-Gate, Nanowire, Recessed Channel

Hybrid CMOS
170
Metal S/D InGaAs-OI MOSFET (Tokyo Uni)

Metal S/D and InAs buffer layer are used

as performance boosters.
DIBL=84 mV/V and SS=105 mV/V was
shown for Lch = 55 nm when In-content was
higher.
171
S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni)
Strained InGaAs-OI MOSFET on Si
S. H. Kim, et al., (Tokyo Uni.) VLSI2013, T50.

Strained InGaAs-OI layer on Si by

DWB(direct wafer bonding) with
optional CMP.
MOSFET with 1.7% tensile strain exhibits
1.65x effective mobility enhancement
against InGaAs without strain with high
Ion/Ioff ration~105.
172
 Outline
Alternative channel n-FETs
- Gate Stack
- On Insulator(OI) MOSFETs
- Fin, Tri-Gate, Nanowire (GAA) MOSFET

Ge channel p-FETs
- Planar MOSFET
- Tri-Gate, Nanowire, Recessed Channel

Hybrid CMOS
173
 InAs nMOSFET (higher than HEMT)
S. W. Chang, et al., (TSMC) IEDM2013, p.417.

Using the STI aspect ratio trapping

(ART) technique to introduce high
mobility channel to Si CMOS
platform. Record performance:
Ion=601μA/μm at Ioff=100nA/μm(Vd=0.5V)
gm,ext=2.72mS/μm
S=85mV/dec &DIBL=40mV/V
resulting from breakthroughs in epitaxy and III-V/dielectric interface
174
engineering.
InGaAs FinFET (NSU)
H.C. Chin, et al. (National Uni of Singapore).,
EDL2011,Vol.32 p.146.

LCH= 130nm

DIBL =135 mV/V and drive current

over 840 mA/mm at Lch = 130nm
and Vds = 1.5V was achieved
175
Tri-gate InGaAs QW-FET(Intel)
M. Radosavljevic, et al.(Intel), IEDM2011, p.765.

Tri-gate structure has superiority

electrostatic controllability
compared to ultra-thin body
planar structure
Steepest SS and smallest DIBL
ever reported (Wfin = 30nm) 176
 InGaAs/InP QW FinFET (1)
N. Waldron, et al., (IMEC) VLSI2014, p.26.

Process flow of InGaAs fin formation

using the replacement fin process.
A CET value of 1.9nm is extracted
from a MOSCAP test structure.

177
 InGaAs/InP QW FinFET (2)
N. Waldron, et al., (IMEC) VLSI2014, p.26.

Performance : High-k last processing outperforms High-

SS=190 mV/dec k first processing in an RMG flow.
gm,ext=558 μS/ μm
EOT=1.9nm

178
InGaAs QW Tri-Gate (EOT,1.0nm)
T. W. Kim, et al., (Sematech) IEDM2013, p.425.

Performance at
Vds=0.5V
SS= 77mV/dec
DIBL=10 mV/V
gm,max>1.5mS/μm

BEST balance of gm,max

179
and SS!
 Gate last InGaAs QW FET
C. –S. Shin, et al., (KANC, Sematch, GF) VLSI2014, p.30.

Performance :
SS=80mV/dec.
DIBL=22mV/V
μn,eff>5,500 cm2/V-s at 300k

Gate-last (GL) Further device optimization in the form

In0.7Ga0.3As QW of self-aligned S/D contact will improve
180

MOSFETs with regrown gm,max at short-channel devices.

InGaAs QW MOSFET for LP
X. Zhou, et al., (IMEC) VLSI2014, p.166.

Best planar InGaAs-channel

MOSFETs attributing to InAlAs
buffer, III-V/oxide interface
engineering and S/D regrowth.

Performance at Vds=0.5V
(Lg=100nm EOT=1.1nm):
Ion=550μA/μm @
Ioff=100nA/μm
gm,ext=2.12mS/μm
SS=82mV/dec

181
Gate all around InGaAs MOSFET(Purdue)
P. D. Ye, et al (Purdue Univ)., IEDM2011, Wfin= 50nm
p.769.

Wfin= 30nm

Inversion mode In0.53Ga0.47As

MOSFET with ALD Al2O3/WN with
well electrostatic properties
DIBL was suppressed down to
Lch = 50nm and
Gm,max =701mS/mm at Vds = 1V 182
InGaAs nanowire transistor(Hokkaido Uni)
T. Fukui, et al. (Hokkaido Univ), IEDM2011, p.773.

Core-multishell InGaAs nanowires

grown without buffer layer on Si substrate
(bottom up approach)

At Vd = 1 V peak transconductance of
500 mS/mm is achieved
(roughly x3 InGaAs nanowire)
183
 Outline
Alternative channel n-FETs
- Gate Stack
- On Insulator(OI) MOSFETs
- Fin, Tri-Gate, Nanowire (GAA) MOSFET

Ge channel p-FETs
- Planar MOSFET
- Tri-Gate, Nanowire, Recessed Channel

Hybrid CMOS
184
 Ge pMOSFET EOT=0.6 nm
Y. Shin, et al., (KAIST) VLSI2014, p.82.

Ge pMOSFET with TaN/ZrO2/Zr-

cap/Ge(100) gate stack.
Performance:
Extremely low leakage:250nA/cm2
Extremely low EOT~0.6nm
Low SS =70mV/dec
185
Low hole mobility ~110cm2/Vs!
Ge triangular pMOSFET (NNDL,Taiwan)
S-H. Hsu, et al. (NNDL,Taiwan), IEDM2011, p. 825.
Lg>2Wfin Lg<2Wfin

Ge Rectangular
Selective etching of high defect
Ge near Ge/Si interface is used which
improves gate controllability.

ION/IOFF = 105 and SS= 130 mV/dec

Ge Triangular
And ION= 235 mm/mm at VD= -1V
186
Ge-nanowire pMOSFET (AIST,Tsukuba)
K. Ikeda, et al. (AIST, Tsukuba), VLSI2012, p.165.

Lg= 65nm Wwire= 20nm

VD= -1V
Using Ni-Ge alloy as metal S/D
Vg-Vth= -2V
Significantly reduces contact resistance
VD= -0.5V

VD= High saturation current and high mobility

-0.05V
μeff = 855 cm2/Vs at Ns =5x1012cm-2
and saturation drain current of
731μA/μm at Vd = -1V 187
 Recessed channel Ge nMOSFET
H. Wu, et al., (Purdue Uni.) VLSI2014, p.82.

Test recessed channels, Tch=20nm.

Record performance(at Lch=60nm):

Imax=714mA/mm
gmax=590mS/mm
Ion/Ioff ratio=1E5

188
 Outline
Alternative channel n-FETs
- Gate Stack
- On Insulator(OI) MOSFETs
- Fin, Tri-Gate, Nanowire (GAA) MOSFET

Ge channel p-FETs
- Planar MOSFET
- Tri-Gate, Nanowire, Recessed Channel

Hybrid CMOS
189
Common InGaAs-GeSn gate stack (NUS)
X. Gong, et al. (National Uni of Singapore),
VLSI2012, p.99.

VGS-VTH= 0～2.0V Common gate stack (gate metal and

LG= 5mm dielectric) were used for both p- and n-type
Si2H6 plasma passivation is employed
which creates Si layer at interface.
SS: nMOS: 90 (mV/decade)
pMOS: 190 (mV/decade)
High intrinsic peak GM,Sat=of ~465
μS/μm at VDS=-1.1 V was achieved 190
for LG=250 nm.
InGaSb as channel material (stanford)
Z. Yuan et al., pp.185, VLSI2012 (Stanford Uni)

Hole Mobility Electron Mobility

InGaSb
InGaSb
Si Si

AlGaSb creates barrier

for both electrons and holes Achieving both N- and P-type MOSFET
on a single channel is possible
In-content of 20-40% improves
perfomance
electron/hole mobility > 4000/900cm2/Vs
was gained in a single channel material
ION at LG = 50 mm pMOS: 4 mA/mm
191
nMOS: 3.8 mA/mm
 InGaAs/Ge Dual Channel Inverter
T. Irisawa, et al., (GNC, AIST) VLSI2013, T56.

First dual channel CMOS inverters

composed of InGaAs nFETs and Ge No degradation of Ge pFETs after
pFETs ultizing stacked 3D InGaAs nFETs processing !
integration.

Mobility enhancement of 2.6x and

Inverter, successful down to
3.0x for InGaAs nFETs and Ge 192
Vdd=0.2V !
pFETs against Si FETs respectively.
 3D InGaAs-OI/SGOI CMOS
Schematic of fabricated T. Irisawa, et al., (GNC, AIST) VLSI2014, p.118.

ultimate CMOS structure

composed of InGaAs-
OI/SGOI wire channel
MOSFET w/ independent
back gate.

Mobility enhancement of 2.3x and

2.4x in InGaAs nMOSFET and SG-
OI pMOSFET against Si MOSFET.

Inverter w/ high gain as Vdd down to

0.2V.
193
Co-integration InGaAs and SiGe ETXOI
L. Czornomaz, et al., (IBM) IEDM2013, p.688.

Using DWB(direct wafer bonding) to

get hybrid dual channel ETXOI
substrate.

First co-integration of co-planar SiGe pFETs(65nm) and

InGaAs nFETs(40nm). Height difference only 17nm ! 194
 InAs/GaSb CMOS
M. Yokoyama, et al., (Tokyo Uni.) VLSI2014, p.28.

Hole mobility of GaSb-OI PFET can

exceed Si PFET as
(TInAs,TGaSb)=(2.5nm,20nm).

(a) Difficult to integrate due to the

material difference, InGaAs and
GaSb.
(b) Newly proposed single channel
lII-V CMOS on Si with UTB
InAs/GaSb-OI layer.
Electron mobility of InAs-OI NFET
can exceed Si NFET as 195
(TInAs,TGaSb)=(5nm,20nm).
 La2O3/GaAs CMOS
L. Dong, et al., (Purdue Uni.) VLSI2014, p.50.

GaAs CMOS invertor: a gain of

Flat and sharp interface. ~12 is achieved with V =3V. Oscillation
DD
frequency
increase from
Mobility in moderate Ninv slightly 0.35-3.87MHz
increased due to less phonon as VDD from 1
scattering and the decreasing at – 2.75V.
low Ninv is by the influence of
Coulomb scattering.

Dit greatly reduced compared to 196

amorphous Al2O3/GaAs interface.
 Appendix 3

T-FET technologies

197
 Tunnel FET
A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)

OFF ON
Vg = 0V Vg = 1V

Band to band tunneling

Low IOFF, Low VDD, SS<60mV/decade 198

 ION and IOFF of TFETs
A.M. Ionescu, IEDM2013 Short Course (EPFL) L. Knoll et al., pp. 100, IEDM2013 (Jülich)
Q. Liu et al., pp.228, IEDM2013 (ST). A. Villalon et al., pp. 66, VLSI2014 (CEA-LETI)
Y. Morita et al., pp. 236, VLSI2013 (AIST) C. Auth et al., pp.131, VLSI2012 (Intel).
0.05 < VDS < 0.6 V 0.3 < VDS < 0.5 V
Si, Ge TFET 0.9 < VDS < 1.2 V III-V TFET 1.0 < VDS < 1.5 V
104 104
SOI 14nm node (Lg=20nm) VDD=0.75V (ST) Tri-gate 22nm node SOI 14nm node (Lg=20nm)
Tri-gate 22nm node (Lg=30nm) (Lg=30nm) VDD=0.75V (ST)
103 VDD=0.8V (Intel) VDD=0.8V (Intel)
Leonelli 2011
Villalon 2014
103 Zhou 2012 Dey 2012
Mohata 2012
102 Jeon 2011 Si Si, silicides S/D
Ion (mA/mm)

InAs/GaSb GaSb/InAsSb

Ion (mA/mm)
SiGe NW tri-gate GaAsSb/InGaAs
Ghandi 2011
Knoll 2013
101 Si NW
Knoll 2012 strained Si 102 Zhou 2012
Chang 2013 Si Zhao 2011 Li 2012
strained Si NW GAA InGaAs/InP
InGaAs AlGaSb/InAs
100 NW tri-gate
Morita 2013 Si Fin Q. Huang 2011 Si 101 Moseiund (IBM) Mookerjea 2009 InGaAs
2012 Si/InAs
10-1 Krishnamohan 2009 GOI Dewey (Intel) 2011 InGaAs
Moselund 2011
10-2 Si NW
Q. Huang 2012 Si
100 Tomioka 2012 Si/InAs
Mayer 2008 Si Schmid (IBM) Tomioka 2011 Si/InAs
2011 Si/InAs
10-3 10-1
10-2 10-1 100 101 102 103 104
10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101
Ioff (pA/mm) Ioff (mA/mm)
Si TFETs show the low Ioff, while Ion enhancement is still challenge.
Strain is efficient for Ion enhancement in Si and Ge TFETs.
199
III-V provide high Ion, however, suffer from unacceptably high Ioff.
 Benchmark of TFETs
H. Lu and A. Seabaugh, vol. 2, No. 4, pp. 44, Journal of Electron Device society (Univ. Notre Dame)

The highest current is in the range of 1 ~ 10 nA/mm accompanied by

sub-threshold swing below 60 mV/dec. 200
 Tunnel FET performance comparison
A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)
measured III-V channel TFETs

Average SS:
SMIN: Most common SS which is
the inverse of ID-VGS slope Ith
at the steepest part
ID
VOFF=0 VTH=VDD/2
SEFF: Is the average swing when I
OFF
VTH=VDD/2 Effective SS:
VOFF=0 Voff VTH
201
VGS
 ION and IOFF of TFETs
[1] G. Zhou et al., pp. 782, vol. 33, no. 6, EDL 2012 (University of Notre Dame)

10000

Si MOSFET
1000
TFET
VDS=0.75V Intel

IOFF [nA/mm]
100 Bulk 32nm
VDD=0.8V
TFET Intel
Bulk 45nm
10 VDS=1.05V VDD=1V

1
TFET
VDS=1V Intel
0.1 Tri-Gate 22nm
VDD=0.8V

0.01
0.01 0.1 1 10
ION [mA/mm]

C. Auth et al., pp.131, VLSI2012 (Intel).

202
K. Mistry et al., pp.247, IEDM2007 (Intel).
 Tunnel FET (III-V)
K. Tomioka et al., pp.47, VLSI2012 (Hokkaido University)

SS=21mV/dec SS=110mV/dec
VDS=1V

HfAlOx
Gate
Conventional FET limit
SS= 60 mV/dec

VDS= 1V

NW Diameter= 30nm
SS of TFET is function of VG due to Zener tunnel current
Minimum SS= 21 mV/dec is reached due to optimized
series resistance of contact, undoped InAs and InAs/Si
ION/IOFF~106 at VDS= 1.0V (ION= 1Am/mm) 203
 Strained SiGe nanowire TFETs
A. Villalon et al., pp. 66, VLSI2014 (CEA-LETI)

Ion enhancement up to 760mA/mm.

Low bandgap of SiGe increase BTBT.

SS lower than 60 mV/dec is

still challenge to be addressed.
204
 Si NW TFET with Silicide S/D
L. Knoll et al., pp. 100, IEDM2013 (Jülich)

Ni(AlxSi1-x)2 can avoid encroachment

into channel region.
Ion at 64mA/mm at VDD = 1V.

Scaling diameter of NW can

improved performance. 205
 Fin-shape Si-TFET
Y. Morita et al., pp. 236, VLSI2013 (AIST)

Multi-gate can enhance

electric field, particularly at
the corner, resulting in better
performance.

Scaling Fin-width provide

SS lower than 60 mV/dec.

206
 Isoelectronic trap for improving TFET
T. Mori et al., pp. 68, VLSI2014 (AIST)

Al-N complex can introduce

isoelectronic trap (IET) below Si CB.

Tunneling probability is increased

through the intermediary of IET.
207
 TFET vs. MOSFET at low VDD
A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)

VDD 0.3~0.35V
TFET 8x faster at the same power
“parameter variation is not a
significant factor for differentiation
between MOSFET and TFET”
208
 Tunnel FET (Si)
A. Villalon, pp.49, VLSI 2012 (CEA-LETI)

X in Si1-xGex is optimized to allow for efficient BTBT

LG= 200nm
ION/IOFF~105

Reducing SiGe
Body thickness improves
Subthreshold swing.
130mV/dec
209
Gate Voltage (V) 190mV/dec
 Device structure
A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)

210
K. Tomioka et al., pp.47, VLSI2012 (Hokkaido University)
 Appendix 4.
2D channel material
technologies

211
 Why 2D channels?
 High-drivability FinFET  Mobility degradation in
 Large Weff/Wfootprint thin Si < 10 nm for both
 Taller Fin electron & hole.
 Narrow Fin pitch High-mobility
 Thinner Fin 2D channels

K. Uchida, et. al., IEDM, 23.1, 2008. S. Kobayashi, et. al., J. Appl. Phys. 106, 024511 (2009).
212
 Family of 2D materials
Vacuum Graphene Oxide Transition metal
0
family family dichalcogenide (TMD)
family
-1 MX2
M: Cr, Mo, W, etc.
Energy [eV]

-2 X: S, Se, Te, etc.

WSe2
MoSe2
-3
TiO2 RuO2
Graphene
-4
1.2 1.6 0.4
1.1 ~ 5.9 1.6 1.4
-5 1.8
~ 3 2.7
Silicene WTe2
-6 MoTe2
Si
WS2
MoS2
-7 h-BN
213
 TMD band structure
 MX2  MoX2 & WX2
Jun Kang, et. al., Applied Physics Letters 102, 012111 (2013).

Mo Mo
S S
MoS2 MoS2

Tokyo Tech. 0.65 nm

214
Dependence on # of layers in MoS2 & WS2

Agnieszka Kuc, et. al., Phys. Rev. B 83,

245213 (2011).

215
 Synthesis of MoS2
 Exfoliation  Dipping & annealing
Scotch tape
Liquid Exfoliation

Valeria Nicolosi et al., Science, 2013: Vol. 340 no. 6139 Keng-Ku Liu et al., Nano Lett., 2012, 12 (3), pp 1538–1544
216
 Synthesis of MoS2
 Chemical vapor  RF magnetron
deposition (CVD) sputtering
RF

Substrate

Accelerated
Ar ions
Ar+ Plasma
Ar+

MoS2 Target

Takumi Ohashi, Bachelor thesis, Tokyo Institute of

H. Wang, et. al., IEDM, 4.6, 2012. Technology, 2014.
217
 Exfoliated single-layer MoS2 nMISFET
 217 cm2/Vs,  Depletion mode
electron

B. Radisavljevic et al., Nature Nanotech. 6, 147 (2011)

218
 Exfoliated 6-layer MoS2 nMISFET
 ~ 4 nm 6 MLs  Depletion mode

Lingming Yang, et. al., Symposium on VLSI Technology 2014, T-21.6.

219
CVD-single-layer MoS2 nMISFET
 Mobility  Depletion mode
~ 190 cm2/Vs

H. Wang, et. al., IEDM, 4.6, 2012.

220
 Monolayer-MoS2 nMISFET simulation
 Non-equilibrium Green’s
function
 Heavier electron effective
mass
 m* = 0.45m0
 Immunity to short channel
effects
 DIBL ∼ 10 mV/V
 S-factor: 60 mV/dec.
 Larger Ion/Ioff ratio than
III-V FET

Youngki Yoon, et. al., Nano Lett., 2011, 11 (9), pp 3768–3773.

221
Summary of band-gaps of TMDs

eV Ti Zr Hf V Nb Ta Mo W
1.8 (SL) 1.93 (SL),
1.95 (D), 1.68 (D), 2.7 (D),
S2 Metal Metal Metal 1.72(D) 1.77 (D),
0.3 (I) 2.1(I) 1.93 (I)
1.2 (I) 1.35 (I)
1.49(SL),
1.55 (D), 1.20 (D), 1.77 (D), 1.6 (D)
Se2 Metal Metal Metal 1.38 (D),
0.15 (I) 1.61(I) 1.18 (I) 1.1 (I)
1.1 (I)
1.0 (D) 1.13 (SL),
Semi- Semi- Semi- Semi-
Te2 Semi- Metal Semi-
metal metal metal metal
metal metal

Ian Post, Symposium on VLSI Technology, 2013, Short Course

222
 Appendix 5.
Other emerging
technologies

223
ON-state resistance [Ohm]
MEMS relay

ION/IOFF of ~1010

Ultra-low-power digital
logic applications.

Number of Operation Cycles

Frequency of 1, 5, 25kHz under operation 224
T. K. Liu et al., pp. 43, VLSI2012 (UC Berkeley)
 Si Junctionless Transistor (Intel)
R. Rios et al., EDL. 32(2011)1170
(Intel)

20 30 40 20 30 40 20 30 40
Lg (nm) Lg (nm) Lg (nm)
IM : Conventional Inversion Mode
JAM LD : Janctionless Accumulation Mode with
low dope
JAM HD : Janctionless Accumulation Mode with
high dope
JAM devices have reduced gate control and degraded short-
channel characteristics relative to IM
225
Not suitable for high-performance logic (high Ion and moderate Ioff)
 Nanowire Junctionless Transistor
J. P. Colinge et al., Nature Nano. 5(2010)225

Lg= 1mm
Wwire= 30nm

Lg= 1mm

Near-ideal subthreshold slope,

close to 60 mV/dec at room
temperature, and extremely low
leakage currents
Silicon nanowire is uniformly doped
Gate material is opposite ION/IOFF~1x106 (-1<Vg<1)
polarity polysilicon 226
IOFFis smaller than 10-15 A
 Carbon nanotube and Graphene
K. Banerjee, UC Santa Barbara, G-COE PICE International Symposium on Silicon Nano Devices in 2030

SWCNT : single wall carbon nanotube

GNR : graphene nano ribbon

Carbon materials for FET applications

・ an ultra-thin body for aggressive channel length scaling
・ excellent intrinsic transport properties similar to carbon
nanotubes
227
・ pattern the desired device structures
 Sub-10nm carbon nanotube transistor
A. D. Franklin et al., pp.525, IEDM2011 (IBM)

Transistor operation with Lch of 9nm 228

 Graphene Field-effect Transistor
Z. Chen et al., pp.509, IEDM2008 (IBM) J. B. Oostinga et al., Nature Materials 7 (2008) 151

・Ambipolar Characteristics
・Bi-layer graphene and
double gates can open the
gap
229
 Spin transfer Torque Switching MOSFET
T. Marukame et al., pp.215, IEDM2009 (Toshiba)

Magnetic tunnel junction on S/D

Lg = 1mm

Read/write are enabled by using ferromagnetic electrodes and

230
Spin-polarized current