TUTORIAL ON FINFET

&
LAB HANDOUT ON ION IMPLANTATION USING
ATHENA-SILVACO TCAD

SUBMITTED BY
Abinaya B (MT20201)
Nallandula Meghana ( MT20191)
Sahil Yadev ( 2018185 )
Shubham Manjhi ( 2018194 )

Submitted to : Dr. Sudhanshu Shekhar Jamuar

 ELECTRONICS AND COMMUNICATION ENGINEERING
INDRAPRASTHA INSTITUTE OF INFORMATION TECHNOLOGY
DELHI NEW DELHI– 110020
November, 2021

Abstract

Raw silicon being neither a perfect insulator nor a perfect conductor, electricity flow in
transistors can be obtained by smattering Boron or phosphorus atoms into the crystal lattice and the
whole process is called ion implantation. As the technology advanced over years, the need for
smaller and effective devices increased. But these advantages were at the cost of small dimensions
effects or second order effects which led to the new innovative device structures such as SOI,
FinFET etc. In FinFET, the gate structure is wrapped around the channel and the body is thin
providing better characteristics suffering less from dopant induced variations. FinFET is known for
its advantages such as high-drive current, high speed, low leakage and lower power consumption.
But, the manufacturing process of FinFET demands little complexity over other technologies.

This paper covers details about software tools performing 3D simulations covering fin
patterning, defect free crystal after annealing, Heated ion implantation method etc. TSUPREM4
contains a Monte Carlo model that models crystalline silicon as well as amorphous models for
silicon and different other materials. Simulation method consists of 4 steps. First of all, we consider
the ions extracted from the plasma by the electric field going through the sheath layer. Collisions in
the sheath layer generate angular dispersion in the ions trajectory and energy dispersion. The ions
also push gas atoms, called recoil atoms to the substrate. From this, we will obtain the angular and
energy distribution of the ions and recoil atoms. Next, we calculate the incident particle distribution
along the geometry of the substrate using the obtained angular distribution. Finally, the depth
concentration profile is computed. Different Gaussian distributions are performed to find the
implanted impurity distributions. This paper covers different simulation methods carried out to
decide the optimum parameters and comparison of different parameters with different devices with
respect to that particular node.

Contents
1. Introduction
1.1. .
1.2. .
1.3. .
2. .
2.1. .
2.2. .
2.3. .
2.4. .
3. FinFET Fabrication.
3.1. .
3.2. .
3.3. .
3.4. .
4. Comparison : FinFET Vs Other Devices
4.1. .
4.2. .
4.3. .
5. Ion Implantation
5.1.

Chapter 1
FinFet ( Fin Field Effect transistor )

❖ What is FinFET?
 ➢ FinFETs are non-planar transistors and structurally as opposed to planar MOSFETs.
➢ Term FinFET was coined by Chenming Hu, Tsu-Jae King-Liu and Jeffrey Bokor in
2001, due to the fin-shaped vertical structure.
➢ FinFET is an example of a multi-gate transistor.
➢ Intel redesigned FinFETs as tri-gate transistors and have used it in 22 nm technology
and below.
➢ Global Foundries, TSMC, Samsung are using FinFET in 7 nm/10 nm/14 nm/16 nm
technology nodes.

❖ Classification in FinFETs
Classification in FinFETs is given below :
❖ Shorted Gate (SG) vs. Independent Gate (IG)
➢ The shorted-gate FET (SG FinFET) has the front and back gates short-circuited and
only one terminal. It is a three-terminal device: source, drain, and gate. There is no
external control for the threshold voltage.

➢ The independent-gate FET (IG FinFET) is a four-terminal device. This arrangement

is a double-gate device with the gate electrodes isolated by a masked etch to allow
for separate biasing (separate channel control) on the two gates.

❖ SOI FinFET vs. Bulk FinFET

 Variation in Fin height and thickness is less in SOI FinFet as compared to bulk
FinFET. Bulk FinFET gives better heat dissipation than SOI FinFET. In bulk FinFETs,
source and drain regions are connected through bulk silicon underneath and form parasitic
npn BJT and parasitic current can still flow underneath. This problem is not encountered in
SOI FinFET. Source and Drain regions are easier to grow in bulk type FinFETs while it is a
relatively more complex process in SOI FinFET.

❖ Why we Need for FinFET

■ Short channel effects
■ Power supply not scaling
■ Increasing power density
 ■ Thin gate dielectric
■ Increased current leakages
■ Frequency not increasing significantly

❖ Scaling: Possible Solutions

➢Short Channel Effects
1. Improve gate control over the channel (eg. Double Gate MOSFET, FinFETS,
GAA).
2. Changing device structure (eg. FinFETS vertical structure).
3. Using 2D, 1D and even 0D devices (eg. of 2D is CNT based or Graphene
based transistors, 1D uses nano wires and 0D devices make use of single
electron transistors).

➢Improved Performance
1. Using III/V materials as a substitute for silicon.
2. New interconnect materials.
3. Strained silicon.

➢Power Constraints
1. Using steep subthreshold devices like TFET, NEMS, NCFET.
❖ Why Do MOSFETs Require Scaling?
1. To increase the transistor density of a particular chip.
2. Increasing the transistor density implies increased functionalities for constant area
footprint.
3. To improve performance in terms of speed.
4. Cost of fabrication per transistor decreases with scaling.

❖ Evolution of FinFET
➢ Performance is limited because of short channel effects and subthreshold slope.
➢ Variability increases as the transistors keep getting smaller.
➢ Limitations in power consumption.
➢ Scaling made possible all the devices shown.
➢ With advancement in MOSFET, the control of gates over the channel increased.
❖ Important parameters for the FinFET
Tfin plays an important role in determining the Subthreshold Slope.
W = width of the transistor
Xj = Junction Depth
Xov = source/drain overlap region with gate
N = number of fins

• W = n(2*Hfin + Tfin )
• Xj = Tfin
• Leff = LG – 2*XOV
❖ FinFETs: Design Consideration

➢ Short Channel performance of FinFET is related to L/Wfin ratio.

➢ A ratio of L/Wfin greater than 1.5 is generally used.
➢ Lower short channel effects are observed with thin fins and longer lengths.
➢ But for scaling we do not increase length rather we decrease the fin width, while
maintaining the ratio.

❖ FinFETs: Design Consideration

➢ Increasing the height and reducing the width of the fin results in better control over
the channel due to confinement of the carriers.

➢ Fins are also made taller to allow more current per layout area. But, too tall a fin
makes it fragile.

➢ For 14nm and 7nm L/Wfin ratio of approx. 2.5 is used.

❖ FinFETs: Characteristics
1. Better gate control over the channel.
2. Lower subthreshold swing.
3. Lower leakage current.
4. Lower short-channel effects.
5. Lesser delay for the same voltage applied.
6. Has lower delay even at low operating voltages.
7. Has lower power consumption.

❖ FinFETs: Subthreshold Swing

➢ Subthreshold swing can be changed by changing the buried oxide and substrate
thickness.

➢ The subthreshold swing improves with increase in silicon substrate thickness to

buried oxide thickness ratio (tSi/tBOX).

➢ Subthreshold swing reduces on increasing the height of the fin and reducing the
width of the fin. This is because of the larger area for current to flow.
❖ FinFETs: Effect of Temperature
➢ With increase in temperature the mobility of the carriers reduces as the lattice itself
starts vibrating, and more collisions take place thereby the saturation current reduces.

➢ Also, the threshold voltage decreases due to increase in the number of carriers in the
channel.

❖ Current Distribution In A FinFET

1. At low gate bias, the current distribution is maximum at the middle of the channel.
However, the gate control is minimum in the middle of the channel and this results in
off-state leakage current.

2. At higher gate voltages the current density distribution is maximum at the Fin-oxide
interface.

3. Thus, due to this non-uniform nature of the current density distribution for different
gate biases, FinFET models are much more complicated than planar MOSFETs.
❖ Advantages of FinFETs
1. Low wafer costs

2. Low defect density

3. Less back-bias effect

4. Good Process Compatibility

5. Excellent SCE controls

6. Double gates are self aligned.

7. Insensitivity to channel doping

❖ FinFETs: Challenges
➢ Due to its unique design FinFETs face their own set of challenges. Some of these
challenges include:
1. Device width quantization
2. Corner Effect
 3. Shadowing Effect
4. Non-uniform fin structure
5. Increased Parasitic
6. Increased Electromigration

❖ Corner Effect
➢ The corner effect is known as increased subthreshold leakage current at the corners
of the vertical sidewalls and the top surfaces.
➢ To reduce corner effect:
1. Deposit layer of SiN at the top
2. Implant dopant such that threshold voltage increases at the corners.
3. Fins are made rounded, the radius less is the corner effect.
❖ Shadowing Effect
1. If uniform Implantation of source and drain part of fin is done at tilt angle then
implantation gets shadowed by the resist.
2. Plasma doping is used in which the fins are immersed into plasma.

❖ Non-uniform fin structure

1. Performance sensitive to fins width and height.
2. Threshold voltage for each fin can change due to different fin structures.
3. Bias pulsing can be used to create uniform films.

❖ Increased Parasitic
1. Increased overlap increases parasitic capacitance.
2. 3D structure introduces more fringing capacitance.
3. Therefore increased complexity to model these.
❖ FINFET I-V Curve
● Tri-gate provides steepest sub-threshold slope and best short-channel values (DIBL) values.

❖ FinFETs: Optimization
➢ Rounded fins to reduce corner effect. It can be done using hydrogen annealing.
➢ Source and Drain fin doping, trade-off between short channel effects and source and
drain resistance.
➢ Strain engineering improves mobility
➢ Using III-V group elements for increased mobility.
 ➢ Changing the orientation of fins from (110) to (100) for higher electron mobility.
➢ Thinner and taller fins. Reduces RC delay but increases energy. Keep aspect ratio in
check.

❖ NEXT in the Future

❖ Comparisons :
➢Double Gate vs. Tri-Gate FinFETs

■ Double-gate FinFETs have a dielectric layer – called a hard mask – above the
fin to inhibit the electric field. The dielectric layer prevents parasitic
inversion channels at the top corners. The gate control is from the sides and
not from the top.

■ Tri-gate denotes a single gate electrode folded over three sides of the fin.
There is no inhibition of the electric field above the fin in the tri-gate, and the
gate exerts control from all the three sides.
➢FinFET Vs CMOS
■ FinFET has lower DIBL than CMOS and hence the subthreshold leakage is
lower in case of FinFET than CMOS which is having higher subthreshold
leakage.
■ The retention voltage of FinFET is low when compared to CMOS which
requires higher retention voltages in memory design.
■ FinFET shows a better performance than CMOS when the power budget is
the same.
■ FinFET has better performance compared to CMOS because the induced
dopant variation is less as channel doping is low in case of FinFET.
■ FinFET has low static and dynamic power as it can operate at low voltages
compared to CMOS.
■ FinFET has a better control over the channel even at low voltages compared
to CMOS.
■ FinFET has less short channel effect and hence also reduces the need of
guard banding compared to CMOS.

➢FinFET Vs MOSFET
■ FINFETs have higher transconductance as compared to MOSFETs.
■ The power dissipation is more in MOSFET as compared to FINFET.
■ The multiple fins in FINFET helps to reduce leakage currents whereas in
MOSFET the major problem is the control of leakage current is difficult.
■ FINFET has a faster switching speed because of the lower input capacitance
and higher dynamic current density.
■ FinFET occupies less area or space on the chip and hence leads to the
 reduction in cost, compared to MOSFET.
■ FINFETs consume less wafer area per transistor in order to get high gain
because the fin height can be increased if we need a higher gain.
■ FINFETs have lower input capacitance for the same gain as compared to
MOSFETs.

Chapter 2
FinFET Fabrication

1.Introduction
Since the fabrication of MOSFET, the minimum channel length has been shrinking
continuously. As devices shrink further and further, the problems with conventional (planar)
MOSFETs are increasing. Industry is currently at the 90nm node (ie. DRAM half metal pitch,
which corresponds to gate lengths of about 70 nm). As we go down to the 65nm, 45nm, etc nodes,
there seem to be no viable options of continuing forth with the conventional MOSFET. The
motivation behind this decrease has been an increasing interest in high speed devices and in very
large scale integrated circuits. The sustained scaling of conventional bulk devices requires
innovations to circumvent the barriers of fundamental physics constraining the conventional
MOSFET device structure.
 Alternative device structures based on silicon-on-insulator (SOI) technology have emerged as
an effective means of extending MOS scaling beyond bulk limits for mainstream high-performance
or low-power applications . Partially depleted (PD) SOI was the first SOI technology introduced for
high-performance microprocessor applications. The ultra-thin-body fully depleted (FD) SOI and the
non-planar FinFET device structures promise to be the potential “future” technology/device choices.
Here, we review the design challenges of these emerging technologies with particular emphasis on
the implications and impacts of individual device scaling elements and unique device structures on
the circuit design. The FinFET is the easiest one to fabricate.

The key challenges in FinFET fabrication are the thin, uniform fin and also in reducing the
source-drain series resistance. FinFET have broadly been reported to have been fabricated divided in
2 ways :
■ Gate-first process: Here the gate stack is patterned/formed first, and then
the source and drain regions are formed. Fabrication steps after the fin
formation are similar to that in a conventional bulk MOSFET process.

■ Gate-last process (also called replacement gate process): Here source

and drain regions are formed first and then the gate is formed. The
source/drain is formed immediately after fin patterning.
2.General layout and Mode of operation

- The basic electrical layout of Finfet does not differ from a traditional
field effect of a transistor as well as mode of operation. The current
flow is controlled by one source and one drain contact as well as
gate.
There are two structures of FinFET :-
■ Planar
■ Three Dimensional
 The heart of the FINFET is a thin Si fin, which serves as a body of the MOSFET. A heavily
doped poly Si film wraps around the fin and makes the electrical contact to the vertical faces of the
fin. A gap is etched through the poly Si film to separate the source and drain. The various steps in
the fabrication of FINFETs are discussed as follows.

3.Fabrication Steps
The fabrication process is mainly divided into four basic steps given below :
■ Fin fabrication and patterning
● Subtractive Fin Process
 ● Replacement Fin Process
■ Gate stack fabrication
■ Source and Drain implantation
■ Deposition of Contact and interconnect

❖Fin fabrication and patterning

FinFets fins can mainly be fabricated in two ways either by Subtractive fin process
or Replacement fin process on SOI or bulk substrate technology.

➢Subtractive Fin Process

Given Below are the steps followed in this Process :-
■ Fin Generation is done by silicon substrate which is taken as the
starting material deposited with Silicon Nitride ( Si3N4 ) layer on the
top followed by an amorphous silicon hard mask.
■ Depending on the pattern by Fin Generation on Fin, the device is
categorized as either Planar or 3D.
■ Pre-Implementation of n-well and p-well is done before the patterning
of the fins.
■ Patterning the films is done by using the Self Aligning Double
patterning approach. Using a mandrel spacers are placed which are
 twice the density or half the pitch. Now, the mandrel is removed and
the etching of spacers is done into these hard masks.
■ The hard mask removal is done by Etching of the hard mask.
■ This hard mask is patterned in the silicon wafer and the silicon fins
are formed
■ At this stage the decision is made whether to remove or keep the
silicon nitride so that the decision can be made whether Si layer or
Si3N4 is used for current conduction.
● If the Si3N4 is kept as a top layer, then it will be used for
current conduction then it will result in FinFET or Double-
Gate Device.
● If the Si3N4 is kept as a top layer, then it will be used for
current conduction then it will result in FinFET or Double-
Gate Device.
■ On the top of the fins, we have silicon nitride, and we fill up these
trenches with an oxide
■ Planarizing the oxide layer using a hard mask as a stop layer is done
by Chemical Mechanical Polishing ( CMP ).
■ Chemical Vapour Deposition :
◆ SiN and SiO layers are deposited on Si film to make a
hard mask or a cover layer.
◆ The cover layer will protect the Si fin throughout the
fabrication process.
◆ Then, a layer of SiO2 is developed by the process of
dry etching.
◆ The layer of SiO2 is used to relieve stress.
■ Etching of the oxide and the height of the fin depends on how deep
the oxide is etched.
 ■ The width of the FinFET device is equal to the width of the spacer
which is defined at the time of patterning.

➢Replacement Fin Process

Replacement Fin fabrication process steps are given below :-
■ Fin Generation is done by silicon substrate which is taken as the
starting material deposited with Silicon Nitride ( Si3N4 ) layer on the
top followed by an amorphous silicon hard mask. Silicon Nitride
thickness is more as compared to Substrate Fin Process.

■ Pre-Implementation of n-well and p-well is done before the patterning

of the fins.

■ Patterning the films is done by using the Self Aligning Double

patterning approach. Using a mandrel spacers are placed which are
twice the density or half the pitch. Now, the mandrel is removed and
the etching of spacers is done into these hard masks.

■ The width of the spacer defines the width of the FINFET device.

■ Etching of the spacer into the hard mask and etching of this hard
mask pattern is done into the silicon nitride. After this we get silicon
nitride fins and the hard mask is removed.

■ The trenches between the nitride layer are filled with oxide layers.

■ Chemical Mechanical Polishing (CMP) is performed to planarize the

oxide layer using a hard mask as a stop layer.

■ The silicon nitride layer is removed which was present in between

and we are left with the dielectric mold that is made of SiO2.

■ In between the dielectric mold, we can grow the material that we

want to use to make the fins. Here we are using Silicon or epitaxy of
silicon as the material to grow the fins.
 ■ Etching of the oxide layer to reveal these fins. The height of the
FINFET device is decided by how deep we etch the oxide.

These two approaches can be used to make the fins. The replacement fin approach is better
than the Subtractive fin approach as we can grow the fin with any material. For eg: if we want to
make the fin with some other material like SiGe, InP (Indium phosphide) because it can trap or
capture these defects (stacking faults) into this high aspect ratio structure of mold and the resulting
film towards the top is defect free. This process is known as aspect ratio trapping.

❖ Gate stack fabrication

After the fins have been formed by either of the processes, the gate oxide is
deposited on top of the fins via thermal oxidation to isolate the channel from the gate
electrode. Since the fins are still connected underneath the oxide, a high-dose angled implant
at the base of the fin creates a dopant junction and completes the isolation.

Deposition of the gate: Finally a highly n+-doped polysilicon layer is deposited on

top of the fins, thus up to three gates are wrapped around the channel: one on each side of
the fin, and - depending on the thickness of the gate oxide on top - a third gate above.Then
after doing Electron beam lithography and mask trimming the length of the gate is now
scaled to appropriate length

The fine Si fin is patterned by EB Lithography with 100keV acceleration energy.

The resist pattern is slightly ashed at 5W and 30 sec to reduce the Si fin width. Then using
 the top SiO layer as a hard etching mask, the SiO layer is etched. By this process, the
silicon fin is patterned.

❖ Source and Drain implantation

● Etching of the polysilicon in the unmasked area is done.
● Offset fin spacer formation is done.
● Source/Drain and gate Ion Implantation: Phosphorus ion implantation is done to
introduce
● dopants into the polysilicon gate and source and drain.

❖Deposition of Contact and interconnect

● After this, gate sidewalls are formed followed by source/drain ion implantation and
annealing.
● Now, sallicidation is done in which CoSi2 film is formed on the top of the poly gate.
● At last metal contacts are deposited, patterned and etched. Contact deposition allows
the device to be assessed to be tested or connected to other devices, creating a
circuit.
4.Challenges in Fabrication
■ Uniform doping is much more difficult to obtain because of fin shadowing;
here one fin acts as a mask for the other fin during ion-implantation.
■ A thin silicon layer is liable to complete fin amorphisation during
Source/Drain ion implantation, it leads to recrystallization during annealing.
This problem gives rise to Boundary defects and possibly poly-crystalline
fins consequently increasing Source/Drain series resistance.
■ The doping challenge is related to silicon amorphisation and uniformity.
Uniform doping is much difficult to obtain due to fin shadowing, here one fin
acts as mask for other fin during ion-implantation
■ Should be focused on Critical Parameters in FinFet During Fabrication
Process. Because special attention is required towards sidewall roughness as
it is responsible for increasing mobility scattering, thus degrading device
performance.
■ Metal Gate should fully envelop the fin, with uniform thickness and proper
step coverage.
■ Complexity is increased by formation of long fins in terms of poly gate,
replacement metal gate and spacer integration with each other. e.g.
◆ Good amount of over-etching is done to remove residual poly
and offset spacers on fin sidewalls to facilitate epitaxial S/D
growth.
◆ Challenging to etch poly gates with high aspect ratio and at
the same time precise control on dimensions.
 Both these over etching damages fin, optimized dry and wet etching is used
to produce gate with minimum fin loss and Lg variation.

Chapter 3
Ion Implantation

❖ Introduction
A low-temperature technique to dope impurities into semiconductors and has more
flexibility when compared to diffusion. In Mos transistors, ion implantation can model
threshold voltage accurately. Here the dopant atoms are volatilized, ionized, accelerated,
separated by the mass to change ratios. Which are directed at a target which is a silicon
substrate. In the crystal lattice, the induced atoms collide with the host atoms, lose energy
and finally rest some depth within the solid. The penetration depth depends on the substrate
material used, dopants induced and energy of acceleration performed.

❖ Ion Stopping
 When the implanted ions impinge on to the target, the series of collisions take place
where at some depth, they finally stop. Since the initial acceleration energy is much higher
than the lattice binding energies, this ion scattering process can be simulated based on the
elastic collisions between pairs of nuclei ignoring the relatively weak lattice forces. There
exists another component of scattering which comes from the inelastic collisions with
electrons in the substrate target. So, the total stopping power S process defined by the
energy loss (E) per unit path length (x) is the sum of the above.

Monte Carlo calculation of 128 ion trajectories for 50 KeV boron implemented into silicon is
shown in figure 1.

Figure 1

The relative distribution to S of each of the following terms over a wide energy
range is shown in the figure 2. Energies which constitute more for ion implantation, 10 to
200 KeV, fall at the far left which is a reason dominated by nuclear stopping. Here V 0 is the
Bohr velocity and Z1 is the ion atomic number. Nuclear stopping is caused by a collision
between two atoms.
 Figure 2

Inelastic collisions constitute electronic stopping, which is caused by the interaction

between the incoming ion and electrons in the target. Modelling this theoretically is
complex, but is similar to a viscous drag force and is proportional to the ion velocity in the
low energy regime. The energy loss by the incident ions is dissipated through the electron
cloud into thermal vibrations of the target.

Modelling ion implantation is done through Gaussian (symmetrical), Pearson

(amorphous implant) and SIMS Verified Dual Pearson (SVDP) methods.

In the VLSI device design, accurate prediction of the doping profiles resulting from
ion implantation, a standard method for doping impurities in VLSI processes is essential,
which can be obtained by analytical expressions for the secondary ion mass spectrometry
(SIMS) data of the ion implantation profiles, and these analytical formulae are used to
compile an ion implantation profile database. The profiles of arbitrary implantation
conditions can be generated by using interpolated parameter values. This whole process is
called modelling and is done by the methods described above.
❖ Simple Gaussian Method
This is the simplest approximation to an ion implanted profile.
 Figure 3 a.) Explains the total path length R is longer than
the projected range Rp and b .) Explains that the stopped
atom distribution is two-dimensional Gaussian.

The Gaussian model is very good for lower energy but for higher energy the profile
is skewed. Here, we'll discuss the '2' types of skewness.

➢ Positive skewness
■ Distribution is shifted away from the surface due to channeling which we'll
discuss in the coming sections and this effect is very common for heavy
elements at low energies.

➢ Negative skewness
■ Distribution is shifted towards the surface due to back scattering which is
common for light elements at high energy as shown in the figure 4.

Figure 4
❖ Pearson model
When ions are implanted into a crystalline substrate, the crystal structure may be
completely destroyed and can form a continuous amorphous layer under some conditions.
When a doping profile is obtained, the basic information about how the implementation took
place can be expressed in terms of moments. For instance, the first moment corresponds to
the average depth reached by the ions, the second moment corresponds to this standard
deviation expressing the degree of spreading, and the third moment corresponds to the
skewness. where more skewness gives more asymmetric profiles, the fourth moment
corresponds to the kurtosis which describes how sharp the profile is in the vicinity of the
peak.

These moment parameters provide basic information about the distribution. Higher
order moments which also describe the distribution but they constitute information about
errors at the lower concentrations.

❖ Dual Pearson standard function

As real ion implementation profiles are often asymmetrical, to express the asymmetry
of distributions, a joined half Gaussian profile consisting of two Gaussian profiles having
different values of second order moments are joined at the peak position.

A Gaussian distribution cannot express asymmetric profiles. Although a joined half

Gaussian can provide a good representation of the peak depth and the neighborhood of the
peak, it cannot represent the profiles that decrease exponentially towards the surface. A
strong limitation of joining half Gaussian profiles is that the exponent terms of the equation
are having high dependency on the square of the distance. This makes the analysis difficult
for the exponential functions which are at the low concentration region near the surface.
That is the reason why these models are not used for database construction. Although they
are not used for database construction, they can represent many profile types. They are
simpler and easier to work with when compared to Pearson models and are highly used in
data analysis applications.

❖ Channeling Effect in Ion Implantation

This effect may add uncertainty in the depth. This leads to an underestimation of the
implantation depth for ions implanted into any crystalline target material. Ion channeling
happens when the incident direction of an ion beam is aligned with a particular axis of the
crystal. The ions can travel through channels between atom rows and planes due to the
interaction between the ion which is charged and the potential induced by the target atoms.
This results in a decrease in the number of collisions that can happen and an increment in the
implantation depth.

The parameters that are considered in ion channeling are the angle of the ion tray
with respect to the crystal orientation and the ion energy for a particular crystalline axis, only
ions incoming within a certain angle and penetrate the channeling rows, where this angle is
called critical angle. If the ion velocity is reduced, channeling does not happen anymore
which is called critical ion energy.

❖ Tilt angle dependence

 The tilt angle is defined as the angle between the incident ion beam direction and the
normal direction of the wafer. Boron distribution is very sensitive even for a small variation
in the tilt angle.

❖ Screen oxide thickness

The intensity of ion scattering and the degree of randomization of the directions of
the implanted ions is done through observations of a series of boron profiles measured by
Secondary Ion Mass Spectroscopy (SIMS) analysis. The effectiveness of the screen oxide
layer plays a very crucial role in randomizing the directions of implanted ions which is
strongly dependent on the correlation between ion energy and oxide thickness. Ion scattering
by the oxide layer can cause enhanced channeling and a deeper profile depth.

❖ Binary Collision Approximation

This method is used to enable efficient simulation of the penetration depth and
defects produced by energetic ions in the solids. In this method, the ion is approximated to
travel through a material by experiencing a sequence of independent binary collisions with
the sample atoms and is assumed to travel in a straight path, experiencing electronic stopping
power but losing no energy in collisions with nuclei. The binary collision approximation can
also be extended to simulate dynamic composition changes of a material due to prolonged
ion irradiation. In the BCA approach, a single collision between the incoming ion and a
target atom (nucleus) is treated by solving the classical scattering integral between two
colliding particles for the impact parameter of the incoming ion. Solution of the integral
gives the scattering angle of the ion as well as its energy loss to the sample atoms, and hence
what the energy is after the collision compared to before it. The scattering integral is defined
in the centre-of-mass coordinate system (two particles reduced to one single particle with one
interatomic potential) and relates the angle of scatter with the interatomic potential.
 (Source: Wikipedia)

❖ Damage Accumulation Model

The present model includes dynamic processes of the transformation from crystalline
to amorphous state as ion implantation proceeds. Each pseudo-projectile in the simulation
represents a portion of the real dose x, where N is the number of projectiles. Pseudo
projectile is x/N. The deposited energy is accounted for at each grid point of the target and
accumulated with the number of projectiles. As the implantation proceeds, deposited energy
increases and the crystalline structure gradually turns into an amorphous structure. This is
quantified by the Amorphization Probability Function.

❖ Statistical Modelling
In order to reduce calculation time and improve statistical quality of simulated
profiles, ATHENA implements a three-dimensional rare event algorithm. An implantation
profile can differ significantly in concentration values across implantation depth. Low
concentrations in the profile are due to low probability of implanted species (rare events) to
reach that point in space. Therefore, the number of cascades simulated to get a good
statistics profile depends on the desired number of orders of magnitude of accuracy. Even in
real experiments, depending on device size, implant distributions below some threshold
concentration value could exhibit significant statistical noise.

(Source: ATHENA Manual)

 Chapter 4
INSTALLATION OF SILVACO TCAD
❖ TCAD:
TCAD is a branch of electronic design automation that models Semiconductor Fabrication and
semiconductor device operation. Today much of the development of semiconductor devices is done
by computer modelling. The approach is called TCAD modelling, TCAD tool reduces the
development cost and time. The modelling of fabrication is termed as process TCAD, while
modelling of device operation is termed as Device TCAD. In this lab, we’re using tools provided by
Silvaco.

❖ SILVACO TCAD:

● Device Simulation:
This is done by the following process.

· Victory Device

· Atlas

It can execute physics-based device simulations to predict and understand device performance.

● Process Simulation:

Process simulation is crucial to develop new technologies, as well as maintain existing

semiconductor processes. Virtualizing the manufacturing process allows organizations to maintain a
“digital twin” of their semiconductor process. Changes in process can be well understood;
maximizing device performance, increasing manufacturing yield, while minimizing the number of
engineering cycles and cycle time. It is done by using

· Victory process

· Athena

❖ Process Flow in Silvaco TCAD:

❖ TOOL INSTALLATION PROCEDURE:

● Installation of SILVACO tool requires the following files:

1. licensed file

2. RPC.sflm file

3. TCAD crack

The minimum requirement for downloading the silvaco 2018 version is it should be 64-bit

processor and minimum 4GB RAM.

Step 1: Download the latest [2018] Silvaco Tcad

Step 2: Extract and Install Silvaco Tcad 2018

Step 3: Mark Install license serve and click ‘next’.

Step 4: After installation Copy Machine ID from auto generated web page of default browser and
paste it to License Host ID in license file given inside the crack folder.
Step 5: Go to task manager and End task rpc.sflmreserver.exe

Press ctrl+alt+dlt and select task manager. end task if you are windows & user then select Task by
all user.

Step 6: Go to crack folder and copy rpc.sflmreserved and paste it to your installation directory C:\
sedatools\lib\rpc.s fmserverd\8.2.12.R\x86-n
Step 7: Run this new rpc.sflmreserved as administrator from installation directory above.

Step 8: Login previously generated web page by giving password you given before installation and
select add new license from saved .
Step 9: Enter the selected password then we are good to go.

Step 10: Browse and select license file you modified by your machine id. press agree.
 Chapter 5
PROCESS SIMULATION-ION
IMPLANTATION
❖ ATHENA-Process Simulation:
It is a simulator that provides general capabilities for numerical, physically-based, two-dimensional
simulation of semiconductor processing. ATHENA has a modular architecture that has the following
licensable tools and extensions. This tool performs structure initialization and manipulation, and
provides basic deposition and etch facilities.

❖ Features provided for Ion-Implantation:

• Experimentally verified Pearson and dual Pearson analytical models.

• Extended low energy and high energy implant parameter tables.

• Binary Collision Approximation Monte Carlo calculations for crystalline and amorphous
materials.

• Universal tilt and rotation capability for both analytic and Monte Carlo calculations
 ❖ Problem Statement:
a. Steps to be followed to carry out ion implantation in Athena-Silvaco

b. Channeling dependence on tilt angle, oxide thickness.

c. Pre-damage of substrate surface before ion implantation

❖ Tools Involved:
● Deckbuild
● Athena
● Tonyplot

a.Steps to be followed to carry out ion implantation in

Athena-Silvaco:
1. Deckbuild is opened and the simulator is set to Athena using the command go Athena.

2. Initialize Mesh.

● Mesh is a rectangular grid. It is required as the simulation time and accuracy depend on how
fine the grid structure is.
● Go to commands -> Mesh define
● The location helps to initialize the coordinates of x-axis and y-axis. The spacing option is
used to determine the gap between the grid. After providing the coordinates and spacing
press ‘insert’ to form the grid.

● When the write is pressed, the command gets written in the deckbuild editor window.
● There are two types of grids i) Uniform grid ii) non-uniform grid
● Uniform grid has equal spacing between each grid. But a non-uniform grid is useful for
critical processes like ion-implantation, etching etc.

❖ Ion-Implantation Window:
 Fig:Ion implantation window

3. For ion implantation go to command ->process->implant.

· Select the impurity to be implanted.

· Dose determines the no. of ions that hits the substrate material.

· Energy (KeV) is the energy with which the ions enter the material.

· At how much angle the ion enters the materials is given by tilt
 · Specifying the rotation angle makes sense only for non-zero tilt
angles. Zero rotation means that the ion beam vector lies in the plane
parallel to the 2D simulation plane. 90° rotation means that the ion beam
vector lies in the plane perpendicular to the simulation plane

· Material can be crystalline or amorphous.

· Model determines by which method the moments (Range, straggle,

skewness, kurtosis) are calculated.

· The different damages such as point defects, <311> clusters, dislocation

loops caused by ion implantation can be modelled by the tool.

b.Tilt angle dependance on channeling:

● Code:

go athena

# Tilt angle =0

#Grid initialization

line x loc = 0.0 spac=0.1

line x loc = 1.0 spac=0.1

line y loc = 0 spac=0.01

line y loc = 0.6 spac=0.01

#Initialisation of substrate material, default=silicon

init
implant boron energy=30 dose=2e13 tilt=0 rotation=0 print.mom

#print.mom extracts the calculated moments and saves in a separate file

struct outfile=lab_1.str

#Helps to view the simulation results

#Tilt angle=7

line x loc = 0.0 spac=0.1

line x loc = 1.0 spac=0.1

line y loc = 0 spac=0.01

line y loc = 0.6 spac=0.01

init one.d

implant boron energy=30 dose=2e13 tilt=7 rotation=0 print.mom

struct outfile=lab_2.str

#Plots the results using tonyplot by combining the two results

tonyplot -overlay lab_*.str

 Fig: Depth Vs Boron Concentration in log scale

Fig: Depth Vs Boron Concentration in linear scale

● Explanation:

· Lab_1.dat-Plot with tilt angle=0

· Lab_2.dat-Plot with tilt angle=7

· .dat files are obtained using extract command.

· As the tilt angle increases, we’re getting a gaussian curve indicating

 the improvement in channeling.

b.Effect of screen oxide on Channeling:

● Code:

go athena

#Without screen oxide

line x loc = 0.0 spac=0.1

line x loc = 1.0 spac=0.1

line y loc = 0 spac=0.01

line y loc = 0.6 spac=0.01

init

implant boron energy=30 dose=2.e13 tilt=0 rotation=0 print.mom

#Extract command is used to obtain the values from the .str file. For a 2D
profile we’re using curve ()

which extracts SIMS profile (concentration Vs depth) and it is stored in .dat

file

extract name="p1" curve (depth,impurity="Boron" material="Silicon" \

mat.occno=1 x.val=0.0) outfile="lab_1.dat"

#A layer of screen-oxide is used

line x loc = 0.0 spac=0.1

line x loc = 1.0 spac=0.1

line y loc = 0 spac=0.01

line y loc = 0.6 spac=0.01

init

#A dry oxide is diffused for a time of 8 min at a temperature of 900 C (Ref:

Fig.lab_2.str)

diffuse time=8 temp=900 dry

struct outf=lab_2.str

#Extracts the thickness of oxide at a ‘x’ co-ordinate=0 and stored in variable

tox8

extract name="tox8" thickness material="SiO~2" mat.occno=1 x.val=0.0

#The effect of s.oxide parameter is that it represents ion implantation through

a thin surface oxide layer

implant boron energy=30 dose=2.e13 tilt=0 rotation=0 s.oxide=1.0e-

04*$tox8 print.mom

extract name="p1" curve(depth,impurity="Boron" material="Silicon" \

mat.occno=1 x.val=0.0) outfile="lab_2.dat"

tonyplot -overlay lab_1.dat lab_2.dat

tonyplot lab_2.str
 Fig: Deposition of oxide using dry oxidation

Fig: Depth Vs Boron Concentration

● Explanation:

· Lab_1.dat-Plot with screen oxide=0

· Lab_2.dat-Plot with screen oxide=1.0e-04*54.144231696145

· Channeling is improved by using screen oxide through which

 implantation occurs as it randomizes the ion flux.

c.Pre-damage of crystal surface by implanting

heavy ion prior to ion-implantation:
● Code:

go athena

# Part I - first implant arsenic, then boron

line x loc = 0.0 spacing=0.005

line x loc = 0.6 spacing=0.005

line y loc = 0 spacing = 0.005

line y loc = 0.3 spacing = 0.005

init silicon

#A barrier of thickness is 0.001 is deposited

deposit barrier thick=0.001

#The barrier is etched of window 0.01 thickness at the center of substrate i.e.,
0.3um

etch start x=0.295 y=-0.001

etch cont x=0.305 y=-0.001

etch cont x=0.295 y=0.000

etch done x=0.305 y=0.000

#Arsenic is the heavy ion used for damaging the crystal surface

#n.ion indicates the no. of ion trajectories used for calculation of moments in
BCA model (Binary Collision Approximation)

implant sampling arsenic energy=12 dose=1e13 bca tilt=0 rotation=0

n.ion=10000 impact.point=0.5

#Impact. point helps in calculating the point at which the ion beam enters the
silicon substrate

X=left (leftmost co-ordinate of x axis) + impact.point *L(length of the

substrate)=0+0.5*0.6=0.3

implant sampling boron energy=12 dose=4e13 bca tilt=0 rotation=0

n.ion=10000 \ impact.point=0.5

structure outfile=lab_1.str

# Part II - Only Boron

line x loc = 0.0 spacing=0.005

line x loc = 0.6 spacing=0.005

line y loc = 0 spacing = 0.005

line y loc = 0.3 spacing = 0.005

init silicon

deposit barrier thick=0.001

etch start x=0.295 y=-0.001

etch cont x=0.305 y=-0.001

etch cont x=0.295 y=0.000

etch done x=0.305 y=0.000

implant sampling boron energy=12 dose=4e13 bca tilt=0 rotation=0

n.ion=10000 \ impact.point=0.5

structure outfile=lab_2.str

#’add’ helps in providing both the graphs in same window

tonyplot lab_1.str -add lab_2.str

Fig: Arsenic implantation

Fig: Plot depicting the first implantation of boron followed by Arsenic

Fig: Implantation of only boron

● Explanation:

· Arsenic, a heavier ion than boron, creates significant damage in the

silicon. As a result, the crystal integrity of silicon is reduced, which in
turn reduces the boron channeling.